[AMDGPU] Tune perfhint analysis to account access width

[rampitec]

Summary

A function with less memory instructions but wider access
is the same as a function with more but narrower accesses
in terms of memory boundness. In fact the pass would give
different answers before and after vectorization without
this change.

[rampitec]

Rebased.

[foad]

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

220–221

The "InstCount" names seem like a lie since we are no longer counting the number of instructions, but I don't have a better idea.

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

220–221

Yes, I also didn't come up with a better name. In fact it always was a lie since IR instruction is not a HW instruction. All of that was inspired by the desire to move pass later in the pipeline and then I realized to preserve its behavior I need to adjust it for LD/ST combining. But the metric name has drifred even more from reality as it used to be.

[yaxunl]

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

220–221

How about Count => Cost ?

Also, we need to do the same change to IAMInstCoount and LSMInstCount to keep the way to calculate the cost consistent.

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

220–221

Thanks, cost sounds better.

[rampitec]

• Renamed variables to read 'cost' instead of 'count'.
• Adjusted IAM and LSM costs accordingly.

[arsenm]

I still think this really should be a machine analysis

[rampitec]

In D105651#2881154, @arsenm wrote:

I still think this really should be a machine analysis

Probably, but that's really a completely separate change.

[rampitec]

ping

[yaxunl]

LGTM. Thanks.

llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp

 AMDGPUPerfHintAnalysis::FuncInfo *AMDGPUPerfHint::visit(const Function &F) {
   AMDGPUPerfHintAnalysis::FuncInfo &FI = FIM[&F];
 
   LLVM_DEBUG(dbgs() << "[AMDGPUPerfHint] process " << F.getName() << '\n');
 
   for (auto &B : F) {
     LastAccess = MemAccessInfo();
     for (auto &I : B) {
-      if (getMemoryInstrPtr(&I)) {
+      if (const Value *Ptr = getMemoryInstrPtr(&I)) {
         if (isIndirectAccess(&I))
           ++FI.IAMInstCount;
         if (isLargeStride(&I))
           ++FI.LSMInstCount;
-        ++FI.MemInstCount;
-        ++FI.InstCount;
+        unsigned Size = divideCeil(
+            Ptr->getType()->getPointerElementType()->getPrimitiveSizeInBits(),
+            32);
+        FI.MemInstCount += Size;
+        FI.InstCount += Size;
         continue;
       }
       if (auto *CB = dyn_cast<CallBase>(&I)) {
         Function *Callee = CB->getCalledFunction();
         if (!Callee || Callee->isDeclaration()) {
           ++FI.InstCount;
           continue;
         }

llvm/test/CodeGen/AMDGPU/perfhint.ll

bb:
   %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
   %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
   store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
   %tmp6 = add nuw nsw i64 %tmp2, 1
   %tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
   %tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
   %tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
   store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
-  %tmp10 = add nuw nsw i64 %tmp2, 2
-  %tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
-  %tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
-  %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
-  store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
-  %tmp14 = add nuw nsw i64 %tmp2, 3
-  %tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
-  %tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
-  %tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
-  store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_large_stride:
 ; GCN: MemoryBound: 0
 ; GCN: WaveLimiterHint : 1
 define amdgpu_kernel void @test_large_stride(i32 addrspace(1)* nocapture %arg) {
 bb: