[PowerPC] Fix addi-load bias scheduling heuristics

[qiucf]

Summary

1. LI/LI8 are also some form of ADDI
2. Fixed the function to check it, the second one should be mayLoad, not !isADDI

According to generated inc file, mtctr is also seen as mayLoad.

[jsji]

llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp

27

This heuristics was intended for the addi in loop induction variable calculation, not for all addi.
So LI/LI8 shouldn't be counted.

Do you have any specific example that we have LI/LI8 in loop and should schedule them earlier?

173

The heuristics was to try to schedule addi as early as possible, not necessary just before mayload instructions.

[qiucf]

Thanks for the review and explaining the background. Besides changes here, I was trying to refactor tryCandidate to return bool, so that target hooks may reuse it better. However, we still cannot if (GenericScheduler::tryCandidate(...)) return ... since that will not be not an NFC. However that will make this heuristic hack in higher priority. I need to evaluate it and see if we should proceed.

llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp

27

Ah, thanks for the background. I was not clear about it. So LI/LI8 should be here.

llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp

 static cl::opt<bool>
     EnableAddiHeuristic("ppc-postra-bias-addi",
                         cl::desc("Enable scheduling addi instruction as early"
                                  "as possible post ra"),
                         cl::Hidden, cl::init(true));
 
 static bool isADDIInstr(const GenericScheduler::SchedCandidate &Cand) {
   return Cand.SU->getInstr()->getOpcode() == PPC::ADDI ||
-         Cand.SU->getInstr()->getOpcode() == PPC::ADDI8;
+         Cand.SU->getInstr()->getOpcode() == PPC::ADDI8 ||
+         Cand.SU->getInstr()->getOpcode() == PPC::LI ||
+         Cand.SU->getInstr()->getOpcode() == PPC::LI8;
 }
 
 bool PPCPreRASchedStrategy::biasAddiLoadCandidate(SchedCandidate &Cand,
                                                   SchedCandidate &TryCand,
                                                   SchedBoundary &Zone) const {
   if (DisableAddiLoadHeuristic)
     return false;
 
-  SchedCandidate &FirstCand = Zone.isTop() ? TryCand : Cand;
-  SchedCandidate &SecondCand = Zone.isTop() ? Cand : TryCand;
-  if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) {
-    TryCand.Reason = Stall;
-    return true;
-  }
-  if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) {
-    TryCand.Reason = NoCand;
-    return true;
+  if (Zone.isTop()) {
+    if (tryGreater(isADDIInstr(TryCand) && Cand.SU->getInstr()->mayLoad(),
+                  isADDIInstr(Cand) && TryCand.SU->getInstr()->mayLoad(),
+                  TryCand, Cand, Stall))
+      return TryCand.Reason != NoCand;
+  } else {
+    if (tryLess(isADDIInstr(TryCand) && Cand.SU->getInstr()->mayLoad(),
+                isADDIInstr(Cand) && TryCand.SU->getInstr()->mayLoad(),
+                TryCand, Cand, Stall))
+      return TryCand.Reason != NoCand;
   }
 
   return false;
 }
 
 bool PPCPreRASchedStrategy::tryCandidate(SchedCandidate &Cand,
                                          SchedCandidate &TryCand,
                                          SchedBoundary *Zone) const {
bool PPCPreRASchedStrategy::tryCandidate(SchedCandidate &Cand,
   return TryCand.Reason != NoCand;
 }
 
 bool PPCPostRASchedStrategy::biasAddiCandidate(SchedCandidate &Cand,
                                                SchedCandidate &TryCand) const {
   if (!EnableAddiHeuristic)
     return false;
 
-  if (isADDIInstr(TryCand) && !isADDIInstr(Cand)) {
-    TryCand.Reason = Stall;
-    return true;
+  if (tryGreater(isADDIInstr(TryCand) && Cand.SU->getInstr()->mayLoad(),
+                 isADDIInstr(Cand) && TryCand.SU->getInstr()->mayLoad(),
+                 TryCand, Cand, Stall)) {
+    return TryCand.Reason != NoCand;
   }
   return false;
 }
 
 bool PPCPostRASchedStrategy::tryCandidate(SchedCandidate &Cand,
                                           SchedCandidate &TryCand) {
   // From PostGenericScheduler::tryCandidate
 

llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll

 ; CHECK-64-NEXT:    rlwinm 3, 3, 2, 28, 29
 ; CHECK-64-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-64-NEXT:    mtfprwz 0, 3
 ; CHECK-64-NEXT:    xscvuxddp 1, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: conv2dlbTestuiVar:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -32
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-NEXT:    addi 4, 1, -32
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    lwzx 3, 4, 3
 ; CHECK-32-NEXT:    stw 3, -4(1)
 ; CHECK-32-NEXT:    addi 3, 1, -4
 ; CHECK-32-NEXT:    lfiwzx 0, 0, 3
 ; CHECK-32-NEXT:    xscvuxddp 1, 0
 ; CHECK-32-NEXT:    blr
 entry:

 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %f, i32 %el
   ret <4 x float> %vecins
 }
 define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {
 ; CHECK-64-LABEL: insertVarI:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stwx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: insertVarI:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stwx 3, 5, 4
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el
   ret <4 x i32> %vecins
 }

llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32
 
 define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
 ; CHECK-64-LABEL: test1:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vextublx 3, 3, 2
 ; CHECK-64-NEXT:    clrldi 3, 3, 56
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test1:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 3, 28
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lbzx 3, 4, 3
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %a, i32 %index
   ret i8 %vecext
 }
 
 define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
 ; CHECK-64-LABEL: test2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vextublx 3, 3, 2
 ; CHECK-64-NEXT:    extsb 3, 3
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test2:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 3, 28
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lbzx 3, 4, 3
 ; CHECK-32-NEXT:    extsb 3, 3
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %a, i32 %index
   ret i8 %vecext
 }
 
 define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
 ; CHECK-64-LABEL: test3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    rlwinm 3, 3, 1, 28, 30
 ; CHECK-64-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-64-NEXT:    clrldi 3, 3, 48
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test3:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lhzx 3, 4, 3
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %a, i32 %index
   ret i16 %vecext
 }
 
 define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
 ; CHECK-64-LABEL: test4:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    rlwinm 3, 3, 1, 28, 30
 ; CHECK-64-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-64-NEXT:    extsh 3, 3
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lhax 3, 4, 3
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %a, i32 %index
   ret i16 %vecext
 }
 
 define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
 ; CHECK-64-LABEL: test5:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    rlwinm 3, 3, 2, 28, 29
 ; CHECK-64-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test5:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lwzx 3, 4, 3
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %a, i32 %index
   ret i32 %vecext
 }
 
 define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
 ; CHECK-64-LABEL: test6:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    rlwinm 3, 3, 2, 28, 29
 ; CHECK-64-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-64-NEXT:    extsw 3, 3
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test6:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lwzx 3, 4, 3
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %a, i32 %index
   ret i32 %vecext
 }
 

llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32
 
 define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) {
 ; CHECK-64-LABEL: test_add1:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vextublx 3, 3, 2
 ; CHECK-64-NEXT:    add 3, 3, 4
 ; CHECK-64-NEXT:    clrldi 3, 3, 56
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test_add1:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 3, 28
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lbzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
 ; CHECK-32-NEXT:    clrlwi 3, 3, 24
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %a, i32 %index
   %conv = zext i8 %vecext to i32
   %conv1 = zext i8 %c to i32
   %add = add nuw nsw i32 %conv, %conv1
   %conv2 = trunc i32 %add to i8
   ret i8 %conv2
 }
 
 define signext i8 @test_add2(<16 x i8> %a, i32 signext %index, i8 signext %c) {
 ; CHECK-64-LABEL: test_add2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vextublx 3, 3, 2
 ; CHECK-64-NEXT:    add 3, 3, 4
 ; CHECK-64-NEXT:    extsb 3, 3
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test_add2:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 3, 28
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lbzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
 ; CHECK-32-NEXT:    extsb 3, 3
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %a, i32 %index
   %conv3 = zext i8 %vecext to i32

 ; CHECK-64-NEXT:    rlwinm 3, 3, 1, 28, 30
 ; CHECK-64-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-64-NEXT:    add 3, 3, 4
 ; CHECK-64-NEXT:    clrldi 3, 3, 48
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test_add3:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lhzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
 ; CHECK-32-NEXT:    clrlwi 3, 3, 16
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %a, i32 %index
   %conv = zext i16 %vecext to i32

 ; CHECK-64-NEXT:    rlwinm 3, 3, 1, 28, 30
 ; CHECK-64-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-64-NEXT:    add 3, 3, 4
 ; CHECK-64-NEXT:    extsh 3, 3
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test_add4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 1, 28, 30
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lhzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
 ; CHECK-32-NEXT:    extsh 3, 3
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %a, i32 %index
   %conv5 = zext i16 %vecext to i32

 ; CHECK-64-NEXT:    rlwinm 3, 3, 2, 28, 29
 ; CHECK-64-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-64-NEXT:    add 3, 3, 4
 ; CHECK-64-NEXT:    clrldi 3, 3, 32
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test_add5:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lwzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %a, i32 %index
   %add = add i32 %vecext, %c
   ret i32 %add
 }
 
 define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) {
 ; CHECK-64-LABEL: test_add6:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    rlwinm 3, 3, 2, 28, 29
 ; CHECK-64-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-64-NEXT:    add 3, 3, 4
 ; CHECK-64-NEXT:    extsw 3, 3
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test_add6:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 3, 2, 28, 29
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    lwzx 3, 5, 3
 ; CHECK-32-NEXT:    add 3, 3, 4
 ; CHECK-32-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %a, i32 %index
   %add = add nsw i32 %vecext, %c
   ret i32 %add

llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-64
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-32
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-64-P10
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff -vec-extabi -mcpu=pwr10 < %s | FileCheck %s -check-prefix=CHECK-32-P10
 
 ; Byte indexed
 
 define <16 x i8> @testByte(<16 x i8> %a, i64 %b, i64 %idx) {
 ; CHECK-64-LABEL: testByte:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    clrldi 4, 4, 60
+; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stbx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testByte:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    clrlwi 3, 6, 28
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stbx 4, 5, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testByte:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    vinsblx 2, 4, 3
entry:
   ret <16 x i8> %vecins
 }
 
 ; Halfword indexed
 
 define <8 x i16> @testHalf(<8 x i16> %a, i64 %b, i64 %idx) {
 ; CHECK-64-LABEL: testHalf:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    rlwinm 4, 4, 1, 28, 30
+; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    sthx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testHalf:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 6, 1, 28, 30
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    sthx 4, 5, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testHalf:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    slwi 4, 4, 1
entry:
   ret <8 x i16> %vecins
 }
 
 ; Word indexed
 
 define <4 x i32> @testWord(<4 x i32> %a, i64 %b, i64 %idx) {
 ; CHECK-64-LABEL: testWord:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stwx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testWord:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 6, 2, 28, 29
+; CHECK-32-NEXT:    addi 5, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stwx 4, 5, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testWord:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    slwi 4, 4, 2
entry:
   ret <4 x i32> %vecins2
 }
 
 ; Doubleword indexed
 
 define <2 x i64> @testDoubleword(<2 x i64> %a, i64 %b, i64 %idx) {
 ; CHECK-64-LABEL: testDoubleword:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stdx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDoubleword:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    add 5, 6, 6
entry:
   ret <2 x i64> %vecins
 }
 
 ; Float indexed
 
 define <4 x float> @testFloat1(<4 x float> %a, float %b, i32 zeroext %idx1) {
 ; CHECK-64-LABEL: testFloat1:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-DAG:     rlwinm 3, 4, 2, 28, 29
-; CHECK-64-DAG:     addi 4, 1, -16
+; CHECK-64-NEXT:    rlwinm 3, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 4, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stfsx 1, 4, 3
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloat1:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    rlwinm 3, 4, 2, 28, 29
entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 %idx1
   ret <4 x float> %vecins
 }
 
 define <4 x float> @testFloat2(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testFloat2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lwz 6, 0(3)
-; CHECK-64-DAG:     rlwinm 4, 4, 2, 28, 29
-; CHECK-64-DAG:     addi 7, 1, -32
+; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 7, 1, -32
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stwx 6, 7, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
 ; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    lxv 0, -32(1)
 ; CHECK-64-NEXT:    lwz 3, 1(3)
 ; CHECK-64-NEXT:    stxv 0, -16(1)
 ; CHECK-64-NEXT:    stwx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloat2:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lwz 6, 0(3)
-; CHECK-32-NEXT:    addi 7, 1, -32
 ; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-32-NEXT:    addi 7, 1, -32
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
 ; CHECK-32-NEXT:    stwx 6, 7, 4
 ; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    lxv 0, -32(1)
 ; CHECK-32-NEXT:    lwz 3, 1(3)
 ; CHECK-32-NEXT:    stxv 0, -16(1)
 ; CHECK-32-NEXT:    stwx 3, 4, 5
entry:
   %vecins2 = insertelement <4 x float> %vecins, float %3, i32 %idx2
   ret <4 x float> %vecins2
 }
 
 define <4 x float> @testFloat3(<4 x float> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testFloat3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lis 6, 1
-; CHECK-64-DAG:         rlwinm 4, 4, 2, 28, 29
-; CHECK-64-DAG:    addi 7, 1, -32
+; CHECK-64-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-64-NEXT:    addi 7, 1, -32
 ; CHECK-64-NEXT:    lwzx 6, 3, 6
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stwx 6, 7, 4
 ; CHECK-64-NEXT:    li 4, 1
 ; CHECK-64-NEXT:    lxv 0, -32(1)
 ; CHECK-64-NEXT:    rldic 4, 4, 36, 27
 ; CHECK-64-NEXT:    lwzx 3, 3, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 2, 28, 29
 ; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 0, -16(1)
 ; CHECK-64-NEXT:    stwx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testFloat3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lis 6, 1
-; CHECK-32-NEXT:    addi 7, 1, -32
 ; CHECK-32-NEXT:    rlwinm 4, 4, 2, 28, 29
+; CHECK-32-NEXT:    addi 7, 1, -32
 ; CHECK-32-NEXT:    rlwinm 5, 5, 2, 28, 29
 ; CHECK-32-NEXT:    lwzx 6, 3, 6
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    stwx 6, 7, 4
 ; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    lxv 0, -32(1)
 ; CHECK-32-NEXT:    lwz 3, 0(3)
 ; CHECK-32-NEXT:    stxv 0, -16(1)
entry:
   ret <4 x float> %vecins2
 }
 
 ; Double indexed
 
 define <2 x double> @testDouble1(<2 x double> %a, double %b, i32 zeroext %idx1) {
 ; CHECK-64-LABEL: testDouble1:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64:         rlwinm 3, 4, 3, 28, 28
+; CHECK-64-NEXT:    rlwinm 3, 4, 3, 28, 28
 ; CHECK-64-NEXT:    addi 4, 1, -16
 ; CHECK-64-NEXT:    stxv 34, -16(1)
 ; CHECK-64-NEXT:    stfdx 1, 4, 3
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDouble1:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    rlwinm 3, 5, 3, 28, 28
+; CHECK-32-NEXT:    addi 4, 1, -16
 ; CHECK-32-NEXT:    stxv 34, -16(1)
 ; CHECK-32-NEXT:    stfdx 1, 4, 3
 ; CHECK-32-NEXT:    lxv 34, -16(1)
 ; CHECK-32-NEXT:    blr
 ;
 ; CHECK-64-P10-LABEL: testDouble1:
 ; CHECK-64-P10:       # %bb.0: # %entry
 ; CHECK-64-P10-NEXT:    extsw 4, 4
 ; CHECK-64-P10-NEXT:    mffprd 3, 1
 ; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
 ; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testDouble1:
 ; CHECK-32-P10:       # %bb.0: # %entry
-; CHECK-32-P10-DAG:     addi 4, 1, -16
-; CHECK-32-P10-DAG:     rlwinm 3, 5, 3, 28, 28
+; CHECK-32-P10-NEXT:    rlwinm 3, 5, 3, 28, 28
+; CHECK-32-P10-NEXT:    addi 4, 1, -16
 ; CHECK-32-P10-NEXT:    stxv 34, -16(1)
 ; CHECK-32-P10-NEXT:    stfdx 1, 4, 3
 ; CHECK-32-P10-NEXT:    lxv 34, -16(1)
 ; CHECK-32-P10-NEXT:    blr
 entry:
   %vecins = insertelement <2 x double> %a, double %b, i32 %idx1
   ret <2 x double> %vecins
 }
 
 define <2 x double> @testDouble2(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testDouble2:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    ld 6, 0(3)
-; CHECK-64-DAG:         rlwinm 4, 4, 3, 28, 28
-; CHECK-64-DAG:    addi 7, 1, -32
+; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-64-NEXT:    addi 7, 1, -32
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stdx 6, 7, 4
 ; CHECK-64-NEXT:    li 4, 1
 ; CHECK-64-NEXT:    lxv 0, -32(1)
 ; CHECK-64-NEXT:    ldx 3, 3, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28
 ; CHECK-64-NEXT:    addi 5, 1, -16
 ; CHECK-64-NEXT:    stxv 0, -16(1)
 ; CHECK-64-NEXT:    stdx 3, 5, 4
 ; CHECK-64-NEXT:    lxv 34, -16(1)
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: testDouble2:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    lfd 0, 0(3)
-; CHECK-32-NEXT:    addi 6, 1, -32
 ; CHECK-32-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-32-NEXT:    addi 6, 1, -32
 ; CHECK-32-NEXT:    stxv 34, -32(1)
 ; CHECK-32-NEXT:    rlwinm 5, 5, 3, 28, 28
 ; CHECK-32-NEXT:    stfdx 0, 6, 4
 ; CHECK-32-NEXT:    lxv 0, -32(1)
 ; CHECK-32-NEXT:    lfd 1, 1(3)
 ; CHECK-32-NEXT:    addi 3, 1, -16
 ; CHECK-32-NEXT:    stxv 0, -16(1)
 ; CHECK-32-NEXT:    stfdx 1, 3, 5

 ; CHECK-64-P10-NEXT:    extsw 4, 5
 ; CHECK-64-P10-NEXT:    rlwinm 4, 4, 3, 0, 28
 ; CHECK-64-P10-NEXT:    vinsdlx 2, 4, 3
 ; CHECK-64-P10-NEXT:    blr
 ;
 ; CHECK-32-P10-LABEL: testDouble2:
 ; CHECK-32-P10:       # %bb.0: # %entry
 ; CHECK-32-P10-NEXT:    lfd 0, 0(3)
-; CHECK-32-P10-DAG:     addi 6, 1, -32
-; CHECK-32-P10-DAG:     rlwinm 4, 4, 3, 28, 28
+; CHECK-32-P10-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-32-P10-NEXT:    addi 6, 1, -32
 ; CHECK-32-P10-NEXT:    stxv 34, -32(1)
 ; CHECK-32-P10-NEXT:    rlwinm 5, 5, 3, 28, 28
 ; CHECK-32-P10-NEXT:    stfdx 0, 6, 4
 ; CHECK-32-P10-NEXT:    lxv 0, -32(1)
 ; CHECK-32-P10-NEXT:    lfd 1, 1(3)
 ; CHECK-32-P10-NEXT:    addi 3, 1, -16
 ; CHECK-32-P10-NEXT:    stxv 0, -16(1)
 ; CHECK-32-P10-NEXT:    stfdx 1, 3, 5
entry:
   %vecins2 = insertelement <2 x double> %vecins, double %3, i32 %idx2
   ret <2 x double> %vecins2
 }
 
 define <2 x double> @testDouble3(<2 x double> %a, i8* %b, i32 zeroext %idx1, i32 zeroext %idx2) {
 ; CHECK-64-LABEL: testDouble3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    lis 6, 1
-; CHECK-64-DAG:     rlwinm 4, 4, 3, 28, 28
-; CHECK-64-DAG:     addi 7, 1, -32
+; CHECK-64-NEXT:    rlwinm 4, 4, 3, 28, 28
+; CHECK-64-NEXT:    addi 7, 1, -32
 ; CHECK-64-NEXT:    ldx 6, 3, 6
 ; CHECK-64-NEXT:    stxv 34, -32(1)
 ; CHECK-64-NEXT:    stdx 6, 7, 4
 ; CHECK-64-NEXT:    li 4, 1
 ; CHECK-64-NEXT:    lxv 0, -32(1)
 ; CHECK-64-NEXT:    rldic 4, 4, 36, 27
 ; CHECK-64-NEXT:    ldx 3, 3, 4
 ; CHECK-64-NEXT:    rlwinm 4, 5, 3, 28, 28

llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll

entry:
   store <2 x double> %val, <2 x double>* @_ZL21StaticVectorDoubleVar, align 16
   ret void
 }
 
  @_ZL3ptr = internal unnamed_addr global i32* null, align 8
 define void @_Z14WriteStaticPtrv() {
 ; CHECK-LABEL: _Z14WriteStaticPtrv:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    pld r3, _ZL3ptr@PCREL(0), 1
-; CHECK-NEXT:    li r4, 3
-; CHECK-NEXT:    stw r4, 0(r3)
+; CHECK-NEXT:    pld r4, _ZL3ptr@PCREL(0), 1
+; CHECK-NEXT:    li r3, 3
+; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
   %0 = load i32*, i32** @_ZL3ptr, align 8
   store i32 3, i32* %0, align 4
   ret void
 }
 
  @.str = private unnamed_addr constant [13 x i8] c"Hello World\0A\00", align 1

llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll

 ; CHECK-NEXT:    cmplwi r4, 0
 ; CHECK-NEXT:    beq cr0, .LBB0_4
 ; CHECK-NEXT:  # %bb.1: # %.preheader
 ; CHECK-NEXT:    cmpldi r4, 1
 ; CHECK-NEXT:    li r5, 1
 ; CHECK-NEXT:    addi r3, r3, 4004
 ; CHECK-NEXT:    li r6, -3
 ; CHECK-NEXT:    li r7, -2
-; CHECK-NEXT:    li r8, -1
-; CHECK-NEXT:    iselgt r5, r4, r5
-; CHECK-NEXT:    mtctr r5
+; CHECK-NEXT:    iselgt r8, r4, r5
 ; CHECK-NEXT:    li r5, 0
+; CHECK-NEXT:    mtctr r8
+; CHECK-NEXT:    li r8, -1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    ldx r9, r3, r6
 ; CHECK-NEXT:    ldx r10, r3, r7
 ; CHECK-NEXT:    ldx r11, r3, r8
 ; CHECK-NEXT:    ld r12, 0(r3)
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    mulld r9, r10, r9

 ; CHECK-LABEL: test_ds_prep:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cmplwi r4, 0
 ; CHECK-NEXT:    beq cr0, .LBB1_4
 ; CHECK-NEXT:  # %bb.1: # %.preheader
 ; CHECK-NEXT:    cmpldi r4, 1
 ; CHECK-NEXT:    li r5, 1
 ; CHECK-NEXT:    addi r6, r3, 4002
-; CHECK-NEXT:    li r7, -1
-; CHECK-NEXT:    iselgt r3, r4, r5
-; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    iselgt r7, r4, r5
+; CHECK-NEXT:    mtctr r7
+; CHECK-NEXT:    li r7, -1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    ldx r8, r6, r7
 ; CHECK-NEXT:    ld r9, 0(r6)
 ; CHECK-NEXT:    ldx r10, r6, r5
 ; CHECK-NEXT:    ld r11, 4(r6)
 ; CHECK-NEXT:    addi r6, r6, 1
 ; CHECK-NEXT:    mulld r8, r9, r8

 ; CHECK-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    beq cr0, .LBB2_3
 ; CHECK-NEXT:  # %bb.1: # %.preheader
 ; CHECK-NEXT:    cmpldi r4, 1
 ; CHECK-NEXT:    li r5, 1
 ; CHECK-NEXT:    addi r9, r3, 4002
+; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    li r6, -1
 ; CHECK-NEXT:    li r7, 3
 ; CHECK-NEXT:    li r8, 5
+; CHECK-NEXT:    iselgt r10, r4, r5
+; CHECK-NEXT:    mtctr r10
 ; CHECK-NEXT:    li r10, 9
-; CHECK-NEXT:    iselgt r3, r4, r5
-; CHECK-NEXT:    mtctr r3
-; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    ldx r11, r9, r6
 ; CHECK-NEXT:    ld r12, 0(r9)
 ; CHECK-NEXT:    ldx r0, r9, r5
 ; CHECK-NEXT:    ldx r30, r9, r7
 ; CHECK-NEXT:    mulld r11, r12, r11
 ; CHECK-NEXT:    ld r29, 4(r9)

 ; CHECK-LABEL: test_update_ds_prep_interact:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cmplwi r4, 0
 ; CHECK-NEXT:    beq cr0, .LBB3_4
 ; CHECK-NEXT:  # %bb.1: # %.preheader
 ; CHECK-NEXT:    cmpldi r4, 1
 ; CHECK-NEXT:    li r6, 1
 ; CHECK-NEXT:    addi r3, r3, 3998
-; CHECK-NEXT:    li r7, -1
-; CHECK-NEXT:    iselgt r5, r4, r6
-; CHECK-NEXT:    mtctr r5
 ; CHECK-NEXT:    li r5, 0
+; CHECK-NEXT:    iselgt r7, r4, r6
+; CHECK-NEXT:    mtctr r7
+; CHECK-NEXT:    li r7, -1
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    ldu r8, 4(r3)
 ; CHECK-NEXT:    ldx r9, r3, r7
 ; CHECK-NEXT:    ldx r10, r3, r6
 ; CHECK-NEXT:    ld r11, 4(r3)
 ; CHECK-NEXT:    mulld r8, r8, r9
 ; CHECK-NEXT:    mulld r8, r8, r10

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    cmplwi r4, 0
 ; CHECK-NEXT:    beq cr0, .LBB4_4
 ; CHECK-NEXT:  # %bb.1: # %.preheader
 ; CHECK-NEXT:    cmpldi r4, 1
 ; CHECK-NEXT:    li r6, 1
 ; CHECK-NEXT:    addi r5, r3, 4000
 ; CHECK-NEXT:    addi r3, r3, 4003
-; CHECK-NEXT:    li r7, -1
-; CHECK-NEXT:    iselgt r6, r4, r6
-; CHECK-NEXT:    mtctr r6
+; CHECK-NEXT:    iselgt r7, r4, r6
 ; CHECK-NEXT:    li r6, 0
+; CHECK-NEXT:    mtctr r7
+; CHECK-NEXT:    li r7, -1
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    lbzu r8, 1(r5)
 ; CHECK-NEXT:    ldx r9, r3, r7
 ; CHECK-NEXT:    ld r10, 0(r3)
 ; CHECK-NEXT:    ld r11, 4(r3)
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    mulld r8, r9, r8

 ; CHECK-NEXT:    cmplwi r5, 0
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    beq cr0, .LBB5_3
 ; CHECK-NEXT:  # %bb.1: # %.preheader
 ; CHECK-NEXT:    cmpldi r5, 1
 ; CHECK-NEXT:    li r6, 1
 ; CHECK-NEXT:    addi r3, r3, 4001
 ; CHECK-NEXT:    addi r4, r4, 4001
-; CHECK-NEXT:    li r7, 9
-; CHECK-NEXT:    iselgt r6, r5, r6
-; CHECK-NEXT:    mtctr r6
+; CHECK-NEXT:    iselgt r7, r5, r6
 ; CHECK-NEXT:    li r6, 0
+; CHECK-NEXT:    mtctr r7
+; CHECK-NEXT:    li r7, 9
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    ld r8, 0(r3)
 ; CHECK-NEXT:    ldx r9, r3, r7
 ; CHECK-NEXT:    ld r10, 4(r3)
 ; CHECK-NEXT:    ld r11, 8(r3)
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    mulld r8, r9, r8

 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    beq cr0, .LBB6_8
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    cmpldi r4, 1
 ; CHECK-NEXT:    li r7, 1
 ; CHECK-NEXT:    addi r6, r3, 4009
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    iselgt r4, r4, r7
+; CHECK-NEXT:    iselgt r0, r4, r7
 ; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, -9
 ; CHECK-NEXT:    li r8, -7
 ; CHECK-NEXT:    li r9, -6
 ; CHECK-NEXT:    li r10, 1
 ; CHECK-NEXT:    li r11, 1
 ; CHECK-NEXT:    li r12, 1
-; CHECK-NEXT:    li r30, 1
 ; CHECK-NEXT:    ld r5, 0(r5)
-; CHECK-NEXT:    mtctr r4
-; CHECK-NEXT:    li r4, -9
+; CHECK-NEXT:    mtctr r0
+; CHECK-NEXT:    li r30, 1
 ; CHECK-NEXT:    li r29, 1
 ; CHECK-NEXT:    addi r5, r5, -1
 ; CHECK-NEXT:    b .LBB6_4
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB6_2:
 ; CHECK-NEXT:    ldx r0, r6, r4
 ; CHECK-NEXT:    add r29, r0, r29
 ; CHECK-NEXT:    ld r0, -8(r6)

llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll

entry:
   %0 = load i8, i8* @valChar, align 1
   %conv = zext i8 %0 to i32
   ret i32 %conv
 }
 
 define dso_local void @WriteGlobalVarChar() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalVarChar:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, valChar@got@pcrel(0), 1
-; LE-NEXT:    li r4, 3
-; LE-NEXT:    stb r4, 0(r3)
+; LE-NEXT:    pld r4, valChar@got@pcrel(0), 1
+; LE-NEXT:    li r3, 3
+; LE-NEXT:    stb r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalVarChar:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, valChar@got@pcrel(0), 1
-; BE-NEXT:    li r4, 3
-; BE-NEXT:    stb r4, 0(r3)
+; BE-NEXT:    pld r4, valChar@got@pcrel(0), 1
+; BE-NEXT:    li r3, 3
+; BE-NEXT:    stb r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   store i8 3, i8* @valChar, align 1
   ret void
 }
 
 define dso_local signext i32 @ReadGlobalVarShort() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarShort:
entry:
   %0 = load i16, i16* @valShort, align 2
   %conv = sext i16 %0 to i32
   ret i32 %conv
 }
 
 define dso_local void @WriteGlobalVarShort() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalVarShort:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, valShort@got@pcrel(0), 1
-; LE-NEXT:    li r4, 3
-; LE-NEXT:    sth r4, 0(r3)
+; LE-NEXT:    pld r4, valShort@got@pcrel(0), 1
+; LE-NEXT:    li r3, 3
+; LE-NEXT:    sth r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalVarShort:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, valShort@got@pcrel(0), 1
-; BE-NEXT:    li r4, 3
-; BE-NEXT:    sth r4, 0(r3)
+; BE-NEXT:    pld r4, valShort@got@pcrel(0), 1
+; BE-NEXT:    li r3, 3
+; BE-NEXT:    sth r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   store i16 3, i16* @valShort, align 2
   ret void
 }
 
 define dso_local signext i32 @ReadGlobalVarInt() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarInt:

 entry:
   %0 = load i32, i32* @valInt, align 4
   ret i32 %0
 }
 
 define dso_local void @WriteGlobalVarInt() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalVarInt:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, valInt@got@pcrel(0), 1
-; LE-NEXT:    li r4, 33
-; LE-NEXT:    stw r4, 0(r3)
+; LE-NEXT:    pld r4, valInt@got@pcrel(0), 1
+; LE-NEXT:    li r3, 33
+; LE-NEXT:    stw r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalVarInt:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, valInt@got@pcrel(0), 1
-; BE-NEXT:    li r4, 33
-; BE-NEXT:    stw r4, 0(r3)
+; BE-NEXT:    pld r4, valInt@got@pcrel(0), 1
+; BE-NEXT:    li r3, 33
+; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   store i32 33, i32* @valInt, align 4
   ret void
 }
 
 define dso_local signext i32 @ReadGlobalVarUnsigned() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarUnsigned:

 entry:
   %0 = load i32, i32* @valUnsigned, align 4
   ret i32 %0
 }
 
 define dso_local void @WriteGlobalVarUnsigned() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalVarUnsigned:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, valUnsigned@got@pcrel(0), 1
-; LE-NEXT:    li r4, 33
-; LE-NEXT:    stw r4, 0(r3)
+; LE-NEXT:    pld r4, valUnsigned@got@pcrel(0), 1
+; LE-NEXT:    li r3, 33
+; LE-NEXT:    stw r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalVarUnsigned:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, valUnsigned@got@pcrel(0), 1
-; BE-NEXT:    li r4, 33
-; BE-NEXT:    stw r4, 0(r3)
+; BE-NEXT:    pld r4, valUnsigned@got@pcrel(0), 1
+; BE-NEXT:    li r3, 33
+; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   store i32 33, i32* @valUnsigned, align 4
   ret void
 }
 
 define dso_local signext i32 @ReadGlobalVarLong() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarLong:
entry:
   %0 = load i64, i64* @valLong, align 8
   %conv = trunc i64 %0 to i32
   ret i32 %conv
 }
 
 define dso_local void @WriteGlobalVarLong() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalVarLong:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, valLong@got@pcrel(0), 1
-; LE-NEXT:    li r4, 3333
-; LE-NEXT:    std r4, 0(r3)
+; LE-NEXT:    pld r4, valLong@got@pcrel(0), 1
+; LE-NEXT:    li r3, 3333
+; LE-NEXT:    std r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalVarLong:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, valLong@got@pcrel(0), 1
-; BE-NEXT:    li r4, 3333
-; BE-NEXT:    std r4, 0(r3)
+; BE-NEXT:    pld r4, valLong@got@pcrel(0), 1
+; BE-NEXT:    li r3, 3333
+; BE-NEXT:    std r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   store i64 3333, i64* @valLong, align 8
   ret void
 }
 
 define dso_local i32* @ReadGlobalPtr() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalPtr:

 entry:
   %0 = load i32*, i32** @ptr, align 8
   ret i32* %0
 }
 
 define dso_local void @WriteGlobalPtr() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalPtr:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, ptr@got@pcrel(0), 1
+; LE-NEXT:    pld r4, ptr@got@pcrel(0), 1
 ; LE-NEXT:  .Lpcrel6:
-; LE-NEXT:    li r4, 3
+; LE-NEXT:    li r3, 3
 ; LE-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
-; LE-NEXT:    ld r3, 0(r3)
-; LE-NEXT:    stw r4, 0(r3)
+; LE-NEXT:    ld r4, 0(r4)
+; LE-NEXT:    stw r3, 0(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalPtr:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, ptr@got@pcrel(0), 1
+; BE-NEXT:    pld r4, ptr@got@pcrel(0), 1
 ; BE-NEXT:  .Lpcrel6:
-; BE-NEXT:    li r4, 3
+; BE-NEXT:    li r3, 3
 ; BE-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
-; BE-NEXT:    ld r3, 0(r3)
-; BE-NEXT:    stw r4, 0(r3)
+; BE-NEXT:    ld r4, 0(r4)
+; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
 entry:
   %0 = load i32*, i32** @ptr, align 8
   store i32 3, i32* %0, align 4
   ret void
 }
 
 define dso_local nonnull i32* @GlobalVarAddr() local_unnamed_addr  {

 entry:
   %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array, i64 0, i64 3), align 4
   ret i32 %0
 }
 
 define dso_local void @WriteGlobalArray() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalArray:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, array@got@pcrel(0), 1
-; LE-NEXT:    li r4, 5
-; LE-NEXT:    stw r4, 12(r3)
+; LE-NEXT:    pld r4, array@got@pcrel(0), 1
+; LE-NEXT:    li r3, 5
+; LE-NEXT:    stw r3, 12(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalArray:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, array@got@pcrel(0), 1
-; BE-NEXT:    li r4, 5
-; BE-NEXT:    stw r4, 12(r3)
+; BE-NEXT:    pld r4, array@got@pcrel(0), 1
+; BE-NEXT:    li r3, 5
+; BE-NEXT:    stw r3, 12(r4)
 ; BE-NEXT:    blr
 entry:
   store i32 5, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array, i64 0, i64 3), align 4
   ret void
 }
 
 define dso_local signext i32 @ReadGlobalStruct() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalStruct:

 entry:
   %0 = load i32, i32* getelementptr inbounds (%struct.Struct, %struct.Struct* @structure, i64 0, i32 2), align 4
   ret i32 %0
 }
 
 define dso_local void @WriteGlobalStruct() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalStruct:
 ; LE:       # %bb.0: # %entry
-; LE-NEXT:    pld r3, structure@got@pcrel(0), 1
-; LE-NEXT:    li r4, 3
-; LE-NEXT:    stw r4, 4(r3)
+; LE-NEXT:    pld r4, structure@got@pcrel(0), 1
+; LE-NEXT:    li r3, 3
+; LE-NEXT:    stw r3, 4(r4)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: WriteGlobalStruct:
 ; BE:       # %bb.0: # %entry
-; BE-NEXT:    pld r3, structure@got@pcrel(0), 1
-; BE-NEXT:    li r4, 3
-; BE-NEXT:    stw r4, 4(r3)
+; BE-NEXT:    pld r4, structure@got@pcrel(0), 1
+; BE-NEXT:    li r3, 3
+; BE-NEXT:    stw r3, 4(r4)
 ; BE-NEXT:    blr
 entry:
   store i32 3, i32* getelementptr inbounds (%struct.Struct, %struct.Struct* @structure, i64 0, i32 2), align 4
   ret void
 }
 
 define dso_local void @ReadFuncPtr() local_unnamed_addr  {
 ; LE-LABEL: ReadFuncPtr:
-; LE:         .localentry ReadFuncPtr, 1
-; LE-NEXT:  # %bb.0: # %entry
+; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, ptrfunc@got@pcrel(0), 1
 ; LE-NEXT:  .Lpcrel9:
 ; LE-NEXT:    .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8)
 ; LE-NEXT:    ld r12, 0(r3)
 ; LE-NEXT:    mtctr r12
 ; LE-NEXT:    bctr
 ; LE-NEXT:    #TC_RETURNr8 ctr 0
 ;
 ; BE-LABEL: ReadFuncPtr:
-; BE:         .localentry ReadFuncPtr, 1
-; BE-NEXT:  # %bb.0: # %entry
+; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, ptrfunc@got@pcrel(0), 1
 ; BE-NEXT:  .Lpcrel9:
 ; BE-NEXT:    .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8)
 ; BE-NEXT:    ld r12, 0(r3)
 ; BE-NEXT:    mtctr r12
 ; BE-NEXT:    bctr
 ; BE-NEXT:    #TC_RETURNr8 ctr 0
 entry:

llvm/test/CodeGen/PowerPC/pr48519.ll

 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB2_6: # %bb15
 ;
 ; CHECK-P9-LABEL: func_48786:
 ; CHECK-P9:       # %bb.0: # %bb
 ; CHECK-P9-NEXT:    ld r3, 0(r3)
 ; CHECK-P9-NEXT:    cmpdi r3, 0
-; CHECK-P9-NEXT:    mtctr r3
 ; CHECK-P9-NEXT:    li r3, 0
+; CHECK-P9-NEXT:    mtctr r3
 ; CHECK-P9-NEXT:    crnot 4*cr5+lt, eq
 ; CHECK-P9-NEXT:    b .LBB2_2
 ; CHECK-P9-NEXT:    .p2align 5
 ; CHECK-P9-NEXT:  .LBB2_1: # %bb10
 ; CHECK-P9-NEXT:    #
 ; CHECK-P9-NEXT:    bdzlr
 ; CHECK-P9-NEXT:  .LBB2_2: # %bb2
 ; CHECK-P9-NEXT:    #

llvm/test/CodeGen/PowerPC/sms-simple.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:       -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr9 --ppc-enable-pipeliner \
 ; RUN:       | FileCheck %s
 
 @x = dso_local local_unnamed_addr global <{ i32, i32, i32, i32, [1020 x i32] }> <{ i32 1, i32 2, i32 3, i32 4, [1020 x i32] zeroinitializer }>, align 4
 @y = dso_local global [1024 x i32] zeroinitializer, align 4
 
 define dso_local i32* @foo() local_unnamed_addr {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis r5, r2, y@toc@ha
-; CHECK-NEXT:    li r7, 340
-; CHECK-NEXT:    addi r3, r5, y@toc@l
-; CHECK-NEXT:    lwz r6, y@toc@l(r5)
+; CHECK-NEXT:    addis r4, r2, y@toc@ha
+; CHECK-NEXT:    li r5, 340
+; CHECK-NEXT:    lwz r6, y@toc@l(r4)
+; CHECK-NEXT:    mtctr r5
 ; CHECK-NEXT:    addis r5, r2, x@toc@ha
-; CHECK-NEXT:    mtctr r7
+; CHECK-NEXT:    addi r3, r4, y@toc@l
 ; CHECK-NEXT:    addi r5, r5, x@toc@l
 ; CHECK-NEXT:    addi r4, r3, -8
 ; CHECK-NEXT:    addi r5, r5, -8
 ; CHECK-NEXT:    lwzu r7, 12(r5)
 ; CHECK-NEXT:    maddld r6, r7, r7, r6
 ; CHECK-NEXT:    lwz r7, 4(r5)
 ; CHECK-NEXT:    stwu r6, 12(r4)
 ; CHECK-NEXT:    maddld r6, r7, r7, r6

llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll

entry:
   ret void
 }
 
 ; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of
 ; loop.
 define i64 @test_xaddrX4_loop(i8* %p) {
 ; CHECK-LABEL: test_xaddrX4_loop:
 ; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r5, 8
 ; CHECK-NEXT:    addi r4, r3, -8
-; CHECK-NEXT:    li r3, 8
-; CHECK-NEXT:    li r5, 3
-; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    mtctr r5
+; CHECK-NEXT:    li r5, 3
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB4_1: # %for.body
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    ldu r6, 8(r4)
 ; CHECK-NEXT:    ldx r7, r4, r5
 ; CHECK-NEXT:    maddld r3, r7, r6, r3
 ; CHECK-NEXT:    bdnz .LBB4_1
 ; CHECK-NEXT:  # %bb.2: # %for.end

llvm/test/CodeGen/PowerPC/vec_insert_elt.ll

 ;
 ; CHECK-BE-LABEL: testByte:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsblx v2, r6, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testByte:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    clrldi r3, r6, 60
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stbx r5, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %conv = trunc i64 %b to i8
   %vecins = insertelement <16 x i8> %a, i8 %conv, i64 %idx
   ret <16 x i8> %vecins

 ; CHECK-BE-LABEL: testHalf:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    slwi r3, r6, 1
 ; CHECK-BE-NEXT:    vinshlx v2, r3, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testHalf:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 1, 28, 30
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    sthx r5, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %conv = trunc i64 %b to i16
   %vecins = insertelement <8 x i16> %a, i16 %conv, i64 %idx
   ret <8 x i16> %vecins

 ; CHECK-BE-LABEL: testWord:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    slwi r3, r6, 2
 ; CHECK-BE-NEXT:    vinswlx v2, r3, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testWord:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 2, 28, 29
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stwx r5, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %conv = trunc i64 %b to i32
   %vecins = insertelement <4 x i32> %a, i32 %conv, i64 %idx
   ret <4 x i32> %vecins

 ; CHECK-BE-LABEL: testDoubleword:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm r3, r6, 3, 0, 28
 ; CHECK-BE-NEXT:    vinsdlx v2, r3, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testDoubleword:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 3, 28, 28
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stdx r5, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %vecins = insertelement <2 x i64> %a, i64 %b, i64 %idx
   ret <2 x i64> %vecins
 }

 ; CHECK-BE-NEXT:    extsw r4, r6
 ; CHECK-BE-NEXT:    slwi r4, r4, 2
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    vinswlx v2, r4, r3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloat1:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 2, 28, 29
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stfsx f1, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %vecins = insertelement <4 x float> %a, float %b, i32 %idx1
   ret <4 x float> %vecins
 }

 ; CHECK-BE-NEXT:    extsw r4, r6
 ; CHECK-BE-NEXT:    mffprd r3, f1
 ; CHECK-BE-NEXT:    rlwinm r4, r4, 3, 0, 28
 ; CHECK-BE-NEXT:    vinsdlx v2, r4, r3
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testDouble1:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    rlwinm r3, r6, 3, 28, 28
+; CHECK-P9-NEXT:    addi r4, r1, -16
 ; CHECK-P9-NEXT:    stxv v2, -16(r1)
 ; CHECK-P9-NEXT:    stfdx f1, r4, r3
 ; CHECK-P9-NEXT:    lxv v2, -16(r1)
 ; CHECK-P9-NEXT:    blr
 entry:
   %vecins = insertelement <2 x double> %a, double %b, i32 %idx1
   ret <2 x double> %vecins
 }