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Differential D105541

[AArch64] Set the latency of A55 stores to 1
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Authored by dmgreen on Jul 7 2021, 2:50 AM.

Details

Reviewers
NickGuy
andreadb
asavonic
Commits
rGf73334c46d59: [AArch64] Set the latency of Cortex-A55 stores to 1
Summary

This sets the latency of stores to 1 in the Cortex-A55 scheduling model, to better match the values given in the software optimization guide.

The latency of a store in normal llvm scheduling does not appear to have a lot of uses. If the store has no output's then the latency is somewhat meaningless (and pre/post increment update operands use the WriteAdr write for those operands instead). The one place it does alter things is the latency between a store and the end of the scheduling region, which can in turn have an effect on the critical path length. As a result a latency of 1 is more correct and offers ever-so-slightly better scheduling of instructions near the end of the block.

They are marked as RetireOOO to keep the llvm-mca from introducing stalls where non would exist.

Diff Detail

Unit TestsFailed

TimeTest
650 msx64 windows > lit.lit::test-output-micro.py

Event Timeline

dmgreen created this revision.Jul 7 2021, 2:50 AM
Herald added subscribers: danielkiss, gbedwell, hiraditya, kristof.beyls. · View Herald TranscriptJul 7 2021, 2:50 AM
dmgreen requested review of this revision.Jul 7 2021, 2:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 7 2021, 2:50 AM
dmgreen mentioned this in D103955: [MCA] Use LSU for the in-order pipeline.Jul 7 2021, 2:51 AM
Harbormaster completed remote builds in B112753: Diff 356906.Jul 7 2021, 3:25 AM
NickGuy accepted this revision.Jul 9 2021, 7:34 AM

No issues that I can see, LGTM

This revision is now accepted and ready to land.Jul 9 2021, 7:34 AM
This revision was landed with ongoing or failed builds.Jul 12 2021, 5:41 AM
Closed by commit rGf73334c46d59: [AArch64] Set the latency of Cortex-A55 stores to 1 (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rGf73334c46d59: [AArch64] Set the latency of Cortex-A55 stores to 1.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
8 lines
test/
tools/
llvm-mca/
AArch64/
Cortex/
23 lines
53 lines
256 lines
1 line
30 lines
1 line

Diff 356906

llvm/lib/Target/AArch64/AArch64SchedA55.td

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Linesdef CortexA55WriteVLD7 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 10;
let ResourceCycles = [7]; } let ResourceCycles = [7]; }
def CortexA55WriteVLD8 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 11; def CortexA55WriteVLD8 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 11;
let ResourceCycles = [8]; } let ResourceCycles = [8]; }
// Pre/Post Indexing - Performed as part of address generation // Pre/Post Indexing - Performed as part of address generation
def : WriteRes<WriteAdr, []> { let Latency = 0; } def : WriteRes<WriteAdr, []> { let Latency = 0; }
// Store // Store
def : WriteRes<WriteST, [CortexA55UnitSt]> { let Latency = 4; } let RetireOOO = 1 in {
def : WriteRes<WriteSTP, [CortexA55UnitSt]> { let Latency = 4; } def : WriteRes<WriteST, [CortexA55UnitSt]> { let Latency = 1; }
def : WriteRes<WriteSTIdx, [CortexA55UnitSt]> { let Latency = 4; } def : WriteRes<WriteSTP, [CortexA55UnitSt]> { let Latency = 1; }
def : WriteRes<WriteSTIdx, [CortexA55UnitSt]> { let Latency = 1; }
}
def : WriteRes<WriteSTX, [CortexA55UnitSt]> { let Latency = 4; } def : WriteRes<WriteSTX, [CortexA55UnitSt]> { let Latency = 4; }
// Vector Store - Similar to vector loads, can take 1-3 cycles to issue. // Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
def : WriteRes<WriteVST, [CortexA55UnitSt]> { let Latency = 5; def : WriteRes<WriteVST, [CortexA55UnitSt]> { let Latency = 5;
let ResourceCycles = [2];} let ResourceCycles = [2];}
def CortexA55WriteVST1 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 4; } def CortexA55WriteVST1 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 4; }
def CortexA55WriteVST2 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5; def CortexA55WriteVST2 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;
let ResourceCycles = [2]; } let ResourceCycles = [2]; }
▲ Show 20 Lines • Show All 220 Lines • Show Last 20 Lines

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --iterations=2 < %s | FileCheck %s # RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --iterations=2 < %s | FileCheck %s
ldr w4, [x2], #4 ldr w4, [x2], #4
ldr w5, [x3] ldr w5, [x3]
madd w0, w5, w4, w0 madd w0, w5, w4, w0
add x3, x3, x13 add x3, x3, x13
subs x1, x1, #1 subs x1, x1, #1
str w0, [x21, x18, lsl #2] str w0, [x21, x18, lsl #2]
# CHECK: Iterations: 2 # CHECK: Iterations: 2
# CHECK-NEXT: Instructions: 12 # CHECK-NEXT: Instructions: 12
# CHECK-NEXT: Total Cycles: 23 # CHECK-NEXT: Total Cycles: 17
# CHECK-NEXT: Total uOps: 14 # CHECK-NEXT: Total uOps: 14
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.61 # CHECK-NEXT: uOps Per Cycle: 0.82
# CHECK-NEXT: IPC: 0.52 # CHECK-NEXT: IPC: 0.71
# CHECK-NEXT: Block RThroughput: 3.5 # CHECK-NEXT: Block RThroughput: 3.5
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 3 1.00 * ldr w4, [x2], #4 # CHECK-NEXT: 2 3 1.00 * ldr w4, [x2], #4
# CHECK-NEXT: 1 3 1.00 * ldr w5, [x3] # CHECK-NEXT: 1 3 1.00 * ldr w5, [x3]
# CHECK-NEXT: 1 4 1.00 madd w0, w5, w4, w0 # CHECK-NEXT: 1 4 1.00 madd w0, w5, w4, w0
# CHECK-NEXT: 1 3 0.50 add x3, x3, x13 # CHECK-NEXT: 1 3 0.50 add x3, x3, x13
# CHECK-NEXT: 1 3 0.50 subs x1, x1, #1 # CHECK-NEXT: 1 3 0.50 subs x1, x1, #1
# CHECK-NEXT: 1 4 1.00 * str w0, [x21, x18, lsl #2] # CHECK-NEXT: 1 1 1.00 * str w0, [x21, x18, lsl #2]
# CHECK: Dynamic Dispatch Stall Cycles: # CHECK: Dynamic Dispatch Stall Cycles:
# CHECK-NEXT: RAT - Register unavailable: 8 (34.8%) # CHECK-NEXT: RAT - Register unavailable: 8 (47.1%)
# CHECK-NEXT: RCU - Retire tokens unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0
# CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: SCHEDQ - Scheduler full: 0
# CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles] # CHECK-NEXT: [# dispatched], [# cycles]
# CHECK-NEXT: 0, 13 (56.5%) # CHECK-NEXT: 0, 7 (41.2%)
# CHECK-NEXT: 1, 6 (26.1%) # CHECK-NEXT: 1, 6 (35.3%)
# CHECK-NEXT: 2, 4 (17.4%) # CHECK-NEXT: 2, 4 (23.5%)
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
# CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: [# issued], [# cycles]
# CHECK-NEXT: 0, 13 (56.5%) # CHECK-NEXT: 0, 7 (41.2%)
# CHECK-NEXT: 1, 6 (26.1%) # CHECK-NEXT: 1, 6 (35.3%)
# CHECK-NEXT: 2, 4 (17.4%) # CHECK-NEXT: 2, 4 (23.5%)
# CHECK: Scheduler's queue usage: # CHECK: Scheduler's queue usage:
# CHECK-NEXT: No scheduler resources used. # CHECK-NEXT: No scheduler resources used.
# CHECK: Register File statistics: # CHECK: Register File statistics:
# CHECK-NEXT: Total number of mappings created: 14 # CHECK-NEXT: Total number of mappings created: 14
# CHECK-NEXT: Max number of mappings used: 4 # CHECK-NEXT: Max number of mappings used: 4
Show All 26 Lines

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views --iterations=2 < %s | FileCheck %s # RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views --iterations=2 < %s | FileCheck %s
ldr w4, [x2], #4 ldr w4, [x2], #4
ldr w5, [x3] ldr w5, [x3]
madd w0, w5, w4, w0 madd w0, w5, w4, w0
add x3, x3, x13 add x3, x3, x13
subs x1, x1, #1 subs x1, x1, #1
str w0, [x21, x18, lsl #2] str w0, [x21, x18, lsl #2]
# CHECK: Iterations: 2 # CHECK: Iterations: 2
# CHECK-NEXT: Instructions: 12 # CHECK-NEXT: Instructions: 12
# CHECK-NEXT: Total Cycles: 23 # CHECK-NEXT: Total Cycles: 17
# CHECK-NEXT: Total uOps: 14 # CHECK-NEXT: Total uOps: 14
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.61 # CHECK-NEXT: uOps Per Cycle: 0.82
# CHECK-NEXT: IPC: 0.52 # CHECK-NEXT: IPC: 0.71
# CHECK-NEXT: Block RThroughput: 3.5 # CHECK-NEXT: Block RThroughput: 3.5
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 3 1.00 * ldr w4, [x2], #4 # CHECK-NEXT: 2 3 1.00 * ldr w4, [x2], #4
# CHECK-NEXT: 1 3 1.00 * ldr w5, [x3] # CHECK-NEXT: 1 3 1.00 * ldr w5, [x3]
# CHECK-NEXT: 1 4 1.00 madd w0, w5, w4, w0 # CHECK-NEXT: 1 4 1.00 madd w0, w5, w4, w0
# CHECK-NEXT: 1 3 0.50 add x3, x3, x13 # CHECK-NEXT: 1 3 0.50 add x3, x3, x13
# CHECK-NEXT: 1 3 0.50 subs x1, x1, #1 # CHECK-NEXT: 1 3 0.50 subs x1, x1, #1
# CHECK-NEXT: 1 4 1.00 * str w0, [x21, x18, lsl #2] # CHECK-NEXT: 1 1 1.00 * str w0, [x21, x18, lsl #2]
# CHECK: Dynamic Dispatch Stall Cycles: # CHECK: Dynamic Dispatch Stall Cycles:
# CHECK-NEXT: RAT - Register unavailable: 8 (34.8%) # CHECK-NEXT: RAT - Register unavailable: 8 (47.1%)
# CHECK-NEXT: RCU - Retire tokens unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0
# CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: SCHEDQ - Scheduler full: 0
# CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles] # CHECK-NEXT: [# dispatched], [# cycles]
# CHECK-NEXT: 0, 13 (56.5%) # CHECK-NEXT: 0, 7 (41.2%)
# CHECK-NEXT: 1, 6 (26.1%) # CHECK-NEXT: 1, 6 (35.3%)
# CHECK-NEXT: 2, 4 (17.4%) # CHECK-NEXT: 2, 4 (23.5%)
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
# CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: [# issued], [# cycles]
# CHECK-NEXT: 0, 13 (56.5%) # CHECK-NEXT: 0, 7 (41.2%)
# CHECK-NEXT: 1, 6 (26.1%) # CHECK-NEXT: 1, 6 (35.3%)
# CHECK-NEXT: 2, 4 (17.4%) # CHECK-NEXT: 2, 4 (23.5%)
# CHECK: Scheduler's queue usage: # CHECK: Scheduler's queue usage:
# CHECK-NEXT: No scheduler resources used. # CHECK-NEXT: No scheduler resources used.
# CHECK: Register File statistics: # CHECK: Register File statistics:
# CHECK-NEXT: Total number of mappings created: 14 # CHECK-NEXT: Total number of mappings created: 14
# CHECK-NEXT: Max number of mappings used: 4 # CHECK-NEXT: Max number of mappings used: 4
Show All 20 Lines
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr w4, [x2], #4 # CHECK-NEXT: - - - - - - - - - 1.00 - - ldr w4, [x2], #4
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr w5, [x3] # CHECK-NEXT: - - - - - - - - - 1.00 - - ldr w5, [x3]
# CHECK-NEXT: - - - - - - - - - - 1.00 - madd w0, w5, w4, w0 # CHECK-NEXT: - - - - - - - - - - 1.00 - madd w0, w5, w4, w0
# CHECK-NEXT: - 1.00 - - - - - - - - - - add x3, x3, x13 # CHECK-NEXT: - 1.00 - - - - - - - - - - add x3, x3, x13
# CHECK-NEXT: 1.00 - - - - - - - - - - - subs x1, x1, #1 # CHECK-NEXT: 1.00 - - - - - - - - - - - subs x1, x1, #1
# CHECK-NEXT: - - - - - - - - - - - 1.00 str w0, [x21, x18, lsl #2] # CHECK-NEXT: - - - - - - - - - - - 1.00 str w0, [x21, x18, lsl #2]
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 # CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789 012 # CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . . . . . ldr w4, [x2], #4 # CHECK: [0,0] DeeE . . .. ldr w4, [x2], #4
# CHECK-NEXT: [0,1] .DeeE. . . . . ldr w5, [x3] # CHECK-NEXT: [0,1] .DeeE. . .. ldr w5, [x3]
# CHECK-NEXT: [0,2] . DeeeE . . . . madd w0, w5, w4, w0 # CHECK-NEXT: [0,2] . DeeeE . .. madd w0, w5, w4, w0
# CHECK-NEXT: [0,3] . DeeE . . . . add x3, x3, x13 # CHECK-NEXT: [0,3] . DeeE . .. add x3, x3, x13
# CHECK-NEXT: [0,4] . DeeE . . . . subs x1, x1, #1 # CHECK-NEXT: [0,4] . DeeE . .. subs x1, x1, #1
# CHECK-NEXT: [0,5] . . DeeeE . . . str w0, [x21, x18, lsl #2] # CHECK-NEXT: [0,5] . . DE . .. str w0, [x21, x18, lsl #2]
# CHECK-NEXT: [1,0] . . .DeeE. . . ldr w4, [x2], #4 # CHECK-NEXT: [1,0] . . DeeE .. ldr w4, [x2], #4
# CHECK-NEXT: [1,1] . . . DeeE . . ldr w5, [x3] # CHECK-NEXT: [1,1] . . DeeE .. ldr w5, [x3]
# CHECK-NEXT: [1,2] . . . DeeeE. . madd w0, w5, w4, w0 # CHECK-NEXT: [1,2] . . . DeeeE madd w0, w5, w4, w0
# CHECK-NEXT: [1,3] . . . .DeeE. . add x3, x3, x13 # CHECK-NEXT: [1,3] . . . DeeE add x3, x3, x13
# CHECK-NEXT: [1,4] . . . .DeeE. . subs x1, x1, #1 # CHECK-NEXT: [1,4] . . . DeeE subs x1, x1, #1
# CHECK-NEXT: [1,5] . . . . DeeeE str w0, [x21, x18, lsl #2] # CHECK-NEXT: [1,5] . . . DE str w0, [x21, x18, lsl #2]
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 2 0.0 0.0 0.0 ldr w4, [x2], #4 # CHECK-NEXT: 0. 2 0.0 0.0 0.0 ldr w4, [x2], #4
# CHECK-NEXT: 1. 2 0.0 0.0 0.0 ldr w5, [x3] # CHECK-NEXT: 1. 2 0.0 0.0 0.0 ldr w5, [x3]
# CHECK-NEXT: 2. 2 0.0 0.0 0.0 madd w0, w5, w4, w0 # CHECK-NEXT: 2. 2 0.0 0.0 0.0 madd w0, w5, w4, w0
# CHECK-NEXT: 3. 2 0.0 0.0 0.0 add x3, x3, x13 # CHECK-NEXT: 3. 2 0.0 0.0 0.0 add x3, x3, x13
# CHECK-NEXT: 4. 2 0.0 0.0 0.0 subs x1, x1, #1 # CHECK-NEXT: 4. 2 0.0 0.0 0.0 subs x1, x1, #1
# CHECK-NEXT: 5. 2 0.0 0.0 0.0 str w0, [x21, x18, lsl #2] # CHECK-NEXT: 5. 2 0.0 0.0 0.0 str w0, [x21, x18, lsl #2]
# CHECK-NEXT: 2 0.0 0.0 0.0 <total> # CHECK-NEXT: 2 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s

Show First 20 Lines • Show All 2,101 Lines • ▼ Show 20 Lines
# CHECK-NEXT: 1 3 1.00 * ldr w3, #0 # CHECK-NEXT: 1 3 1.00 * ldr w3, #0
# CHECK-NEXT: 1 3 1.00 * ldr x29, #4 # CHECK-NEXT: 1 3 1.00 * ldr x29, #4
# CHECK-NEXT: 1 3 1.00 * ldrsw xzr, #-4 # CHECK-NEXT: 1 3 1.00 * ldrsw xzr, #-4
# CHECK-NEXT: 1 3 1.00 * ldr s0, #8 # CHECK-NEXT: 1 3 1.00 * ldr s0, #8
# CHECK-NEXT: 1 3 1.00 * ldr d0, #1048572 # CHECK-NEXT: 1 3 1.00 * ldr d0, #1048572
# CHECK-NEXT: 1 3 1.00 * ldr q0, #-1048576 # CHECK-NEXT: 1 3 1.00 * ldr q0, #-1048576
# CHECK-NEXT: 1 3 1.00 U prfm pldl1strm, #0 # CHECK-NEXT: 1 3 1.00 U prfm pldl1strm, #0
# CHECK-NEXT: 1 3 1.00 U prfm #22, #0 # CHECK-NEXT: 1 3 1.00 U prfm #22, #0
# CHECK-NEXT: 2 7 1.00 * * U stxrb w18, w8, [sp] # CHECK-NEXT: 2 4 1.00 * * U stxrb w18, w8, [sp]
# CHECK-NEXT: 2 7 1.00 * * U stxrh w24, w15, [x16] # CHECK-NEXT: 2 4 1.00 * * U stxrh w24, w15, [x16]
# CHECK-NEXT: 2 7 1.00 * * U stxr w5, w6, [x17] # CHECK-NEXT: 2 4 1.00 * * U stxr w5, w6, [x17]
# CHECK-NEXT: 2 7 1.00 * * U stxr w1, x10, [x21] # CHECK-NEXT: 2 4 1.00 * * U stxr w1, x10, [x21]
# CHECK-NEXT: 1 3 1.00 * * U ldxrb w30, [x0] # CHECK-NEXT: 1 3 1.00 * * U ldxrb w30, [x0]
# CHECK-NEXT: 1 3 1.00 * * U ldxrh w17, [x4] # CHECK-NEXT: 1 3 1.00 * * U ldxrh w17, [x4]
# CHECK-NEXT: 1 3 1.00 * * U ldxr w22, [sp] # CHECK-NEXT: 1 3 1.00 * * U ldxr w22, [sp]
# CHECK-NEXT: 1 3 1.00 * * U ldxr x11, [x29] # CHECK-NEXT: 1 3 1.00 * * U ldxr x11, [x29]
# CHECK-NEXT: 1 3 1.00 * * U ldxr x11, [x29] # CHECK-NEXT: 1 3 1.00 * * U ldxr x11, [x29]
# CHECK-NEXT: 1 3 1.00 * * U ldxr x11, [x29] # CHECK-NEXT: 1 3 1.00 * * U ldxr x11, [x29]
# CHECK-NEXT: 2 7 1.00 * * U stxp w12, w11, w10, [sp] # CHECK-NEXT: 2 4 1.00 * * U stxp w12, w11, w10, [sp]
# CHECK-NEXT: 2 7 1.00 * * U stxp wzr, x27, x9, [x12] # CHECK-NEXT: 2 4 1.00 * * U stxp wzr, x27, x9, [x12]
# CHECK-NEXT: 2 5 2.00 * * U ldxp w0, wzr, [sp] # CHECK-NEXT: 2 5 2.00 * * U ldxp w0, wzr, [sp]
# CHECK-NEXT: 2 5 2.00 * * U ldxp x17, x0, [x18] # CHECK-NEXT: 2 5 2.00 * * U ldxp x17, x0, [x18]
# CHECK-NEXT: 2 5 2.00 * * U ldxp x17, x0, [x18] # CHECK-NEXT: 2 5 2.00 * * U ldxp x17, x0, [x18]
# CHECK-NEXT: 2 7 1.00 * * U stlxrb w12, w22, [x0] # CHECK-NEXT: 2 4 1.00 * * U stlxrb w12, w22, [x0]
# CHECK-NEXT: 2 7 1.00 * * U stlxrh w10, w1, [x1] # CHECK-NEXT: 2 4 1.00 * * U stlxrh w10, w1, [x1]
# CHECK-NEXT: 2 7 1.00 * * U stlxr w9, w2, [x2] # CHECK-NEXT: 2 4 1.00 * * U stlxr w9, w2, [x2]
# CHECK-NEXT: 2 7 1.00 * * U stlxr w9, x3, [sp] # CHECK-NEXT: 2 4 1.00 * * U stlxr w9, x3, [sp]
# CHECK-NEXT: 1 3 1.00 * * U ldaxrb w8, [x4] # CHECK-NEXT: 1 3 1.00 * * U ldaxrb w8, [x4]
# CHECK-NEXT: 1 3 1.00 * * U ldaxrh w7, [x5] # CHECK-NEXT: 1 3 1.00 * * U ldaxrh w7, [x5]
# CHECK-NEXT: 1 3 1.00 * * U ldaxr w6, [sp] # CHECK-NEXT: 1 3 1.00 * * U ldaxr w6, [sp]
# CHECK-NEXT: 1 3 1.00 * * U ldaxr x5, [x6] # CHECK-NEXT: 1 3 1.00 * * U ldaxr x5, [x6]
# CHECK-NEXT: 1 3 1.00 * * U ldaxr x5, [x6] # CHECK-NEXT: 1 3 1.00 * * U ldaxr x5, [x6]
# CHECK-NEXT: 1 3 1.00 * * U ldaxr x5, [x6] # CHECK-NEXT: 1 3 1.00 * * U ldaxr x5, [x6]
# CHECK-NEXT: 2 7 1.00 * * U stlxp w4, w5, w6, [sp] # CHECK-NEXT: 2 4 1.00 * * U stlxp w4, w5, w6, [sp]
# CHECK-NEXT: 2 7 1.00 * * U stlxp wzr, x6, x7, [x1] # CHECK-NEXT: 2 4 1.00 * * U stlxp wzr, x6, x7, [x1]
# CHECK-NEXT: 2 5 2.00 * * U ldaxp w5, w18, [sp] # CHECK-NEXT: 2 5 2.00 * * U ldaxp w5, w18, [sp]
# CHECK-NEXT: 2 5 2.00 * * U ldaxp x6, x19, [x22] # CHECK-NEXT: 2 5 2.00 * * U ldaxp x6, x19, [x22]
# CHECK-NEXT: 2 5 2.00 * * U ldaxp x6, x19, [x22] # CHECK-NEXT: 2 5 2.00 * * U ldaxp x6, x19, [x22]
# CHECK-NEXT: 1 4 1.00 * U stlrb w24, [sp] # CHECK-NEXT: 1 1 1.00 * U stlrb w24, [sp]
# CHECK-NEXT: 1 4 1.00 * U stlrh w25, [x30] # CHECK-NEXT: 1 1 1.00 * U stlrh w25, [x30]
# CHECK-NEXT: 1 4 1.00 * U stlr w26, [x29] # CHECK-NEXT: 1 1 1.00 * U stlr w26, [x29]
# CHECK-NEXT: 1 4 1.00 * U stlr x27, [x28] # CHECK-NEXT: 1 1 1.00 * U stlr x27, [x28]
# CHECK-NEXT: 1 4 1.00 * U stlr x27, [x28] # CHECK-NEXT: 1 1 1.00 * U stlr x27, [x28]
# CHECK-NEXT: 1 4 1.00 * U stlr x27, [x28] # CHECK-NEXT: 1 1 1.00 * U stlr x27, [x28]
# CHECK-NEXT: 1 3 1.00 * U ldarb w23, [sp] # CHECK-NEXT: 1 3 1.00 * U ldarb w23, [sp]
# CHECK-NEXT: 1 3 1.00 * U ldarh w22, [x30] # CHECK-NEXT: 1 3 1.00 * U ldarh w22, [x30]
# CHECK-NEXT: 1 3 1.00 * U ldar wzr, [x29] # CHECK-NEXT: 1 3 1.00 * U ldar wzr, [x29]
# CHECK-NEXT: 1 3 1.00 * U ldar x21, [x28] # CHECK-NEXT: 1 3 1.00 * U ldar x21, [x28]
# CHECK-NEXT: 1 3 1.00 * U ldar x21, [x28] # CHECK-NEXT: 1 3 1.00 * U ldar x21, [x28]
# CHECK-NEXT: 1 3 1.00 * U ldar x21, [x28] # CHECK-NEXT: 1 3 1.00 * U ldar x21, [x28]
# CHECK-NEXT: 1 4 1.00 * sturb w9, [sp] # CHECK-NEXT: 1 1 1.00 * sturb w9, [sp]
# CHECK-NEXT: 1 4 1.00 * sturh wzr, [x12, #255] # CHECK-NEXT: 1 1 1.00 * sturh wzr, [x12, #255]
# CHECK-NEXT: 1 4 1.00 * stur w16, [x0, #-256] # CHECK-NEXT: 1 1 1.00 * stur w16, [x0, #-256]
# CHECK-NEXT: 1 4 1.00 * stur x28, [x14, #1] # CHECK-NEXT: 1 1 1.00 * stur x28, [x14, #1]
# CHECK-NEXT: 1 3 1.00 * ldurb w1, [x20, #255] # CHECK-NEXT: 1 3 1.00 * ldurb w1, [x20, #255]
# CHECK-NEXT: 1 3 1.00 * ldurh w20, [x1, #255] # CHECK-NEXT: 1 3 1.00 * ldurh w20, [x1, #255]
# CHECK-NEXT: 1 3 1.00 * ldur w12, [sp, #255] # CHECK-NEXT: 1 3 1.00 * ldur w12, [sp, #255]
# CHECK-NEXT: 1 3 1.00 * ldur xzr, [x12, #255] # CHECK-NEXT: 1 3 1.00 * ldur xzr, [x12, #255]
# CHECK-NEXT: 1 3 1.00 * ldursb x9, [x7, #-256] # CHECK-NEXT: 1 3 1.00 * ldursb x9, [x7, #-256]
# CHECK-NEXT: 1 3 1.00 * ldursh x17, [x19, #-256] # CHECK-NEXT: 1 3 1.00 * ldursh x17, [x19, #-256]
# CHECK-NEXT: 1 3 1.00 * ldursw x20, [x15, #-256] # CHECK-NEXT: 1 3 1.00 * ldursw x20, [x15, #-256]
# CHECK-NEXT: 1 3 1.00 U prfum pldl2keep, [sp, #-256] # CHECK-NEXT: 1 3 1.00 U prfum pldl2keep, [sp, #-256]
# CHECK-NEXT: 1 3 1.00 * ldursb w19, [x1, #-256] # CHECK-NEXT: 1 3 1.00 * ldursb w19, [x1, #-256]
# CHECK-NEXT: 1 3 1.00 * ldursh w15, [x21, #-256] # CHECK-NEXT: 1 3 1.00 * ldursh w15, [x21, #-256]
# CHECK-NEXT: 1 4 1.00 * stur b0, [sp, #1] # CHECK-NEXT: 1 1 1.00 * stur b0, [sp, #1]
# CHECK-NEXT: 1 4 1.00 * stur h12, [x12, #-1] # CHECK-NEXT: 1 1 1.00 * stur h12, [x12, #-1]
# CHECK-NEXT: 1 4 1.00 * stur s15, [x0, #255] # CHECK-NEXT: 1 1 1.00 * stur s15, [x0, #255]
# CHECK-NEXT: 1 4 1.00 * stur d31, [x5, #25] # CHECK-NEXT: 1 1 1.00 * stur d31, [x5, #25]
# CHECK-NEXT: 1 4 1.00 * stur q9, [x5] # CHECK-NEXT: 1 1 1.00 * stur q9, [x5]
# CHECK-NEXT: 1 3 1.00 * ldur b3, [sp] # CHECK-NEXT: 1 3 1.00 * ldur b3, [sp]
# CHECK-NEXT: 1 3 1.00 * ldur h5, [x4, #-256] # CHECK-NEXT: 1 3 1.00 * ldur h5, [x4, #-256]
# CHECK-NEXT: 1 3 1.00 * ldur s7, [x12, #-1] # CHECK-NEXT: 1 3 1.00 * ldur s7, [x12, #-1]
# CHECK-NEXT: 1 3 1.00 * ldur d11, [x19, #4] # CHECK-NEXT: 1 3 1.00 * ldur d11, [x19, #4]
# CHECK-NEXT: 1 3 1.00 * ldur q13, [x1, #2] # CHECK-NEXT: 1 3 1.00 * ldur q13, [x1, #2]
# CHECK-NEXT: 2 4 1.00 * strb w9, [x2], #255 # CHECK-NEXT: 2 1 1.00 * strb w9, [x2], #255
# CHECK-NEXT: 2 4 1.00 * strb w10, [x3], #1 # CHECK-NEXT: 2 1 1.00 * strb w10, [x3], #1
# CHECK-NEXT: 2 4 1.00 * strb w10, [x3], #-256 # CHECK-NEXT: 2 1 1.00 * strb w10, [x3], #-256
# CHECK-NEXT: 2 4 1.00 * strh w9, [x2], #255 # CHECK-NEXT: 2 1 1.00 * strh w9, [x2], #255
# CHECK-NEXT: 2 4 1.00 * strh w9, [x2], #1 # CHECK-NEXT: 2 1 1.00 * strh w9, [x2], #1
# CHECK-NEXT: 2 4 1.00 * strh w10, [x3], #-256 # CHECK-NEXT: 2 1 1.00 * strh w10, [x3], #-256
# CHECK-NEXT: 2 4 1.00 * str w19, [sp], #255 # CHECK-NEXT: 2 1 1.00 * str w19, [sp], #255
# CHECK-NEXT: 2 4 1.00 * str w20, [x30], #1 # CHECK-NEXT: 2 1 1.00 * str w20, [x30], #1
# CHECK-NEXT: 2 4 1.00 * str w21, [x12], #-256 # CHECK-NEXT: 2 1 1.00 * str w21, [x12], #-256
# CHECK-NEXT: 2 4 1.00 * str xzr, [x9], #255 # CHECK-NEXT: 2 1 1.00 * str xzr, [x9], #255
# CHECK-NEXT: 2 4 1.00 * str x2, [x3], #1 # CHECK-NEXT: 2 1 1.00 * str x2, [x3], #1
# CHECK-NEXT: 2 4 1.00 * str x19, [x12], #-256 # CHECK-NEXT: 2 1 1.00 * str x19, [x12], #-256
# CHECK-NEXT: 2 3 1.00 * ldrb w9, [x2], #255 # CHECK-NEXT: 2 3 1.00 * ldrb w9, [x2], #255
# CHECK-NEXT: 2 3 1.00 * ldrb w10, [x3], #1 # CHECK-NEXT: 2 3 1.00 * ldrb w10, [x3], #1
# CHECK-NEXT: 2 3 1.00 * ldrb w10, [x3], #-256 # CHECK-NEXT: 2 3 1.00 * ldrb w10, [x3], #-256
# CHECK-NEXT: 2 3 1.00 * ldrh w9, [x2], #255 # CHECK-NEXT: 2 3 1.00 * ldrh w9, [x2], #255
# CHECK-NEXT: 2 3 1.00 * ldrh w9, [x2], #1 # CHECK-NEXT: 2 3 1.00 * ldrh w9, [x2], #1
# CHECK-NEXT: 2 3 1.00 * ldrh w10, [x3], #-256 # CHECK-NEXT: 2 3 1.00 * ldrh w10, [x3], #-256
# CHECK-NEXT: 2 3 1.00 * ldr w19, [sp], #255 # CHECK-NEXT: 2 3 1.00 * ldr w19, [sp], #255
# CHECK-NEXT: 2 3 1.00 * ldr w20, [x30], #1 # CHECK-NEXT: 2 3 1.00 * ldr w20, [x30], #1
Show All 11 Lines
# CHECK-NEXT: 2 3 1.00 * ldrsw x2, [x3], #1 # CHECK-NEXT: 2 3 1.00 * ldrsw x2, [x3], #1
# CHECK-NEXT: 2 3 1.00 * ldrsw x19, [x12], #-256 # CHECK-NEXT: 2 3 1.00 * ldrsw x19, [x12], #-256
# CHECK-NEXT: 2 3 1.00 * ldrsb wzr, [x9], #255 # CHECK-NEXT: 2 3 1.00 * ldrsb wzr, [x9], #255
# CHECK-NEXT: 2 3 1.00 * ldrsb w2, [x3], #1 # CHECK-NEXT: 2 3 1.00 * ldrsb w2, [x3], #1
# CHECK-NEXT: 2 3 1.00 * ldrsb w19, [x12], #-256 # CHECK-NEXT: 2 3 1.00 * ldrsb w19, [x12], #-256
# CHECK-NEXT: 2 3 1.00 * ldrsh wzr, [x9], #255 # CHECK-NEXT: 2 3 1.00 * ldrsh wzr, [x9], #255
# CHECK-NEXT: 2 3 1.00 * ldrsh w2, [x3], #1 # CHECK-NEXT: 2 3 1.00 * ldrsh w2, [x3], #1
# CHECK-NEXT: 2 3 1.00 * ldrsh w19, [x12], #-256 # CHECK-NEXT: 2 3 1.00 * ldrsh w19, [x12], #-256
# CHECK-NEXT: 2 4 1.00 * str b0, [x0], #255 # CHECK-NEXT: 2 1 1.00 * str b0, [x0], #255
# CHECK-NEXT: 2 4 1.00 * str b3, [x3], #1 # CHECK-NEXT: 2 1 1.00 * str b3, [x3], #1
# CHECK-NEXT: 2 4 1.00 * str b5, [sp], #-256 # CHECK-NEXT: 2 1 1.00 * str b5, [sp], #-256
# CHECK-NEXT: 2 4 1.00 * str h10, [x10], #255 # CHECK-NEXT: 2 1 1.00 * str h10, [x10], #255
# CHECK-NEXT: 2 4 1.00 * str h13, [x23], #1 # CHECK-NEXT: 2 1 1.00 * str h13, [x23], #1
# CHECK-NEXT: 2 4 1.00 * str h15, [sp], #-256 # CHECK-NEXT: 2 1 1.00 * str h15, [sp], #-256
# CHECK-NEXT: 2 4 1.00 * str s20, [x20], #255 # CHECK-NEXT: 2 1 1.00 * str s20, [x20], #255
# CHECK-NEXT: 2 4 1.00 * str s23, [x23], #1 # CHECK-NEXT: 2 1 1.00 * str s23, [x23], #1
# CHECK-NEXT: 2 4 1.00 * str s25, [x0], #-256 # CHECK-NEXT: 2 1 1.00 * str s25, [x0], #-256
# CHECK-NEXT: 2 4 1.00 * str d20, [x20], #255 # CHECK-NEXT: 2 1 1.00 * str d20, [x20], #255
# CHECK-NEXT: 2 4 1.00 * str d23, [x23], #1 # CHECK-NEXT: 2 1 1.00 * str d23, [x23], #1
# CHECK-NEXT: 2 4 1.00 * str d25, [x0], #-256 # CHECK-NEXT: 2 1 1.00 * str d25, [x0], #-256
# CHECK-NEXT: 2 3 1.00 * ldr b0, [x0], #255 # CHECK-NEXT: 2 3 1.00 * ldr b0, [x0], #255
# CHECK-NEXT: 2 3 1.00 * ldr b3, [x3], #1 # CHECK-NEXT: 2 3 1.00 * ldr b3, [x3], #1
# CHECK-NEXT: 2 3 1.00 * ldr b5, [sp], #-256 # CHECK-NEXT: 2 3 1.00 * ldr b5, [sp], #-256
# CHECK-NEXT: 2 3 1.00 * ldr h10, [x10], #255 # CHECK-NEXT: 2 3 1.00 * ldr h10, [x10], #255
# CHECK-NEXT: 2 3 1.00 * ldr h13, [x23], #1 # CHECK-NEXT: 2 3 1.00 * ldr h13, [x23], #1
# CHECK-NEXT: 2 3 1.00 * ldr h15, [sp], #-256 # CHECK-NEXT: 2 3 1.00 * ldr h15, [sp], #-256
# CHECK-NEXT: 2 3 1.00 * ldr s20, [x20], #255 # CHECK-NEXT: 2 3 1.00 * ldr s20, [x20], #255
# CHECK-NEXT: 2 3 1.00 * ldr s23, [x23], #1 # CHECK-NEXT: 2 3 1.00 * ldr s23, [x23], #1
# CHECK-NEXT: 2 3 1.00 * ldr s25, [x0], #-256 # CHECK-NEXT: 2 3 1.00 * ldr s25, [x0], #-256
# CHECK-NEXT: 2 3 1.00 * ldr d20, [x20], #255 # CHECK-NEXT: 2 3 1.00 * ldr d20, [x20], #255
# CHECK-NEXT: 2 3 1.00 * ldr d23, [x23], #1 # CHECK-NEXT: 2 3 1.00 * ldr d23, [x23], #1
# CHECK-NEXT: 2 3 1.00 * ldr d25, [x0], #-256 # CHECK-NEXT: 2 3 1.00 * ldr d25, [x0], #-256
# CHECK-NEXT: 2 3 1.00 * ldr q20, [x1], #255 # CHECK-NEXT: 2 3 1.00 * ldr q20, [x1], #255
# CHECK-NEXT: 2 3 1.00 * ldr q23, [x9], #1 # CHECK-NEXT: 2 3 1.00 * ldr q23, [x9], #1
# CHECK-NEXT: 2 3 1.00 * ldr q25, [x20], #-256 # CHECK-NEXT: 2 3 1.00 * ldr q25, [x20], #-256
# CHECK-NEXT: 2 4 1.00 * str q10, [x1], #255 # CHECK-NEXT: 2 1 1.00 * str q10, [x1], #255
# CHECK-NEXT: 2 4 1.00 * str q22, [sp], #1 # CHECK-NEXT: 2 1 1.00 * str q22, [sp], #1
# CHECK-NEXT: 2 4 1.00 * str q21, [x20], #-256 # CHECK-NEXT: 2 1 1.00 * str q21, [x20], #-256
# CHECK-NEXT: 2 3 1.00 * ldr x3, [x4, #0]! # CHECK-NEXT: 2 3 1.00 * ldr x3, [x4, #0]!
# CHECK-NEXT: 2 4 1.00 * strb w9, [x2, #255]! # CHECK-NEXT: 2 1 1.00 * strb w9, [x2, #255]!
# CHECK-NEXT: 2 4 1.00 * strb w10, [x3, #1]! # CHECK-NEXT: 2 1 1.00 * strb w10, [x3, #1]!
# CHECK-NEXT: 2 4 1.00 * strb w10, [x3, #-256]! # CHECK-NEXT: 2 1 1.00 * strb w10, [x3, #-256]!
# CHECK-NEXT: 2 4 1.00 * strh w9, [x2, #255]! # CHECK-NEXT: 2 1 1.00 * strh w9, [x2, #255]!
# CHECK-NEXT: 2 4 1.00 * strh w9, [x2, #1]! # CHECK-NEXT: 2 1 1.00 * strh w9, [x2, #1]!
# CHECK-NEXT: 2 4 1.00 * strh w10, [x3, #-256]! # CHECK-NEXT: 2 1 1.00 * strh w10, [x3, #-256]!
# CHECK-NEXT: 2 4 1.00 * str w19, [sp, #255]! # CHECK-NEXT: 2 1 1.00 * str w19, [sp, #255]!
# CHECK-NEXT: 2 4 1.00 * str w20, [x30, #1]! # CHECK-NEXT: 2 1 1.00 * str w20, [x30, #1]!
# CHECK-NEXT: 2 4 1.00 * str w21, [x12, #-256]! # CHECK-NEXT: 2 1 1.00 * str w21, [x12, #-256]!
# CHECK-NEXT: 2 4 1.00 * str xzr, [x9, #255]! # CHECK-NEXT: 2 1 1.00 * str xzr, [x9, #255]!
# CHECK-NEXT: 2 4 1.00 * str x2, [x3, #1]! # CHECK-NEXT: 2 1 1.00 * str x2, [x3, #1]!
# CHECK-NEXT: 2 4 1.00 * str x19, [x12, #-256]! # CHECK-NEXT: 2 1 1.00 * str x19, [x12, #-256]!
# CHECK-NEXT: 2 3 1.00 * ldrb w9, [x2, #255]! # CHECK-NEXT: 2 3 1.00 * ldrb w9, [x2, #255]!
# CHECK-NEXT: 2 3 1.00 * ldrb w10, [x3, #1]! # CHECK-NEXT: 2 3 1.00 * ldrb w10, [x3, #1]!
# CHECK-NEXT: 2 3 1.00 * ldrb w10, [x3, #-256]! # CHECK-NEXT: 2 3 1.00 * ldrb w10, [x3, #-256]!
# CHECK-NEXT: 2 3 1.00 * ldrh w9, [x2, #255]! # CHECK-NEXT: 2 3 1.00 * ldrh w9, [x2, #255]!
# CHECK-NEXT: 2 3 1.00 * ldrh w9, [x2, #1]! # CHECK-NEXT: 2 3 1.00 * ldrh w9, [x2, #1]!
# CHECK-NEXT: 2 3 1.00 * ldrh w10, [x3, #-256]! # CHECK-NEXT: 2 3 1.00 * ldrh w10, [x3, #-256]!
# CHECK-NEXT: 2 3 1.00 * ldr w19, [sp, #255]! # CHECK-NEXT: 2 3 1.00 * ldr w19, [sp, #255]!
# CHECK-NEXT: 2 3 1.00 * ldr w20, [x30, #1]! # CHECK-NEXT: 2 3 1.00 * ldr w20, [x30, #1]!
Show All 11 Lines
# CHECK-NEXT: 2 3 1.00 * ldrsw x2, [x3, #1]! # CHECK-NEXT: 2 3 1.00 * ldrsw x2, [x3, #1]!
# CHECK-NEXT: 2 3 1.00 * ldrsw x19, [x12, #-256]! # CHECK-NEXT: 2 3 1.00 * ldrsw x19, [x12, #-256]!
# CHECK-NEXT: 2 3 1.00 * ldrsb wzr, [x9, #255]! # CHECK-NEXT: 2 3 1.00 * ldrsb wzr, [x9, #255]!
# CHECK-NEXT: 2 3 1.00 * ldrsb w2, [x3, #1]! # CHECK-NEXT: 2 3 1.00 * ldrsb w2, [x3, #1]!
# CHECK-NEXT: 2 3 1.00 * ldrsb w19, [x12, #-256]! # CHECK-NEXT: 2 3 1.00 * ldrsb w19, [x12, #-256]!
# CHECK-NEXT: 2 3 1.00 * ldrsh wzr, [x9, #255]! # CHECK-NEXT: 2 3 1.00 * ldrsh wzr, [x9, #255]!
# CHECK-NEXT: 2 3 1.00 * ldrsh w2, [x3, #1]! # CHECK-NEXT: 2 3 1.00 * ldrsh w2, [x3, #1]!
# CHECK-NEXT: 2 3 1.00 * ldrsh w19, [x12, #-256]! # CHECK-NEXT: 2 3 1.00 * ldrsh w19, [x12, #-256]!
# CHECK-NEXT: 2 4 1.00 * str b0, [x0, #255]! # CHECK-NEXT: 2 1 1.00 * str b0, [x0, #255]!
# CHECK-NEXT: 2 4 1.00 * str b3, [x3, #1]! # CHECK-NEXT: 2 1 1.00 * str b3, [x3, #1]!
# CHECK-NEXT: 2 4 1.00 * str b5, [sp, #-256]! # CHECK-NEXT: 2 1 1.00 * str b5, [sp, #-256]!
# CHECK-NEXT: 2 4 1.00 * str h10, [x10, #255]! # CHECK-NEXT: 2 1 1.00 * str h10, [x10, #255]!
# CHECK-NEXT: 2 4 1.00 * str h13, [x23, #1]! # CHECK-NEXT: 2 1 1.00 * str h13, [x23, #1]!
# CHECK-NEXT: 2 4 1.00 * str h15, [sp, #-256]! # CHECK-NEXT: 2 1 1.00 * str h15, [sp, #-256]!
# CHECK-NEXT: 2 4 1.00 * str s20, [x20, #255]! # CHECK-NEXT: 2 1 1.00 * str s20, [x20, #255]!
# CHECK-NEXT: 2 4 1.00 * str s23, [x23, #1]! # CHECK-NEXT: 2 1 1.00 * str s23, [x23, #1]!
# CHECK-NEXT: 2 4 1.00 * str s25, [x0, #-256]! # CHECK-NEXT: 2 1 1.00 * str s25, [x0, #-256]!
# CHECK-NEXT: 2 4 1.00 * str d20, [x20, #255]! # CHECK-NEXT: 2 1 1.00 * str d20, [x20, #255]!
# CHECK-NEXT: 2 4 1.00 * str d23, [x23, #1]! # CHECK-NEXT: 2 1 1.00 * str d23, [x23, #1]!
# CHECK-NEXT: 2 4 1.00 * str d25, [x0, #-256]! # CHECK-NEXT: 2 1 1.00 * str d25, [x0, #-256]!
# CHECK-NEXT: 2 3 1.00 * ldr b0, [x0, #255]! # CHECK-NEXT: 2 3 1.00 * ldr b0, [x0, #255]!
# CHECK-NEXT: 2 3 1.00 * ldr b3, [x3, #1]! # CHECK-NEXT: 2 3 1.00 * ldr b3, [x3, #1]!
# CHECK-NEXT: 2 3 1.00 * ldr b5, [sp, #-256]! # CHECK-NEXT: 2 3 1.00 * ldr b5, [sp, #-256]!
# CHECK-NEXT: 2 3 1.00 * ldr h10, [x10, #255]! # CHECK-NEXT: 2 3 1.00 * ldr h10, [x10, #255]!
# CHECK-NEXT: 2 3 1.00 * ldr h13, [x23, #1]! # CHECK-NEXT: 2 3 1.00 * ldr h13, [x23, #1]!
# CHECK-NEXT: 2 3 1.00 * ldr h15, [sp, #-256]! # CHECK-NEXT: 2 3 1.00 * ldr h15, [sp, #-256]!
# CHECK-NEXT: 2 3 1.00 * ldr s20, [x20, #255]! # CHECK-NEXT: 2 3 1.00 * ldr s20, [x20, #255]!
# CHECK-NEXT: 2 3 1.00 * ldr s23, [x23, #1]! # CHECK-NEXT: 2 3 1.00 * ldr s23, [x23, #1]!
# CHECK-NEXT: 2 3 1.00 * ldr s25, [x0, #-256]! # CHECK-NEXT: 2 3 1.00 * ldr s25, [x0, #-256]!
# CHECK-NEXT: 2 3 1.00 * ldr d20, [x20, #255]! # CHECK-NEXT: 2 3 1.00 * ldr d20, [x20, #255]!
# CHECK-NEXT: 2 3 1.00 * ldr d23, [x23, #1]! # CHECK-NEXT: 2 3 1.00 * ldr d23, [x23, #1]!
# CHECK-NEXT: 2 3 1.00 * ldr d25, [x0, #-256]! # CHECK-NEXT: 2 3 1.00 * ldr d25, [x0, #-256]!
# CHECK-NEXT: 2 3 1.00 * ldr q20, [x1, #255]! # CHECK-NEXT: 2 3 1.00 * ldr q20, [x1, #255]!
# CHECK-NEXT: 2 3 1.00 * ldr q23, [x9, #1]! # CHECK-NEXT: 2 3 1.00 * ldr q23, [x9, #1]!
# CHECK-NEXT: 2 3 1.00 * ldr q25, [x20, #-256]! # CHECK-NEXT: 2 3 1.00 * ldr q25, [x20, #-256]!
# CHECK-NEXT: 2 4 1.00 * str q10, [x1, #255]! # CHECK-NEXT: 2 1 1.00 * str q10, [x1, #255]!
# CHECK-NEXT: 2 4 1.00 * str q22, [sp, #1]! # CHECK-NEXT: 2 1 1.00 * str q22, [sp, #1]!
# CHECK-NEXT: 2 4 1.00 * str q21, [x20, #-256]! # CHECK-NEXT: 2 1 1.00 * str q21, [x20, #-256]!
# CHECK-NEXT: 1 4 1.00 * sttrb w9, [sp] # CHECK-NEXT: 1 1 1.00 * sttrb w9, [sp]
# CHECK-NEXT: 1 4 1.00 * sttrh wzr, [x12, #255] # CHECK-NEXT: 1 1 1.00 * sttrh wzr, [x12, #255]
# CHECK-NEXT: 1 4 1.00 * sttr w16, [x0, #-256] # CHECK-NEXT: 1 1 1.00 * sttr w16, [x0, #-256]
# CHECK-NEXT: 1 4 1.00 * sttr x28, [x14, #1] # CHECK-NEXT: 1 1 1.00 * sttr x28, [x14, #1]
# CHECK-NEXT: 1 3 1.00 * ldtrb w1, [x20, #255] # CHECK-NEXT: 1 3 1.00 * ldtrb w1, [x20, #255]
# CHECK-NEXT: 1 3 1.00 * ldtrh w20, [x1, #255] # CHECK-NEXT: 1 3 1.00 * ldtrh w20, [x1, #255]
# CHECK-NEXT: 1 3 1.00 * ldtr w12, [sp, #255] # CHECK-NEXT: 1 3 1.00 * ldtr w12, [sp, #255]
# CHECK-NEXT: 1 3 1.00 * ldtr xzr, [x12, #255] # CHECK-NEXT: 1 3 1.00 * ldtr xzr, [x12, #255]
# CHECK-NEXT: 1 3 1.00 * ldtrsb x9, [x7, #-256] # CHECK-NEXT: 1 3 1.00 * ldtrsb x9, [x7, #-256]
# CHECK-NEXT: 1 3 1.00 * ldtrsh x17, [x19, #-256] # CHECK-NEXT: 1 3 1.00 * ldtrsh x17, [x19, #-256]
# CHECK-NEXT: 1 3 1.00 * ldtrsw x20, [x15, #-256] # CHECK-NEXT: 1 3 1.00 * ldtrsw x20, [x15, #-256]
# CHECK-NEXT: 1 3 1.00 * ldtrsb w19, [x1, #-256] # CHECK-NEXT: 1 3 1.00 * ldtrsb w19, [x1, #-256]
Show All 10 Lines
# CHECK-NEXT: 1 3 1.00 * ldrh w2, [x4] # CHECK-NEXT: 1 3 1.00 * ldrh w2, [x4]
# CHECK-NEXT: 1 3 1.00 * ldrsh w23, [x6, #8190] # CHECK-NEXT: 1 3 1.00 * ldrsh w23, [x6, #8190]
# CHECK-NEXT: 1 3 1.00 * ldrsh wzr, [sp, #2] # CHECK-NEXT: 1 3 1.00 * ldrsh wzr, [sp, #2]
# CHECK-NEXT: 1 3 1.00 * ldrsh x29, [x2, #2] # CHECK-NEXT: 1 3 1.00 * ldrsh x29, [x2, #2]
# CHECK-NEXT: 1 3 1.00 * ldrb w26, [x3, #121] # CHECK-NEXT: 1 3 1.00 * ldrb w26, [x3, #121]
# CHECK-NEXT: 1 3 1.00 * ldrb w12, [x2] # CHECK-NEXT: 1 3 1.00 * ldrb w12, [x2]
# CHECK-NEXT: 1 3 1.00 * ldrsb w27, [sp, #4095] # CHECK-NEXT: 1 3 1.00 * ldrsb w27, [sp, #4095]
# CHECK-NEXT: 1 3 1.00 * ldrsb xzr, [x15] # CHECK-NEXT: 1 3 1.00 * ldrsb xzr, [x15]
# CHECK-NEXT: 1 4 1.00 * str x30, [sp] # CHECK-NEXT: 1 1 1.00 * str x30, [sp]
# CHECK-NEXT: 1 4 1.00 * str w20, [x4, #16380] # CHECK-NEXT: 1 1 1.00 * str w20, [x4, #16380]
# CHECK-NEXT: 1 4 1.00 * strh w17, [sp, #8190] # CHECK-NEXT: 1 1 1.00 * strh w17, [sp, #8190]
# CHECK-NEXT: 1 4 1.00 * strb w23, [x3, #4095] # CHECK-NEXT: 1 1 1.00 * strb w23, [x3, #4095]
# CHECK-NEXT: 1 4 1.00 * strb wzr, [x2] # CHECK-NEXT: 1 1 1.00 * strb wzr, [x2]
# CHECK-NEXT: 1 3 1.00 * ldr b31, [sp, #4095] # CHECK-NEXT: 1 3 1.00 * ldr b31, [sp, #4095]
# CHECK-NEXT: 1 3 1.00 * ldr h20, [x2, #8190] # CHECK-NEXT: 1 3 1.00 * ldr h20, [x2, #8190]
# CHECK-NEXT: 1 3 1.00 * ldr s10, [x19, #16380] # CHECK-NEXT: 1 3 1.00 * ldr s10, [x19, #16380]
# CHECK-NEXT: 1 3 1.00 * ldr d3, [x10, #32760] # CHECK-NEXT: 1 3 1.00 * ldr d3, [x10, #32760]
# CHECK-NEXT: 1 4 1.00 * str q12, [sp, #65520] # CHECK-NEXT: 1 1 1.00 * str q12, [sp, #65520]
# CHECK-NEXT: 1 4 1.00 * ldrb w3, [sp, x5] # CHECK-NEXT: 1 4 1.00 * ldrb w3, [sp, x5]
# CHECK-NEXT: 1 4 1.00 * ldrb w9, [x27, x6] # CHECK-NEXT: 1 4 1.00 * ldrb w9, [x27, x6]
# CHECK-NEXT: 1 4 1.00 * ldrsb w10, [x30, x7] # CHECK-NEXT: 1 4 1.00 * ldrsb w10, [x30, x7]
# CHECK-NEXT: 1 4 1.00 * ldrb w11, [x29, x3, sxtx] # CHECK-NEXT: 1 4 1.00 * ldrb w11, [x29, x3, sxtx]
# CHECK-NEXT: 1 4 1.00 * strb w12, [x28, xzr, sxtx] # CHECK-NEXT: 1 1 1.00 * strb w12, [x28, xzr, sxtx]
# CHECK-NEXT: 1 4 1.00 * ldrb w14, [x26, w6, uxtw] # CHECK-NEXT: 1 4 1.00 * ldrb w14, [x26, w6, uxtw]
# CHECK-NEXT: 1 4 1.00 * ldrsb w15, [x25, w7, uxtw] # CHECK-NEXT: 1 4 1.00 * ldrsb w15, [x25, w7, uxtw]
# CHECK-NEXT: 1 4 1.00 * ldrb w17, [x23, w9, sxtw] # CHECK-NEXT: 1 4 1.00 * ldrb w17, [x23, w9, sxtw]
# CHECK-NEXT: 1 4 1.00 * ldrsb x18, [x22, w10, sxtw] # CHECK-NEXT: 1 4 1.00 * ldrsb x18, [x22, w10, sxtw]
# CHECK-NEXT: 1 4 1.00 * ldrsh w3, [sp, x5] # CHECK-NEXT: 1 4 1.00 * ldrsh w3, [sp, x5]
# CHECK-NEXT: 1 4 1.00 * ldrsh w9, [x27, x6] # CHECK-NEXT: 1 4 1.00 * ldrsh w9, [x27, x6]
# CHECK-NEXT: 1 4 1.00 * ldrh w10, [x30, x7, lsl #1] # CHECK-NEXT: 1 4 1.00 * ldrh w10, [x30, x7, lsl #1]
# CHECK-NEXT: 1 4 1.00 * strh w11, [x29, x3, sxtx] # CHECK-NEXT: 1 1 1.00 * strh w11, [x29, x3, sxtx]
# CHECK-NEXT: 1 4 1.00 * ldrh w12, [x28, xzr, sxtx] # CHECK-NEXT: 1 4 1.00 * ldrh w12, [x28, xzr, sxtx]
# CHECK-NEXT: 1 4 1.00 * ldrsh x13, [x27, x5, sxtx #1] # CHECK-NEXT: 1 4 1.00 * ldrsh x13, [x27, x5, sxtx #1]
# CHECK-NEXT: 1 4 1.00 * ldrh w14, [x26, w6, uxtw] # CHECK-NEXT: 1 4 1.00 * ldrh w14, [x26, w6, uxtw]
# CHECK-NEXT: 1 4 1.00 * ldrh w15, [x25, w7, uxtw] # CHECK-NEXT: 1 4 1.00 * ldrh w15, [x25, w7, uxtw]
# CHECK-NEXT: 1 4 1.00 * ldrsh w16, [x24, w8, uxtw #1] # CHECK-NEXT: 1 4 1.00 * ldrsh w16, [x24, w8, uxtw #1]
# CHECK-NEXT: 1 4 1.00 * ldrh w17, [x23, w9, sxtw] # CHECK-NEXT: 1 4 1.00 * ldrh w17, [x23, w9, sxtw]
# CHECK-NEXT: 1 4 1.00 * ldrh w18, [x22, w10, sxtw] # CHECK-NEXT: 1 4 1.00 * ldrh w18, [x22, w10, sxtw]
# CHECK-NEXT: 1 4 1.00 * strh w19, [x21, wzr, sxtw #1] # CHECK-NEXT: 1 1 1.00 * strh w19, [x21, wzr, sxtw #1]
# CHECK-NEXT: 1 4 1.00 * ldr w3, [sp, x5] # CHECK-NEXT: 1 4 1.00 * ldr w3, [sp, x5]
# CHECK-NEXT: 1 4 1.00 * ldr s9, [x27, x6] # CHECK-NEXT: 1 4 1.00 * ldr s9, [x27, x6]
# CHECK-NEXT: 1 4 1.00 * ldr w10, [x30, x7, lsl #2] # CHECK-NEXT: 1 4 1.00 * ldr w10, [x30, x7, lsl #2]
# CHECK-NEXT: 1 4 1.00 * ldr w11, [x29, x3, sxtx] # CHECK-NEXT: 1 4 1.00 * ldr w11, [x29, x3, sxtx]
# CHECK-NEXT: 1 4 1.00 * str s12, [x28, xzr, sxtx] # CHECK-NEXT: 1 1 1.00 * str s12, [x28, xzr, sxtx]
# CHECK-NEXT: 1 4 1.00 * str w13, [x27, x5, sxtx #2] # CHECK-NEXT: 1 1 1.00 * str w13, [x27, x5, sxtx #2]
# CHECK-NEXT: 1 4 1.00 * str w14, [x26, w6, uxtw] # CHECK-NEXT: 1 1 1.00 * str w14, [x26, w6, uxtw]
# CHECK-NEXT: 1 4 1.00 * ldr w15, [x25, w7, uxtw] # CHECK-NEXT: 1 4 1.00 * ldr w15, [x25, w7, uxtw]
# CHECK-NEXT: 1 4 1.00 * ldr w16, [x24, w8, uxtw #2] # CHECK-NEXT: 1 4 1.00 * ldr w16, [x24, w8, uxtw #2]
# CHECK-NEXT: 1 4 1.00 * ldrsw x17, [x23, w9, sxtw] # CHECK-NEXT: 1 4 1.00 * ldrsw x17, [x23, w9, sxtw]
# CHECK-NEXT: 1 4 1.00 * ldr w18, [x22, w10, sxtw] # CHECK-NEXT: 1 4 1.00 * ldr w18, [x22, w10, sxtw]
# CHECK-NEXT: 1 4 1.00 * ldrsw x19, [x21, wzr, sxtw #2] # CHECK-NEXT: 1 4 1.00 * ldrsw x19, [x21, wzr, sxtw #2]
# CHECK-NEXT: 1 4 1.00 * ldr x3, [sp, x5] # CHECK-NEXT: 1 4 1.00 * ldr x3, [sp, x5]
# CHECK-NEXT: 1 4 1.00 * str x9, [x27, x6] # CHECK-NEXT: 1 1 1.00 * str x9, [x27, x6]
# CHECK-NEXT: 1 4 1.00 * ldr d10, [x30, x7, lsl #3] # CHECK-NEXT: 1 4 1.00 * ldr d10, [x30, x7, lsl #3]
# CHECK-NEXT: 1 4 1.00 * str x11, [x29, x3, sxtx] # CHECK-NEXT: 1 1 1.00 * str x11, [x29, x3, sxtx]
# CHECK-NEXT: 1 4 1.00 * ldr x12, [x28, xzr, sxtx] # CHECK-NEXT: 1 4 1.00 * ldr x12, [x28, xzr, sxtx]
# CHECK-NEXT: 1 4 1.00 * ldr x13, [x27, x5, sxtx #3] # CHECK-NEXT: 1 4 1.00 * ldr x13, [x27, x5, sxtx #3]
# CHECK-NEXT: 1 3 1.00 U prfm pldl1keep, [x26, w6, uxtw] # CHECK-NEXT: 1 3 1.00 U prfm pldl1keep, [x26, w6, uxtw]
# CHECK-NEXT: 1 4 1.00 * ldr x15, [x25, w7, uxtw] # CHECK-NEXT: 1 4 1.00 * ldr x15, [x25, w7, uxtw]
# CHECK-NEXT: 1 4 1.00 * ldr x16, [x24, w8, uxtw #3] # CHECK-NEXT: 1 4 1.00 * ldr x16, [x24, w8, uxtw #3]
# CHECK-NEXT: 1 4 1.00 * ldr x17, [x23, w9, sxtw] # CHECK-NEXT: 1 4 1.00 * ldr x17, [x23, w9, sxtw]
# CHECK-NEXT: 1 4 1.00 * ldr x18, [x22, w10, sxtw] # CHECK-NEXT: 1 4 1.00 * ldr x18, [x22, w10, sxtw]
# CHECK-NEXT: 1 4 1.00 * str d19, [x21, wzr, sxtw #3] # CHECK-NEXT: 1 1 1.00 * str d19, [x21, wzr, sxtw #3]
# CHECK-NEXT: 1 4 1.00 * ldr q3, [sp, x5] # CHECK-NEXT: 1 4 1.00 * ldr q3, [sp, x5]
# CHECK-NEXT: 1 4 1.00 * ldr q9, [x27, x6] # CHECK-NEXT: 1 4 1.00 * ldr q9, [x27, x6]
# CHECK-NEXT: 1 4 1.00 * ldr q10, [x30, x7, lsl #4] # CHECK-NEXT: 1 4 1.00 * ldr q10, [x30, x7, lsl #4]
# CHECK-NEXT: 1 4 1.00 * str q11, [x29, x3, sxtx] # CHECK-NEXT: 1 1 1.00 * str q11, [x29, x3, sxtx]
# CHECK-NEXT: 1 4 1.00 * str q12, [x28, xzr, sxtx] # CHECK-NEXT: 1 1 1.00 * str q12, [x28, xzr, sxtx]
# CHECK-NEXT: 1 4 1.00 * str q13, [x27, x5, sxtx #4] # CHECK-NEXT: 1 1 1.00 * str q13, [x27, x5, sxtx #4]
# CHECK-NEXT: 1 4 1.00 * ldr q14, [x26, w6, uxtw] # CHECK-NEXT: 1 4 1.00 * ldr q14, [x26, w6, uxtw]
# CHECK-NEXT: 1 4 1.00 * ldr q15, [x25, w7, uxtw] # CHECK-NEXT: 1 4 1.00 * ldr q15, [x25, w7, uxtw]
# CHECK-NEXT: 1 4 1.00 * ldr q16, [x24, w8, uxtw #4] # CHECK-NEXT: 1 4 1.00 * ldr q16, [x24, w8, uxtw #4]
# CHECK-NEXT: 1 4 1.00 * ldr q17, [x23, w9, sxtw] # CHECK-NEXT: 1 4 1.00 * ldr q17, [x23, w9, sxtw]
# CHECK-NEXT: 1 4 1.00 * str q18, [x22, w10, sxtw] # CHECK-NEXT: 1 1 1.00 * str q18, [x22, w10, sxtw]
# CHECK-NEXT: 1 4 1.00 * ldr q19, [x21, wzr, sxtw #4] # CHECK-NEXT: 1 4 1.00 * ldr q19, [x21, wzr, sxtw #4]
# CHECK-NEXT: 2 5 3.00 * ldp w3, w5, [sp] # CHECK-NEXT: 2 5 3.00 * ldp w3, w5, [sp]
# CHECK-NEXT: 1 4 1.00 * stp wzr, w9, [sp, #252] # CHECK-NEXT: 1 1 1.00 * stp wzr, w9, [sp, #252]
# CHECK-NEXT: 2 5 3.00 * ldp w2, wzr, [sp, #-256] # CHECK-NEXT: 2 5 3.00 * ldp w2, wzr, [sp, #-256]
# CHECK-NEXT: 2 5 3.00 * ldp w9, w10, [sp, #4] # CHECK-NEXT: 2 5 3.00 * ldp w9, w10, [sp, #4]
# CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [sp, #4] # CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [sp, #4]
# CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [x2, #-256] # CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [x2, #-256]
# CHECK-NEXT: 2 5 3.00 * ldpsw x20, x30, [sp, #252] # CHECK-NEXT: 2 5 3.00 * ldpsw x20, x30, [sp, #252]
# CHECK-NEXT: 2 5 3.00 * ldp x21, x29, [x2, #504] # CHECK-NEXT: 2 5 3.00 * ldp x21, x29, [x2, #504]
# CHECK-NEXT: 2 5 3.00 * ldp x22, x23, [x3, #-512] # CHECK-NEXT: 2 5 3.00 * ldp x22, x23, [x3, #-512]
# CHECK-NEXT: 2 5 3.00 * ldp x24, x25, [x4, #8] # CHECK-NEXT: 2 5 3.00 * ldp x24, x25, [x4, #8]
# CHECK-NEXT: 2 5 3.00 * ldp s29, s28, [sp, #252] # CHECK-NEXT: 2 5 3.00 * ldp s29, s28, [sp, #252]
# CHECK-NEXT: 1 4 1.00 * stp s27, s26, [sp, #-256] # CHECK-NEXT: 1 1 1.00 * stp s27, s26, [sp, #-256]
# CHECK-NEXT: 2 5 3.00 * ldp s1, s2, [x3, #44] # CHECK-NEXT: 2 5 3.00 * ldp s1, s2, [x3, #44]
# CHECK-NEXT: 1 4 1.00 * stp d3, d5, [x9, #504] # CHECK-NEXT: 1 1 1.00 * stp d3, d5, [x9, #504]
# CHECK-NEXT: 1 4 1.00 * stp d7, d11, [x10, #-512] # CHECK-NEXT: 1 1 1.00 * stp d7, d11, [x10, #-512]
# CHECK-NEXT: 2 5 3.00 * ldp d2, d3, [x30, #-8] # CHECK-NEXT: 2 5 3.00 * ldp d2, d3, [x30, #-8]
# CHECK-NEXT: 1 4 1.00 * stp q3, q5, [sp] # CHECK-NEXT: 1 1 1.00 * stp q3, q5, [sp]
# CHECK-NEXT: 1 4 1.00 * stp q17, q19, [sp, #1008] # CHECK-NEXT: 1 1 1.00 * stp q17, q19, [sp, #1008]
# CHECK-NEXT: 2 5 3.00 * ldp q23, q29, [x1, #-1024] # CHECK-NEXT: 2 5 3.00 * ldp q23, q29, [x1, #-1024]
# CHECK-NEXT: 2 5 3.00 * ldp w3, w5, [sp], #0 # CHECK-NEXT: 2 5 3.00 * ldp w3, w5, [sp], #0
# CHECK-NEXT: 2 4 1.00 * stp wzr, w9, [sp], #252 # CHECK-NEXT: 2 1 1.00 * stp wzr, w9, [sp], #252
# CHECK-NEXT: 2 5 3.00 * ldp w2, wzr, [sp], #-256 # CHECK-NEXT: 2 5 3.00 * ldp w2, wzr, [sp], #-256
# CHECK-NEXT: 2 5 3.00 * ldp w9, w10, [sp], #4 # CHECK-NEXT: 2 5 3.00 * ldp w9, w10, [sp], #4
# CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [sp], #4 # CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [sp], #4
# CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [x2], #-256 # CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [x2], #-256
# CHECK-NEXT: 2 5 3.00 * ldpsw x20, x30, [sp], #252 # CHECK-NEXT: 2 5 3.00 * ldpsw x20, x30, [sp], #252
# CHECK-NEXT: 2 5 3.00 * ldp x21, x29, [x2], #504 # CHECK-NEXT: 2 5 3.00 * ldp x21, x29, [x2], #504
# CHECK-NEXT: 2 5 3.00 * ldp x22, x23, [x3], #-512 # CHECK-NEXT: 2 5 3.00 * ldp x22, x23, [x3], #-512
# CHECK-NEXT: 2 5 3.00 * ldp x24, x25, [x4], #8 # CHECK-NEXT: 2 5 3.00 * ldp x24, x25, [x4], #8
# CHECK-NEXT: 2 5 3.00 * ldp s29, s28, [sp], #252 # CHECK-NEXT: 2 5 3.00 * ldp s29, s28, [sp], #252
# CHECK-NEXT: 2 4 1.00 * stp s27, s26, [sp], #-256 # CHECK-NEXT: 2 1 1.00 * stp s27, s26, [sp], #-256
# CHECK-NEXT: 2 5 3.00 * ldp s1, s2, [x3], #44 # CHECK-NEXT: 2 5 3.00 * ldp s1, s2, [x3], #44
# CHECK-NEXT: 2 4 1.00 * stp d3, d5, [x9], #504 # CHECK-NEXT: 2 1 1.00 * stp d3, d5, [x9], #504
# CHECK-NEXT: 2 4 1.00 * stp d7, d11, [x10], #-512 # CHECK-NEXT: 2 1 1.00 * stp d7, d11, [x10], #-512
# CHECK-NEXT: 2 5 3.00 * ldp d2, d3, [x30], #-8 # CHECK-NEXT: 2 5 3.00 * ldp d2, d3, [x30], #-8
# CHECK-NEXT: 2 4 1.00 * stp q3, q5, [sp], #0 # CHECK-NEXT: 2 1 1.00 * stp q3, q5, [sp], #0
# CHECK-NEXT: 2 4 1.00 * stp q17, q19, [sp], #1008 # CHECK-NEXT: 2 1 1.00 * stp q17, q19, [sp], #1008
# CHECK-NEXT: 2 5 3.00 * ldp q23, q29, [x1], #-1024 # CHECK-NEXT: 2 5 3.00 * ldp q23, q29, [x1], #-1024
# CHECK-NEXT: 2 5 3.00 * ldp w3, w5, [sp, #0]! # CHECK-NEXT: 2 5 3.00 * ldp w3, w5, [sp, #0]!
# CHECK-NEXT: 2 4 1.00 * stp wzr, w9, [sp, #252]! # CHECK-NEXT: 2 1 1.00 * stp wzr, w9, [sp, #252]!
# CHECK-NEXT: 2 5 3.00 * ldp w2, wzr, [sp, #-256]! # CHECK-NEXT: 2 5 3.00 * ldp w2, wzr, [sp, #-256]!
# CHECK-NEXT: 2 5 3.00 * ldp w9, w10, [sp, #4]! # CHECK-NEXT: 2 5 3.00 * ldp w9, w10, [sp, #4]!
# CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [sp, #4]! # CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [sp, #4]!
# CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [x2, #-256]! # CHECK-NEXT: 2 5 3.00 * ldpsw x9, x10, [x2, #-256]!
# CHECK-NEXT: 2 5 3.00 * ldpsw x20, x30, [sp, #252]! # CHECK-NEXT: 2 5 3.00 * ldpsw x20, x30, [sp, #252]!
# CHECK-NEXT: 2 5 3.00 * ldp x21, x29, [x2, #504]! # CHECK-NEXT: 2 5 3.00 * ldp x21, x29, [x2, #504]!
# CHECK-NEXT: 2 5 3.00 * ldp x22, x23, [x3, #-512]! # CHECK-NEXT: 2 5 3.00 * ldp x22, x23, [x3, #-512]!
# CHECK-NEXT: 2 5 3.00 * ldp x24, x25, [x4, #8]! # CHECK-NEXT: 2 5 3.00 * ldp x24, x25, [x4, #8]!
# CHECK-NEXT: 2 5 3.00 * ldp s29, s28, [sp, #252]! # CHECK-NEXT: 2 5 3.00 * ldp s29, s28, [sp, #252]!
# CHECK-NEXT: 2 4 1.00 * stp s27, s26, [sp, #-256]! # CHECK-NEXT: 2 1 1.00 * stp s27, s26, [sp, #-256]!
# CHECK-NEXT: 2 5 3.00 * ldp s1, s2, [x3, #44]! # CHECK-NEXT: 2 5 3.00 * ldp s1, s2, [x3, #44]!
# CHECK-NEXT: 2 4 1.00 * stp d3, d5, [x9, #504]! # CHECK-NEXT: 2 1 1.00 * stp d3, d5, [x9, #504]!
# CHECK-NEXT: 2 4 1.00 * stp d7, d11, [x10, #-512]! # CHECK-NEXT: 2 1 1.00 * stp d7, d11, [x10, #-512]!
# CHECK-NEXT: 2 5 3.00 * ldp d2, d3, [x30, #-8]! # CHECK-NEXT: 2 5 3.00 * ldp d2, d3, [x30, #-8]!
# CHECK-NEXT: 2 4 1.00 * stp q3, q5, [sp, #0]! # CHECK-NEXT: 2 1 1.00 * stp q3, q5, [sp, #0]!
# CHECK-NEXT: 2 4 1.00 * stp q17, q19, [sp, #1008]! # CHECK-NEXT: 2 1 1.00 * stp q17, q19, [sp, #1008]!
# CHECK-NEXT: 2 5 3.00 * ldp q23, q29, [x1, #-1024]! # CHECK-NEXT: 2 5 3.00 * ldp q23, q29, [x1, #-1024]!
# CHECK-NEXT: 2 5 2.00 * ldnp w3, w5, [sp] # CHECK-NEXT: 2 5 2.00 * ldnp w3, w5, [sp]
# CHECK-NEXT: 1 4 1.00 * stnp wzr, w9, [sp, #252] # CHECK-NEXT: 1 1 1.00 * stnp wzr, w9, [sp, #252]
# CHECK-NEXT: 2 5 2.00 * ldnp w2, wzr, [sp, #-256] # CHECK-NEXT: 2 5 2.00 * ldnp w2, wzr, [sp, #-256]
# CHECK-NEXT: 2 5 2.00 * ldnp w9, w10, [sp, #4] # CHECK-NEXT: 2 5 2.00 * ldnp w9, w10, [sp, #4]
# CHECK-NEXT: 2 5 2.00 * ldnp x21, x29, [x2, #504] # CHECK-NEXT: 2 5 2.00 * ldnp x21, x29, [x2, #504]
# CHECK-NEXT: 2 5 2.00 * ldnp x22, x23, [x3, #-512] # CHECK-NEXT: 2 5 2.00 * ldnp x22, x23, [x3, #-512]
# CHECK-NEXT: 2 5 2.00 * ldnp x24, x25, [x4, #8] # CHECK-NEXT: 2 5 2.00 * ldnp x24, x25, [x4, #8]
# CHECK-NEXT: 2 5 2.00 * ldnp s29, s28, [sp, #252] # CHECK-NEXT: 2 5 2.00 * ldnp s29, s28, [sp, #252]
# CHECK-NEXT: 1 4 1.00 * stnp s27, s26, [sp, #-256] # CHECK-NEXT: 1 1 1.00 * stnp s27, s26, [sp, #-256]
# CHECK-NEXT: 2 5 2.00 * ldnp s1, s2, [x3, #44] # CHECK-NEXT: 2 5 2.00 * ldnp s1, s2, [x3, #44]
# CHECK-NEXT: 1 4 1.00 * stnp d3, d5, [x9, #504] # CHECK-NEXT: 1 1 1.00 * stnp d3, d5, [x9, #504]
# CHECK-NEXT: 1 4 1.00 * stnp d7, d11, [x10, #-512] # CHECK-NEXT: 1 1 1.00 * stnp d7, d11, [x10, #-512]
# CHECK-NEXT: 2 5 2.00 * ldnp d2, d3, [x30, #-8] # CHECK-NEXT: 2 5 2.00 * ldnp d2, d3, [x30, #-8]
# CHECK-NEXT: 1 4 1.00 * stnp q3, q5, [sp] # CHECK-NEXT: 1 1 1.00 * stnp q3, q5, [sp]
# CHECK-NEXT: 1 4 1.00 * stnp q17, q19, [sp, #1008] # CHECK-NEXT: 1 1 1.00 * stnp q17, q19, [sp, #1008]
# CHECK-NEXT: 2 5 2.00 * ldnp q23, q29, [x1, #-1024] # CHECK-NEXT: 2 5 2.00 * ldnp q23, q29, [x1, #-1024]
# CHECK-NEXT: 1 3 0.50 mov w3, #983055 # CHECK-NEXT: 1 3 0.50 mov w3, #983055
# CHECK-NEXT: 1 3 0.50 mov x10, #-6148914691236517206 # CHECK-NEXT: 1 3 0.50 mov x10, #-6148914691236517206
# CHECK-NEXT: 1 3 0.50 and w12, w23, w21 # CHECK-NEXT: 1 3 0.50 and w12, w23, w21
# CHECK-NEXT: 1 3 0.50 and w16, w15, w1, lsl #1 # CHECK-NEXT: 1 3 0.50 and w16, w15, w1, lsl #1
# CHECK-NEXT: 1 3 0.50 and w9, w4, w10, lsl #31 # CHECK-NEXT: 1 3 0.50 and w9, w4, w10, lsl #31
# CHECK-NEXT: 1 3 0.50 and w3, w30, w11 # CHECK-NEXT: 1 3 0.50 and w3, w30, w11
# CHECK-NEXT: 1 3 0.50 and x3, x5, x7, lsl #63 # CHECK-NEXT: 1 3 0.50 and x3, x5, x7, lsl #63
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llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s

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# CHECK: Dynamic Dispatch Stall Cycles: # CHECK: Dynamic Dispatch Stall Cycles:
# CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RAT - Register unavailable: 0
# CHECK-NEXT: RCU - Retire tokens unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0
# CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: SCHEDQ - Scheduler full: 0
# CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 1 (5.3%) # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 1 (5.3%)
# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles] # CHECK-NEXT: [# dispatched], [# cycles]
# CHECK-NEXT: 0, 11 (57.9%) # CHECK-NEXT: 0, 11 (57.9%)
# CHECK-NEXT: 1, 4 (21.1%) # CHECK-NEXT: 1, 4 (21.1%)
# CHECK-NEXT: 2, 4 (21.1%) # CHECK-NEXT: 2, 4 (21.1%)
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
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llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s

# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 -timeline --iterations=5 -noalias=false < %s | FileCheck %s # RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 -timeline --iterations=5 -noalias=false < %s | FileCheck %s
# PR50483: Execution of loads and stores should not overlap if flag -noalias is set to false. # PR50483: Execution of loads and stores should not overlap if flag -noalias is set to false.
str x1, [x4] str x1, [x4]
ldr x2, [x4] ldr x2, [x4]
# CHECK: Iterations: 5 # CHECK: Iterations: 5
# CHECK-NEXT: Instructions: 10 # CHECK-NEXT: Instructions: 10
# CHECK-NEXT: Total Cycles: 9 # CHECK-NEXT: Total Cycles: 8
# CHECK-NEXT: Total uOps: 10 # CHECK-NEXT: Total uOps: 10
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 1.11 # CHECK-NEXT: uOps Per Cycle: 1.25
# CHECK-NEXT: IPC: 1.11 # CHECK-NEXT: IPC: 1.25
# CHECK-NEXT: Block RThroughput: 1.0 # CHECK-NEXT: Block RThroughput: 1.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 1.00 * str x1, [x4] # CHECK-NEXT: 1 1 1.00 * str x1, [x4]
# CHECK-NEXT: 1 3 1.00 * ldr x2, [x4] # CHECK-NEXT: 1 3 1.00 * ldr x2, [x4]
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0.0] - CortexA55UnitALU # CHECK-NEXT: [0.0] - CortexA55UnitALU
# CHECK-NEXT: [0.1] - CortexA55UnitALU # CHECK-NEXT: [0.1] - CortexA55UnitALU
# CHECK-NEXT: [1] - CortexA55UnitB # CHECK-NEXT: [1] - CortexA55UnitB
# CHECK-NEXT: [2] - CortexA55UnitDiv # CHECK-NEXT: [2] - CortexA55UnitDiv
# CHECK-NEXT: [3.0] - CortexA55UnitFPALU # CHECK-NEXT: [3.0] - CortexA55UnitFPALU
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# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 # CHECK-NEXT: - - - - - - - - - 1.00 - 1.00
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:
# CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x4] # CHECK-NEXT: - - - - - - - - - - - 1.00 str x1, [x4]
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x4] # CHECK-NEXT: - - - - - - - - - 1.00 - - ldr x2, [x4]
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 012345678 # CHECK-NEXT: Index 01234567
# CHECK: [0,0] DeeeE. . str x1, [x4] # CHECK: [0,0] DE . . str x1, [x4]
# CHECK-NEXT: [0,1] .DeeE. . ldr x2, [x4] # CHECK-NEXT: [0,1] DeeE . . ldr x2, [x4]
# CHECK-NEXT: [1,0] .DeeeE . str x1, [x4] # CHECK-NEXT: [1,0] .DE . . str x1, [x4]
# CHECK-NEXT: [1,1] . DeeE . ldr x2, [x4] # CHECK-NEXT: [1,1] .DeeE. . ldr x2, [x4]
# CHECK-NEXT: [2,0] . DeeeE . str x1, [x4] # CHECK-NEXT: [2,0] . DE . . str x1, [x4]
# CHECK-NEXT: [2,1] . DeeE . ldr x2, [x4] # CHECK-NEXT: [2,1] . DeeE . ldr x2, [x4]
# CHECK-NEXT: [3,0] . DeeeE. str x1, [x4] # CHECK-NEXT: [3,0] . DE. . str x1, [x4]
# CHECK-NEXT: [3,1] . DeeE. ldr x2, [x4] # CHECK-NEXT: [3,1] . DeeE. ldr x2, [x4]
# CHECK-NEXT: [4,0] . DeeeE str x1, [x4] # CHECK-NEXT: [4,0] . DE . str x1, [x4]
# CHECK-NEXT: [4,1] . DeeE ldr x2, [x4] # CHECK-NEXT: [4,1] . DeeE ldr x2, [x4]
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 5 0.0 0.0 0.0 str x1, [x4] # CHECK-NEXT: 0. 5 0.0 0.0 0.0 str x1, [x4]
# CHECK-NEXT: 1. 5 0.0 0.0 0.0 ldr x2, [x4] # CHECK-NEXT: 1. 5 0.0 0.0 0.0 ldr x2, [x4]
# CHECK-NEXT: 5 0.0 0.0 0.0 <total> # CHECK-NEXT: 5 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s

Show All 35 Lines
# CHECK: Dynamic Dispatch Stall Cycles: # CHECK: Dynamic Dispatch Stall Cycles:
# CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RAT - Register unavailable: 0
# CHECK-NEXT: RCU - Retire tokens unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0
# CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: SCHEDQ - Scheduler full: 0
# CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: LQ - Load queue full: 0
# CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 7 (29.2%) # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 7 (29.2%)
# CHECK-NEXT: USH - Uncategorised Structural Hazard: 0
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
# CHECK-NEXT: [# dispatched], [# cycles] # CHECK-NEXT: [# dispatched], [# cycles]
# CHECK-NEXT: 0, 18 (75.0%) # CHECK-NEXT: 0, 18 (75.0%)
# CHECK-NEXT: 2, 6 (25.0%) # CHECK-NEXT: 2, 6 (25.0%)
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
# CHECK-NEXT: [# issued], [# cycles] # CHECK-NEXT: [# issued], [# cycles]
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