[SVE] Fixed cast<FixedVectorType> on scalable vector in SelectionDAGBuilder::getUniformBase

[sdesmalen]

llvm/test/CodeGen/AArch64/sve-masked-scatter.ll

76

nit: please rename it to something like masked_scatter_splat_constant_pointer to make it clear it is specifically testing a splat(constant) pointer.

89–92

The control-flow can be removed from this function.

96

can this be passed in as an argument, e.g. <vscale x 4 x i1> %pg

97

remove.

[DylanFleming-arm]

Renamed test function
Cleaned up control flow

[sdesmalen]

LGTM

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index,
   // Handle splat constant pointer.
   if (auto *C = dyn_cast<Constant>(Ptr)) {
     C = C->getSplatValue();
     if (!C)
       return false;
 
     Base = SDB->getValue(C);
 
-    unsigned NumElts = cast<FixedVectorType>(Ptr->getType())->getNumElements();
+    ElementCount NumElts = cast<VectorType>(Ptr->getType())->getElementCount();
     EVT VT = EVT::getVectorVT(*DAG.getContext(), TLI.getPointerTy(DL), NumElts);
     Index = DAG.getConstant(0, SDB->getCurSDLoc(), VT);
     IndexType = ISD::SIGNED_SCALED;
     Scale = DAG.getTargetConstant(1, SDB->getCurSDLoc(), TLI.getPointerTy(DL));
     return true;
   }
 
   const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);

llvm/test/CodeGen/AArch64/sve-masked-scatter.ll

 ; CHECK-LABEL: masked_scatter_nxv2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    st1d { z0.d }, p0, [z1.d]
 ; CHECK-NEXT:    ret
   call void @llvm.masked.scatter.nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x double*> %ptrs, i32 0, <vscale x 2 x i1> %masks)
   ret void
 }
 
+define i32 @masked_scatter_nxv4i32_nxvp0i32 () {
+; CHECK-LABEL: masked_scatter_nxv4i32_nxvp0i32:
+; CHECK:       // %bb.0: // %vector.ph
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    mov z0.d, #0 // =0x0
+; CHECK-NEXT:  .LBB8_1: // %vector.body
+; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    pfalse p1.b
+; CHECK-NEXT:    zip1 p2.s, p0.s, p1.s
+; CHECK-NEXT:    zip2 p1.s, p0.s, p1.s
+; CHECK-NEXT:    st1w { z0.d }, p2, [x8, z0.d, lsl #2]
+; CHECK-NEXT:    st1w { z0.d }, p1, [x8, z0.d, lsl #2]
+; CHECK-NEXT:    b .LBB8_1
+vector.ph:
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  call void @llvm.masked.scatter.nxv4i32.nxv4p0i32(<vscale x 4 x i32> undef,
+    <vscale x 4 x i32*> shufflevector (<vscale x 4 x i32*> insertelement (<vscale x 4 x i32*> poison, i32* undef, i32 0), <vscale x 4 x i32*> poison, <vscale x 4 x i32> zeroinitializer),
+    i32 4,
+    <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> undef, i1 true, i32 0), <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer))
+  br label %vector.body
+}
+
 declare void @llvm.masked.scatter.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half*>, i32, <vscale x 2 x i1>)
 declare void @llvm.masked.scatter.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x bfloat*>, i32, <vscale x 2 x i1>)
 declare void @llvm.masked.scatter.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float*>, i32, <vscale x 2 x i1>)
 declare void @llvm.masked.scatter.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double*>, i32, <vscale x 2 x i1>)
 declare void @llvm.masked.scatter.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16*>, i32, <vscale x 2 x i1>)
 declare void @llvm.masked.scatter.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32*>, i32, <vscale x 2 x i1>)
 declare void @llvm.masked.scatter.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64*>, i32, <vscale x 2 x i1>)
 declare void @llvm.masked.scatter.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8*>, i32, <vscale x 2 x i1>)
+declare void @llvm.masked.scatter.nxv4i32.nxv4p0i32(<vscale x 4 x i32>, <vscale x 4 x i32*>, i32, <vscale x 4 x i1>)
 attributes #0 = { "target-features"="+sve,+bf16" }