[AArch64][X86] Allow 64-bit label differences lower to IMAGE_REL_*_REL32

[MaskRay]

Summary

IMAGE_REL_ARM64_REL64/IMAGE_REL_AMD64_REL64 do not exist and .quad a - . is
currently not representable.

For instrumentation, .quad a - . is useful representing a cross-section
reference in a metadata section, to allow ELF medium/large code models. The COFF
limitation makes such generic instrumentations inconvenient. I plan to make a
PGO/coverage metadata section field relative in D104556.

[mstorsjo]

Looks ok to me. A PE-COFF image is limited to 32 bits in range anyway, so as long as the target symbol doesn't turn out to be from outside of the image (with mingw automatic dllimport), a 32 bit difference should be enough in all cases.

[MaskRay]

I think the main problem is when the value is negative. How to represent it?

For D104556 compiler-rt/lib/profile/InstrProfilingMerge.c I just truncate Header->CountersDelta to 32-bit for COFF.

[rnk]

I was going to say, I wonder if it would be better to find a way to put the extension in IR instead of in the assembler. For example, maybe the IR could look like (pseudo-IR):
zext i64 (trunc i32 (sub i64 (ptrtoint i64 @label2)), (ptrtoint i64 @label1))))
So that would slot into the constant inititalizer, and the backend would know to emit that pattern as:

.long 0
.long label2 - label1

Now that I've written it out, it seems worse and more complex. Let's go with .quad I guess.

[MaskRay]

In D104564#2831690, @rnk wrote:

I was going to say, I wonder if it would be better to find a way to put the extension in IR instead of in the assembler. For example, maybe the IR could look like (pseudo-IR):
zext i64 (trunc i32 (sub i64 (ptrtoint i64 @label2)), (ptrtoint i64 @label1))))
So that would slot into the constant inititalizer, and the backend would know to emit that pattern as:

.long 0
.long label2 - label1

Now that I've written it out, it seems worse and more complex. Let's go with .quad I guess.

Thanks!

The IR approach would mean every new relative metadata usage needs to be different for COFF and non-COFF.
Label differences are probably not that common today but may get more uses in the future, e.g. https://lists.llvm.org/pipermail/llvm-dev/2021-June/151198.html

llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp

 
 } // end anonymous namespace
 
 unsigned AArch64WinCOFFObjectWriter::getRelocType(
     MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup,
     bool IsCrossSection, const MCAsmBackend &MAB) const {
   unsigned FixupKind = Fixup.getKind();
   if (IsCrossSection) {
-    if (FixupKind != FK_Data_4) {
+    // IMAGE_REL_ARM64_REL64 does not exist. We treat FK_Data_8 as FK_PCRel_4 so
+    // that .xword a-b can lower to IMAGE_REL_ARM64_REL32. This allows generic
+    // instrumentation to not bother with the COFF limitation.
+    if (FixupKind != FK_Data_4 && FixupKind != FK_Data_8) {
       Ctx.reportError(Fixup.getLoc(), "Cannot represent this expression");
       return COFF::IMAGE_REL_ARM64_ADDR32;
     }
     FixupKind = FK_PCRel_4;
   }
 
   auto Modifier = Target.isAbsolute() ? MCSymbolRefExpr::VK_None
                                       : Target.getSymA()->getKind();

llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp

X86WinCOFFObjectWriter::X86WinCOFFObjectWriter(bool Is64Bit)
     : MCWinCOFFObjectTargetWriter(Is64Bit ? COFF::IMAGE_FILE_MACHINE_AMD64
                                           : COFF::IMAGE_FILE_MACHINE_I386) {}
 
 unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
                                               const MCValue &Target,
                                               const MCFixup &Fixup,
                                               bool IsCrossSection,
                                               const MCAsmBackend &MAB) const {
+  const bool Is64Bit = getMachine() == COFF::IMAGE_FILE_MACHINE_AMD64;
   unsigned FixupKind = Fixup.getKind();
   if (IsCrossSection) {
-    if (FixupKind != FK_Data_4 && FixupKind != llvm::X86::reloc_signed_4byte) {
+    // IMAGE_REL_AMD64_REL64 does not exist. We treat FK_Data_8 as FK_PCRel_4 so
+    // that .quad a-b can lower to IMAGE_REL_AMD64_REL32. This allows generic
+    // instrumentation to not bother with the COFF limitation.
+    if (FixupKind == FK_Data_4 || FixupKind == llvm::X86::reloc_signed_4byte ||
+        (FixupKind == FK_Data_8 && Is64Bit)) {
+      FixupKind = FK_PCRel_4;
+    } else {
       Ctx.reportError(Fixup.getLoc(), "Cannot represent this expression");
       return COFF::IMAGE_REL_AMD64_ADDR32;
     }
-    FixupKind = FK_PCRel_4;
   }
 
   MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ?
     MCSymbolRefExpr::VK_None : Target.getSymA()->getKind();
 
-  if (getMachine() == COFF::IMAGE_FILE_MACHINE_AMD64) {
+  if (Is64Bit) {
     switch (FixupKind) {
     case FK_PCRel_4:
     case X86::reloc_riprel_4byte:
     case X86::reloc_riprel_4byte_movq_load:
     case X86::reloc_riprel_4byte_relax:
     case X86::reloc_riprel_4byte_relax_rex:
     case X86::reloc_branch_4byte_pcrel:
       return COFF::IMAGE_REL_AMD64_REL32;

llvm/test/MC/AArch64/coff-relocations.s

 // IMAGE_REL_ARM64_BRANCH14
 tbz x0, #0, target
 
 .section .rdata, "dr"
 .Ltable:
 .word .Linfo_bar - .Ltable
 .word .Linfo_foo - .Ltable
 
+// As an extension, we allow 64-bit label differences. They lower to
+// IMAGE_REL_ARM64_REL32 because IMAGE_REL_ARM64_REL64 does not exist.
+.xword .Linfo_foo - .Ltable
+
 // CHECK: Format: COFF-ARM64
 // CHECK: Arch: aarch64
 // CHECK: AddressSize: 64bit
 // CHECK: Relocations [
 // CHECK:   Section (1) .text {
 // CHECK: 0x4 IMAGE_REL_ARM64_ADDR32 foo
 // CHECK: 0x8 IMAGE_REL_ARM64_ADDR32NB func
 // CHECK: 0xC IMAGE_REL_ARM64_ADDR64 arr

 // CHECK: 0x48 IMAGE_REL_ARM64_SECREL_LOW12L foo
 // CHECK: 0x4C IMAGE_REL_ARM64_REL21 foo
 // CHECK: 0x50 IMAGE_REL_ARM64_BRANCH19 target
 // CHECK: 0x54 IMAGE_REL_ARM64_BRANCH14 target
 // CHECK:   }
 // CHECK:   Section (4) .rdata {
 // CHECK: 0x0 IMAGE_REL_ARM64_REL32 .text
 // CHECK: 0x4 IMAGE_REL_ARM64_REL32 .text
+// CHECK: 0x8 IMAGE_REL_ARM64_REL32 .text
 // CHECK:   }
 // CHECK: ]
 
 // DISASM: 30:       20 1a 09 b0     adrp    x0, 0x12345000
 // DISASM: 34:       00 14 0d 91     add     x0, x0, #837
 // DISASM: 38:       00 14 4d 39     ldrb    w0, [x0, #837]
 // DISASM: 3c:       00 a4 41 f9     ldr     x0, [x0, #840]
 // DISASM: 40:       00 00 00 91     add     x0, x0, #0
 // DISASM: 44:       00 00 40 91     add     x0, x0, #0, lsl #12
 // DISASM: 48:       00 00 40 f9     ldr     x0, [x0]
 // DISASM: 4c:       20 1a 09 30     adr     x0, #74565
 
 // DATA: Contents of section .rdata:
 // DATA-NEXT:  0000 30000000 08000000

llvm/test/MC/COFF/cross-section-relative-err.s

+// RUN: not llvm-mc -filetype=obj -triple i686-pc-win32 %s -o /dev/null 2>&1 | FileCheck %s --check-prefixes=CHECK,I686
 // RUN: not llvm-mc -filetype=obj -triple x86_64-pc-win32 %s -o /dev/null 2>&1 | FileCheck %s
 
 
 // CHECK: [[@LINE+1]]:{{[0-9]+}}: error: Cannot represent this expression
         .byte foo - .
 
 // CHECK: [[@LINE+1]]:{{[0-9]+}}: error: Cannot represent this expression
         .short foo - .
 
-// CHECK: [[@LINE+1]]:{{[0-9]+}}: error: Cannot represent this expression
+// I686: [[@LINE+1]]:{{[0-9]+}}: error: Cannot represent this expression
         .quad foo - .
-

llvm/test/MC/COFF/cross-section-relative.s

t6:
   .ascii  "\001\002"
   .zero 6
   .quad 256                     # 0x100
   .long g3-(t6+16)
   .zero 4
 
 .long foobar - .
 
+// As an extension, we allow 64-bit label differences. They lower to
+// IMAGE_REL_AMD64_REL32 because IMAGE_REL_AMD64_REL64 does not exist.
+.quad foobar - .
+
 // READOBJ:       Section {
 // READOBJ:         Number:
 // READOBJ:         Name: .fix (2E 66 69 78 00 00 00 00)
 // READOBJ-NEXT:    VirtualSize: 0x0
 // READOBJ-NEXT:    VirtualAddress: 0x0
 // READOBJ-NEXT:    RawDataSize:
 // READOBJ-NEXT:    PointerToRawData: 0xEC
 // READOBJ-NEXT:    PointerToRelocations:
 // READOBJ-NEXT:    PointerToLineNumbers: 0x0
 // READOBJ-NEXT:    RelocationCount:
 // READOBJ-NEXT:    LineNumberCount: 0
 // READOBJ-NEXT:    Characteristics [ (0xC0500040)
 // READOBJ-NEXT:      IMAGE_SCN_ALIGN_16BYTES (0x500000)
 // READOBJ-NEXT:      IMAGE_SCN_CNT_INITIALIZED_DATA (0x40)
 // READOBJ-NEXT:      IMAGE_SCN_MEM_READ (0x40000000)
 // READOBJ-NEXT:      IMAGE_SCN_MEM_WRITE (0x80000000)
 // READOBJ-NEXT:    ]
 // READOBJ-NEXT:    SectionData (
 // READOBJ-NEXT:      0000: 04000000 00000000 00000000 00000000  |
 // READOBJ-NEXT:      0010: 01020000 00000000 00010000 00000000  |
-// READOBJ-NEXT:      0020: 04000000 00000000 04000000           |
+// READOBJ-NEXT:      0020: 04000000 00000000 04000000 04000000  |
+// READOBJ-NEXT:      0030: 00000000 |
 // READOBJ-NEXT:    )
 // READOBJ-NEXT:  }
 // READOBJ-NEXT:  ]
 // READOBJ-NEXT:  Relocations [
 // READOBJ-NEXT:  Section (5) .fix {
 // READOBJ-NEXT:    Relocation {
 // READOBJ-NEXT:      Offset: 0x0
 // READOBJ-NEXT:      Type: IMAGE_REL_AMD64_REL32 (4)

 // READOBJ-NEXT:      SymbolIndex: 12
 // READOBJ-NEXT:    }
 // READOBJ-NEXT:    Relocation {
 // READOBJ-NEXT:      Offset: 0x28
 // READOBJ-NEXT:      Type: IMAGE_REL_AMD64_REL32 (4)
 // READOBJ-NEXT:      Symbol: foobar
 // READOBJ-NEXT:      SymbolIndex: 20
 // READOBJ-NEXT:    }
+// READOBJ-NEXT:    Relocation {
+// READOBJ-NEXT:      Offset: 0x2C
+// READOBJ-NEXT:      Type: IMAGE_REL_AMD64_REL32 (4)
+// READOBJ-NEXT:      Symbol: foobar
+// READOBJ-NEXT:      SymbolIndex: 20
+// READOBJ-NEXT:    }
 // READOBJ-NEXT:  }
 // READOBJ-NEXT:]