[M68k][GloballSel] Formal arguments lowering in IRTranslator

[sushmaunnibhavi]

Summary

Implementation of formal arguments lowering in the IRTranslator for the M68k backend

[gandhi21299]

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

13

Should add checks for the parameters

[gandhi21299]

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

177

add more tests with parameters of various types: aggregate types, non-aggregate types, combination of those

[gandhi21299]

Title of this patch is not clear enough, perhaps something like [M68k] [GlobalISel] Formal arguments lowering in IRTranslator.

Also, I just realized this is only for i32 values so far. I think it should be easily extensible across any primitive type. Thoughts @myhsu ?

[myhsu]

In D104542#2829342, @gandhi21299 wrote:

Title of this patch is not clear enough, perhaps something like [M68k] [GlobalISel] Formal arguments lowering in IRTranslator.

Also, I just realized this is only for i32 values so far. I think it should be easily extensible across any primitive type. Thoughts @myhsu ?

Agree, please try to augment this patch into generic integer type

[myhsu]

llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp

82

I think you're trying to say either "Value should be assigned to reg" or "Value was not assigned to reg?" right?

97

You can just put "unimeplemented" here. Since the stack trace will tell you which function triggers this unreachable statement

104

ditto

llvm/lib/Target/M68k/GlSel/M68kCallLowering.h

70

(nit) please use struct instead and remove "public" in the following line

llvm/lib/Target/M68k/M68kISelLowering.h

174

The function name is a little confusing, maybe something like "getCCAssignGnForCall"?

[sushmaunnibhavi]

Updated patch according to @myhsu and @gandhi21299 comments

[gandhi21299]

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

40

Shorter variable name instead of G_FRAME_INDEX, replaces uses and should not be reused for a different register

[sushmaunnibhavi]

Added tests for pointer, array and struct

[gandhi21299]

LGTM, please wait for approval from at least one more reviewer before we merge this patch in. Great work @sushmaunnibhavi !

[sushmaunnibhavi]

In D104542#2839057, @gandhi21299 wrote:

LGTM, please wait for approval from at least one more reviewer before we merge this patch in. Great work @sushmaunnibhavi !

Thanks for reviewing the patch @gandhi21299. @myhsu does the patch look good?

[myhsu]

I'm curious if the test pass on your side. When I applied this patch on tip-of-tree, the newly-added test case triggered unreachable statement on line 87 of lib/Target/M68k/GlSel/M68kCallLowering.cpp (i.e. M68kIncomingValueHandler::getStackAddress was called).
Can you double check if this patch works on tip-of-tree? (of course please make sure you have assertion enabled in your build)

llvm/lib/Target/M68k/GlSel/M68kCallLowering.h

68

please use struct instead and remove "public" in this line as well as the empty line above

[sushmaunnibhavi]

In D104542#2840195, @myhsu wrote:

I'm curious if the test pass on your side. When I applied this patch on tip-of-tree, the newly-added test case triggered unreachable statement on line 87 of lib/Target/M68k/GlSel/M68kCallLowering.cpp (i.e. M68kIncomingValueHandler::getStackAddress was called).
Can you double check if this patch works on tip-of-tree? (of course please make sure you have assertion enabled in your build)

I did build my patch again but I don't get any errors.

[myhsu]

In D104542#2842366, @sushmaunnibhavi wrote:

In D104542#2840195, @myhsu wrote:

I'm curious if the test pass on your side. When I applied this patch on tip-of-tree, the newly-added test case triggered unreachable statement on line 87 of lib/Target/M68k/GlSel/M68kCallLowering.cpp (i.e. M68kIncomingValueHandler::getStackAddress was called).
Can you double check if this patch works on tip-of-tree? (of course please make sure you have assertion enabled in your build)

I did build my patch again but I don't get any errors.

no, I didn't say it fail the build, I said it failed the test after this patch was applied.
In other words, ninja check-llvm-codegen-m68k fails (or replace ninja with whatever build system you're using). Can you verify whether that command fails on your side?

[myhsu]

Also, since M68k's calling convention uses stack to pass incoming parameters, I'm not surprised M68kIncomingValueHandler::getStackAddress was called by GlobalISel to generate proper MIR instructions.
I suggest you to use i386 (a.k.a 32-bit X86) as a reference to see how thing works there and how they implement IncomingValueHandler. Since i386 is also using stack to pass incoming parameters.

[sushmaunnibhavi]

In D104542#2842715, @myhsu wrote:

In D104542#2842366, @sushmaunnibhavi wrote:

In D104542#2840195, @myhsu wrote:

I'm curious if the test pass on your side. When I applied this patch on tip-of-tree, the newly-added test case triggered unreachable statement on line 87 of lib/Target/M68k/GlSel/M68kCallLowering.cpp (i.e. M68kIncomingValueHandler::getStackAddress was called).
Can you double check if this patch works on tip-of-tree? (of course please make sure you have assertion enabled in your build)

I did build my patch again but I don't get any errors.

no, I didn't say it fail the build, I said it failed the test after this patch was applied.
In other words, ninja check-llvm-codegen-m68k fails (or replace ninja with whatever build system you're using). Can you verify whether that command fails on your side?

Yes I did this too and the tests didn't fail.

[sushmaunnibhavi]

In D104542#2842720, @myhsu wrote:

Also, since M68k's calling convention uses stack to pass incoming parameters, I'm not surprised M68kIncomingValueHandler::getStackAddress was called by GlobalISel to generate proper MIR instructions.
I suggest you to use i386 (a.k.a 32-bit X86) as a reference to see how thing works there and how they implement IncomingValueHandler. Since i386 is also using stack to pass incoming parameters.

I will look into this. Thanks!

[myhsu]

In D104542#2842737, @sushmaunnibhavi wrote:

In D104542#2842715, @myhsu wrote:

In D104542#2842366, @sushmaunnibhavi wrote:

In D104542#2840195, @myhsu wrote:

I'm curious if the test pass on your side. When I applied this patch on tip-of-tree, the newly-added test case triggered unreachable statement on line 87 of lib/Target/M68k/GlSel/M68kCallLowering.cpp (i.e. M68kIncomingValueHandler::getStackAddress was called).
Can you double check if this patch works on tip-of-tree? (of course please make sure you have assertion enabled in your build)

I did build my patch again but I don't get any errors.

no, I didn't say it fail the build, I said it failed the test after this patch was applied.
In other words, ninja check-llvm-codegen-m68k fails (or replace ninja with whatever build system you're using). Can you verify whether that command fails on your side?

Yes I did this too and the tests didn't fail.

Hmmm...alright, let's see how the buildbot will say

llvm/lib/Target/M68k/GlSel/M68kCallLowering.h

68

still outstanding

[sushmaunnibhavi]

Changed class to struct in M68CallLowering.h file

[myhsu]

LGTM

[myhsu]

Do you want me to commit on your behalf?

[sushmaunnibhavi]

In D104542#2843047, @myhsu wrote:

Do you want me to commit on your behalf?

Yes, because I don't have commit access.

[myhsu]

I'm afraid the build fails: https://lab.llvm.org/staging/#/builders/180/builds/132
More specifically, here is the error details on the test case added by this patch: https://lab.llvm.org/staging/#/builders/180/builds/132/steps/5/logs/FAIL__LLVM__irtranslator-ret_ll
Which is identical to the assertion failure I pointed out earlier in this review.

@sushmaunnibhavi I'm afraid I need to temporarily revert the commit (since it is the only test case relates to the patch, it doesn't make sense to only mark the test XFAIL)

[myhsu]

Here are my guesses of why you couldn't reproduce the failure:

1. Your local changes are not sync with the patch presented here.
2. You didn't turn on assertion. Please open <your build folder>/CMakeCache.txt. If the CMAKE_BUILD_TYPE variable is "Debug" then you're fine, if it's something else, make sure LLVM_ENABLE_ASSERTIONS is ON (in case you don't know, you can directly change the variable value in that file and CMake will reconfigure on the next build).

Regarding the root cause of the crash, M68k's calling convention relies on pushing parameters to the stack, so only implementing register assignment is not enough. As I suggested before, i386's implementation of GlobalISel might be a good reference.

Last but not the least, commits got reverted all the time in LLVM so please don't mind :-) You're almost there and I definitely appreciate your contribution here!

[sushmaunnibhavi]

In D104542#2843380, @myhsu wrote:

Here are my guesses of why you couldn't reproduce the failure:

1. Your local changes are not sync with the patch presented here.
2. You didn't turn on assertion. Please open <your build folder>/CMakeCache.txt. If the CMAKE_BUILD_TYPE variable is "Debug" then you're fine, if it's something else, make sure LLVM_ENABLE_ASSERTIONS is ON (in case you don't know, you can directly change the variable value in that file and CMake will reconfigure on the next build).

Regarding the root cause of the crash, M68k's calling convention relies on pushing parameters to the stack, so only implementing register assignment is not enough. As I suggested before, i386's implementation of GlobalISel might be a good reference.

Last but not the least, commits got reverted all the time in LLVM so please don't mind :-) You're almost there and I definitely appreciate your contribution here!

Thanks! I will look into this and fix it.

[sushmaunnibhavi]

Added implementation for M68kIncomingValueHandler::getStackAddress.

[sushmaunnibhavi]

@myhsu can you check the patch now? All test cases pass on my side.

[myhsu]

llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp

81

Is there any specific reason to extract these code into a separate lambda if there is only one callsite

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

16

Git told me that there are trailing white spaces after every G_FRAME_INDEX line in this file, please remove them

[myhsu]

Basically looks good to me now. Please address the minor issue I point out in the inlined comments.

[sushmaunnibhavi]

llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp

81

Yeah, this isn't necessary.

[sushmaunnibhavi]

Removed trailing whitespaces after G_FRAME_INDEX

[myhsu]

LGTM Thank you!
I'll commit it later today

llvm/lib/Target/M68k/GlSel/M68kCallLowering.h

bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
                             ArrayRef<ArrayRef<Register>> VRegs,
                             FunctionLoweringInfo &FLI) const override;
 
   bool lowerCall(MachineIRBuilder &MIRBuilder,
                  CallLoweringInfo &Info) const override;
 
   bool enableBigEndian() const override;
 };
+struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler {
+  M68kIncomingValueHandler(MachineIRBuilder &MIRBuilder,
+                           MachineRegisterInfo &MRI)
+      : CallLowering::IncomingValueHandler(MIRBuilder, MRI) {}
+
+  uint64_t StackUsed;
+
+private:
+  void assignValueToReg(Register ValVReg, Register PhysReg,
+                        CCValAssign &VA) override;
+
+  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
+                            MachinePointerInfo &MPO, CCValAssign &VA) override;
+
+  Register getStackAddress(uint64_t Size, int64_t Offset,
+                           MachinePointerInfo &MPO,
+                           ISD::ArgFlagsTy Flags) override;
+};
+
+struct FormalArgHandler : public M68kIncomingValueHandler {
+  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
+      : M68kIncomingValueHandler(MIRBuilder, MRI) {}
+};
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_M68K_GLSEL_M68KCALLLOWERING_H

llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp

 /// This file implements the lowering of LLVM calls to machine code calls for
 /// GlobalISel.
 //
 //===----------------------------------------------------------------------===//
 
 #include "M68kCallLowering.h"
 #include "M68kISelLowering.h"
 #include "M68kInstrInfo.h"
+#include "M68kSubtarget.h"
+#include "M68kTargetMachine.h"
+#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/TargetCallingConv.h"
+
 using namespace llvm;
 
 M68kCallLowering::M68kCallLowering(const M68kTargetLowering &TLI)
     : CallLowering(&TLI) {}
-
 bool M68kCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                    const Value *Val, ArrayRef<Register> VRegs,
                                    FunctionLoweringInfo &FLI,
                                    Register SwiftErrorVReg) const {
 
   if (Val)
     return false;
   MIRBuilder.buildInstr(M68k::RTS);
   return true;
 }
 
 bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
                                             const Function &F,
                                             ArrayRef<ArrayRef<Register>> VRegs,
                                             FunctionLoweringInfo &FLI) const {
+  MachineFunction &MF = MIRBuilder.getMF();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  const auto &DL = F.getParent()->getDataLayout();
+  auto &TLI = *getTLI<M68kTargetLowering>();
+
+  SmallVector<ArgInfo, 8> SplitArgs;
+  unsigned I = 0;
+  for (const auto &Arg : F.args()) {
+    ArgInfo OrigArg{VRegs[I], Arg.getType()};
+    setArgFlags(OrigArg, I + AttributeList::FirstArgIndex, DL, F);
+    splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
+    ++I;
+  }
 
-  if (F.arg_empty())
-    return true;
+  CCAssignFn *AssignFn =
+      TLI.getCCAssignFnForCall(F.getCallingConv(), false, F.isVarArg());
+  IncomingValueAssigner ArgAssigner(AssignFn);
+  FormalArgHandler ArgHandler(MIRBuilder, MRI);
+  return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
+                                       MIRBuilder, F.getCallingConv(),
+                                       F.isVarArg());
+}
 
-  return false;
+void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
+                                                Register PhysReg,
+                                                CCValAssign &VA) {
+  MIRBuilder.getMRI()->addLiveIn(PhysReg);
+  MIRBuilder.getMBB().addLiveIn(PhysReg);
+  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
+}
+
+void M68kIncomingValueHandler::assignValueToAddress(Register ValVReg,
+                                                    Register Addr,
+                                                    uint64_t Size,
+                                                    MachinePointerInfo &MPO,
+                                                    CCValAssign &VA) {
+  llvm_unreachable("unimeplemented");
+}
+
+Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
+                                                   int64_t Offset,
+                                                   MachinePointerInfo &MPO,
+                                                   ISD::ArgFlagsTy Flags) {
+  llvm_unreachable("unimeplemented");
 }
 
 bool M68kCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
                                  CallLoweringInfo &Info) const {
   return false;
 }
 
 bool M68kCallLowering::enableBigEndian() const { return true; }

llvm/lib/Target/M68k/M68kISelLowering.h

public:
   void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                     std::vector<SDValue> &Ops,
                                     SelectionDAG &DAG) const override;
 
   MachineBasicBlock *
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *MBB) const override;
 
+  CCAssignFn *getCCAssignFnForCall(CallingConv::ID CC, bool Return,
+                                   bool IsVarArg) const;
+
 private:
   unsigned GetAlignedArgumentStackSize(unsigned StackSize,
                                        SelectionDAG &DAG) const;
 
   SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
 
   /// Emit a load of return address if tail call
   /// optimization is performed and it is required.

llvm/lib/Target/M68k/M68kISelLowering.cpp

const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case M68kISD::WrapperPC:
     return "M68kISD::WrapperPC";
   case M68kISD::SEG_ALLOCA:
     return "M68kISD::SEG_ALLOCA";
   default:
     return NULL;
   }
 }
+
+CCAssignFn *M68kTargetLowering::getCCAssignFnForCall(CallingConv::ID CC,
+                                                     bool Return,
+                                                     bool IsVarArg) const {
+  return CC_M68k_C;
+}

llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

 ; RUN: llc -mtriple=m68k -global-isel -stop-after=irtranslator < %s | FileCheck %s
 
+%struct.A = type { i8, float, i32, i32, i32 }
+
 ; CHECK: name: noArgRetVoid
 ; CHECK: RTS
 define void @noArgRetVoid() {
   ret void
 }
+
+define void @test_arg_lowering1(i8 %x, i8 %y) {
+  ; CHECK-LABEL: name: test_arg_lowering1
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   [[G_TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
+  ; CHECK:   [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
+  ; CHECK:   [[G_TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering2(i16 %x, i16 %y) {
+  ; CHECK-LABEL: name: test_arg_lowering2
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   [[G_TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD1]](s32)
+  ; CHECK:   [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
+  ; CHECK:   [[G_TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD2]](s32)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering3(i32 %x, i32 %y) {
+  ; CHECK-LABEL: name: test_arg_lowering3
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   {{%.*}} G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   {{%.*}} G_LOAD [[G_F_I2]](p0)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering_vector(<5 x i8> %x) {
+  ; CHECK-LABEL: name: test_arg_lowering_vector
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
+  ; CHECK:   [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
+  ; CHECK:   [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
+  ; CHECK:   [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
+  ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[G_LOAD1]](s32), [[G_LOAD2]](s32), [[G_LOAD3]](s32), [[G_LOAD4]](s32), [[G_LOAD5]](s32)
+  ; CHECK:   [[G_TRUNC:%[0-9]+]]:_(<5 x s8>) = G_TRUNC [[BUILD_VECTOR]](<5 x s32>)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering_array([5 x i8] %x) {
+  ; CHECK-LABEL: name: test_arg_lowering_array
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   [[G_TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
+  ; CHECK:   [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
+  ; CHECK:   [[G_TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
+  ; CHECK:   [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
+  ; CHECK:   [[G_TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD3]](s32)
+  ; CHECK:   [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
+  ; CHECK:   [[G_TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD4]](s32)
+  ; CHECK:   [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
+  ; CHECK:   [[G_TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD5]](s32)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering_double(double %x) {
+  ; CHECK-LABEL: name: test_arg_lowering_double
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
+  ; CHECK:   [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD1]](s32), [[G_LOAD2]](s32)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering_float(float %x) {
+  ; CHECK-LABEL: name: test_arg_lowering_float
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering_multiple(i1 %a, i8 %b, i16 %c, i32 %d, i64 %e, i128 %f){
+  ; CHECK-LABEL: name: test_arg_lowering_multiple
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   [[G_TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[G_LOAD1]](s32)
+  ; CHECK:   [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
+  ; CHECK:   [[G_TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD2]](s32)
+  ; CHECK:   [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
+  ; CHECK:   [[G_TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[G_LOAD3]](s32)
+  ; CHECK:   [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
+  ; CHECK:   [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
+  ; CHECK:   [[G_F_I6:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I6]](p0)
+  ; CHECK:   [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD5]](s32), [[G_LOAD6]](s32)
+  ; CHECK:   [[G_F_I7:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I7]](p0)
+  ; CHECK:   [[G_F_I8:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I8]](p0)
+  ; CHECK:   [[G_F_I9:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I9]](p0)
+  ; CHECK:   [[G_F_I10:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I10]](p0)
+  ; CHECK:   [[G_MERGE_VAL:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[G_LOAD7]](s32), [[G_LOAD8]](s32), [[G_LOAD9]](s32), [[G_LOAD10]](s32)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering_ptr(i32* %x) {
+  ; CHECK-LABEL: name: test_arg_lowering_ptr
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering_float_ptr(float* %x) {
+  ; CHECK-LABEL: name: test_arg_lowering_float_ptr
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   RTS
+  ret void
+}
+
+define void @test_arg_lowering_struct(%struct.A %a) #0 {
+  ; CHECK-LABEL: name: test_arg_lowering_struct
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   [[G_TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[G_LOAD1]](s32)
+  ; CHECK:   [[G_F_I2:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
+  ; CHECK:   [[G_F_I3:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I3]](p0)
+  ; CHECK:   [[G_F_I4:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I4]](p0)
+  ; CHECK:   [[G_F_I5:%[0-9]+]]:_(p0) = G_FRAME_INDEX 
+  ; CHECK:   [[G_LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I5]](p0)
+  ; CHECK:   RTS
+  ret void
+}