[InstrRef][AArch64][4/4] Save variable locations over pseudo-inst expansion

[jmorse]

Summary

Various forms of aarch64 instructions are finalised in this pass, and involve the replacement of one instruction with another. That requires a call to substituteDebugValuesForInst to patch up the variable location information: deleted instructions need to be accounted for, so that instruction-referencing variable locations can find the new value.

The test covers the major elements that get expanded; however I haven't written a test covering each form of pcrel 'add' instruction to ensure it gets salvaged; is it acceptable to skip that?

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

case AArch64::MOVKXi: {
                 RenamableState)
         .addReg(DstReg)
         .addImm(I->Op1)
         .addImm(I->Op2));
       } break;
     }
   }
   transferImpOps(MI, MIBS.front(), MIBS.back());
+  // Final instr finishes the value definition for debug-info.
+  auto &MF = *MI.getMF();
+  MF.substituteDebugValuesForInst(MI, *MIBS.back(), 1);
   MI.eraseFromParent();
   return true;
 }
 
 bool AArch64ExpandPseudo::expandCMP_SWAP(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned LdarOp,
     unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg,
     MachineBasicBlock::iterator &NextMBBI) {
bool AArch64ExpandPseudo::expandCMP_SWAP(
   // .Lloadcmp:
   //     mov wStatus, 0
   //     ldaxr xDest, [xAddr]
   //     cmp xDest, xDesired
   //     b.ne .Ldone
   if (!StatusDead)
     BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg)
       .addImm(0).addImm(0);
+  MachineInstr *LdarxInstr =
   BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg())
         .addReg(AddrReg);
   BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
       .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
       .addReg(DesiredReg)
       .addImm(ExtendImm);
   BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
       .addImm(AArch64CC::NE)
       .addMBB(DoneBB)
       .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
bool AArch64ExpandPseudo::expandCMP_SWAP(
   StoreBB->addSuccessor(DoneBB);
 
   DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
   DoneBB->transferSuccessors(&MBB);
 
   MBB.addSuccessor(LoadCmpBB);
 
   NextMBBI = MBB.end();
+
+  // Was there debug-info attached to the pseudo instr? If so, substitute it
+  // with the result of the load, which has the swap result.
+  MF->substituteDebugValuesForInst(MI, *LdarxInstr, 1);
+
   MI.eraseFromParent();
 
   // Recompute livein lists.
   LivePhysRegs LiveRegs;
   computeAndAddLiveIns(LiveRegs, *DoneBB);
   computeAndAddLiveIns(LiveRegs, *StoreBB);
   computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
   // Do an extra pass around the loop to get loop carried registers right.
bool AArch64ExpandPseudo::expandCMP_SWAP_128(
   MF->insert(++LoadCmpBB->getIterator(), StoreBB);
   MF->insert(++StoreBB->getIterator(), DoneBB);
 
   // .Lloadcmp:
   //     ldaxp xDestLo, xDestHi, [xAddr]
   //     cmp xDestLo, xDesiredLo
   //     sbcs xDestHi, xDesiredHi
   //     b.ne .Ldone
+  MachineInstr *LdaxpInstr =
     BuildMI(LoadCmpBB, DL, TII->get(AArch64::LDAXPX))
         .addReg(DestLo.getReg(), RegState::Define)
         .addReg(DestHi.getReg(), RegState::Define)
         .addReg(AddrReg);
   BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
       .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
       .addReg(DesiredLoReg)
       .addImm(0);
   BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
     .addUse(AArch64::WZR)
     .addUse(AArch64::WZR)
     .addImm(AArch64CC::EQ);
bool AArch64ExpandPseudo::expandCMP_SWAP_128(
   StoreBB->addSuccessor(DoneBB);
 
   DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
   DoneBB->transferSuccessors(&MBB);
 
   MBB.addSuccessor(LoadCmpBB);
 
   NextMBBI = MBB.end();
+  // Was there debug-info attached to the pseudo instr? If so, substitute it
+  // with the result of the load, which has the swap result.
+  MF->substituteDebugValuesForInst(MI, *LdaxpInstr, 2);
   MI.eraseFromParent();
 
   // Recompute liveness bottom up.
   LivePhysRegs LiveRegs;
   computeAndAddLiveIns(LiveRegs, *DoneBB);
   computeAndAddLiveIns(LiveRegs, *StoreBB);
   computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
   // Do an extra pass in the loop to get the loop carried dependencies right.
case AArch64::ORRXrr: {
     }
     MachineInstrBuilder MIB1 =
         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode),
                 MI.getOperand(0).getReg())
             .add(MI.getOperand(1))
             .add(MI.getOperand(2))
             .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
     transferImpOps(MI, MIB1, MIB1);
+    auto &MF = *MI.getMF();
+    MF.substituteDebugValuesForInst(MI, *MIB1, 1);
     MI.eraseFromParent();
     return true;
   }
 
   case AArch64::LOADgot: {
     MachineFunction *MF = MBB.getParent();
     Register DstReg = MI.getOperand(0).getReg();
     const MachineOperand &MO1 = MI.getOperand(1);
     unsigned Flags = MO1.getTargetFlags();
 
     if (MF->getTarget().getCodeModel() == CodeModel::Tiny) {
       // Tiny codemodel expand to LDR
       MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
                                         TII->get(AArch64::LDRXl), DstReg);
 
       if (MO1.isGlobal()) {
         MIB.addGlobalAddress(MO1.getGlobal(), 0, Flags);
       } else if (MO1.isSymbol()) {
         MIB.addExternalSymbol(MO1.getSymbolName(), Flags);
       } else {
         assert(MO1.isCPI() &&
                "Only expect globals, externalsymbols, or constant pools");
         MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags);
       }
+      MF->substituteDebugValuesForInst(MI, *MIB, 1);
     } else {
       // Small codemodel expand into ADRP + LDR.
       MachineFunction &MF = *MI.getParent()->getParent();
       DebugLoc DL = MI.getDebugLoc();
       MachineInstrBuilder MIB1 =
           BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
 
       MachineInstrBuilder MIB2;
if (MF->getTarget().getCodeModel() == CodeModel::Tiny) {
         MIB1.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
                                   Flags | AArch64II::MO_PAGE);
         MIB2.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(),
                                   Flags | AArch64II::MO_PAGEOFF |
                                       AArch64II::MO_NC);
       }
 
       transferImpOps(MI, MIB1, MIB2);
+      MF.substituteDebugValuesForInst(MI, *MIB2, 1);
     }
     MI.eraseFromParent();
     return true;
   }
   case AArch64::MOVaddrBA: {
     MachineFunction &MF = *MI.getParent()->getParent();
     if (MF.getSubtarget<AArch64Subtarget>().isTargetMachO()) {
       // blockaddress expressions have to come from a constant pool because the
case AArch64::MOVaddrEXT: {
 
     MachineInstrBuilder MIB2 =
         BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
             .add(MI.getOperand(0))
             .addReg(DstReg)
             .add(MI.getOperand(2))
             .addImm(0);
 
+    auto &MF = *MI.getMF();
     transferImpOps(MI, MIB1, MIB2);
+    MF.substituteDebugValuesForInst(MI, *MIB2, 1);
     MI.eraseFromParent();
     return true;
   }
   case AArch64::ADDlowTLS:
+  {
     // Produce a plain ADD
+    MachineInstrBuilder MIB =
     BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
         .add(MI.getOperand(0))
         .add(MI.getOperand(1))
         .add(MI.getOperand(2))
         .addImm(0);
+    auto &MF = *MI.getMF();
+    MF.substituteDebugValuesForInst(MI, *MIB, 1);
     MI.eraseFromParent();
     return true;
+  }
 
   case AArch64::MOVbaseTLS: {
     Register DstReg = MI.getOperand(0).getReg();
     auto SysReg = AArch64SysReg::TPIDR_EL0;
     MachineFunction *MF = MBB.getParent();
     if (MF->getSubtarget<AArch64Subtarget>().useEL3ForTP())
       SysReg = AArch64SysReg::TPIDR_EL3;
     else if (MF->getSubtarget<AArch64Subtarget>().useEL2ForTP())
       SysReg = AArch64SysReg::TPIDR_EL2;
     else if (MF->getSubtarget<AArch64Subtarget>().useEL1ForTP())
       SysReg = AArch64SysReg::TPIDR_EL1;
+    MachineInstrBuilder MIB =
     BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
         .addImm(SysReg);
+    MF->substituteDebugValuesForInst(MI, *MIB, 1);
     MI.eraseFromParent();
     return true;
   }
 
   case AArch64::MOVi32imm:
     return expandMOVImm(MBB, MBBI, 32);
   case AArch64::MOVi64imm:
     return expandMOVImm(MBB, MBBI, 64);