AMDGPU: Fix assert on m0_lo16/m0_hi16

[arsenm]

Summary

These get added (redundantly) to the bundle expanded for indirect
register accesses. We hit this path only when there is a call in the
function.

[arsenm]

ad4a18251a37a244e3d4375538abfc0894a1e6ac

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

for (const MachineInstr &MI : MBB) {
 
         Register Reg = MO.getReg();
         switch (Reg) {
         case AMDGPU::EXEC:
         case AMDGPU::EXEC_LO:
         case AMDGPU::EXEC_HI:
         case AMDGPU::SCC:
         case AMDGPU::M0:
+        case AMDGPU::M0_LO16:
+        case AMDGPU::M0_HI16:
         case AMDGPU::SRC_SHARED_BASE:
         case AMDGPU::SRC_SHARED_LIMIT:
         case AMDGPU::SRC_PRIVATE_BASE:
         case AMDGPU::SRC_PRIVATE_LIMIT:
         case AMDGPU::SGPR_NULL:
         case AMDGPU::MODE:
           continue;
 

llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll

entry:
   %ins2 = insertelement <16 x float> %ins1, float 17.0, i32 %add2
   store <16 x float> %ins1, <16 x float> addrspace(1)* %out1
   %out2 = getelementptr <16 x float>, <16 x float> addrspace(1)* %out1, i32 1
   store <16 x float> %ins2, <16 x float> addrspace(1)* %out2
 
   ret void
 }
 
+declare hidden void @foo()
+
+; For functions with calls, we were not accounting for m0_lo16/m0_hi16
+; uses on the BUNDLE created when expanding the insert register pseudo.
+; GCN-LABEL: {{^}}insertelement_with_call:
+; GCN: s_set_gpr_idx_on s{{[0-9]+}}, gpr_idx(DST)
+; GCN-NEXT: v_mov_b32_e32 {{v[0-9]+}}, 8
+; GCN-NEXT: s_set_gpr_idx_off
+; GCN: s_swappc_b64
+define amdgpu_kernel void @insertelement_with_call(<16 x i32> addrspace(1)* %ptr, i32 %idx) #0 {
+  %vec = load <16 x i32>, <16 x i32> addrspace(1)* %ptr
+  %i6 = insertelement <16 x i32> %vec, i32 8, i32 %idx
+  call void @foo()
+  store <16 x i32> %i6, <16 x i32> addrspace(1)* null
+  ret void
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 declare void @llvm.amdgcn.s.barrier() #2
 
 attributes #0 = { nounwind }