This is an archive of the discontinued LLVM Phabricator instance.

Differential D104210

[RISCV][test] Add new tests of SH*ADD in the zba extension
ClosedPublic

Authored by benshi001 on Jun 14 2021, 2:56 AM.

Details

Reviewers
asb
luismarques
MaskRay
craig.topper
Commits
rG07990571812d: [RISCV][test] Add new tests of SH*ADD in the zba extension
Summary

These tests will show the following optimization by future patches.

Rx + Ry * 6 => (SH1ADD (SH2ADD Rx, Ry), Ry)
Rx + Ry * 10 => (SH1ADD (SH3ADD Rx, Ry), Ry)
Rx + Ry * 12 => (SH2ADD (SH3ADD Rx, Ry), Ry)

Diff Detail

Event Timeline

benshi001 created this revision.Jun 14 2021, 2:56 AM
Herald added subscribers: vkmr, frasercrmck, evandro and 22 others. · View Herald TranscriptJun 14 2021, 2:56 AM
benshi001 requested review of this revision.Jun 14 2021, 2:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 14 2021, 2:56 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
benshi001 retitled this revision from [RISCV][test] Add new tests of sh*add in the zba extension to [RISCV][test] Add new tests of SH*ADD in the zba extension.Jun 14 2021, 3:04 AM
Harbormaster completed remote builds in B109059: Diff 351802.Jun 14 2021, 3:39 AM
benshi001 updated this revision to Diff 352311.Jun 15 2021, 6:18 PM
benshi001 edited the summary of this revision. (Show Details)
benshi001 updated this revision to Diff 352324.Jun 15 2021, 7:56 PM
benshi001 edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B109442: Diff 352324.Jun 16 2021, 3:30 AM
MaskRay accepted this revision.Jun 16 2021, 1:31 PM

LGTM.

This revision is now accepted and ready to land.Jun 16 2021, 1:31 PM
This revision was landed with ongoing or failed builds.Jun 16 2021, 4:02 PM
Closed by commit rG07990571812d: [RISCV][test] Add new tests of SH*ADD in the zba extension (authored by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG07990571812d: [RISCV][test] Add new tests of SH*ADD in the zba extension.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
84 lines
162 lines

Diff 352577

llvm/test/CodeGen/RISCV/rv32zba.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IB ; RUN: | FileCheck %s -check-prefix=RV32IB
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zba -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IBA ; RUN: | FileCheck %s -check-prefix=RV32IBA
define signext i16 @sh1add(i64 %0, i16* %1) { define signext i16 @sh1add(i64 %0, i16* %1) {
; RV32I-LABEL: sh1add: ; RV32I-LABEL: sh1add:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: add a0, a2, a0
; RV32I-NEXT: lh a0, 0(a0) ; RV32I-NEXT: lh a0, 0(a0)
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; RV32IBA-NEXT: sh3add a1, a0, a2 ; RV32IBA-NEXT: sh3add a1, a0, a2
; RV32IBA-NEXT: lw a0, 0(a1) ; RV32IBA-NEXT: lw a0, 0(a1)
; RV32IBA-NEXT: lw a1, 4(a1) ; RV32IBA-NEXT: lw a1, 4(a1)
; RV32IBA-NEXT: ret ; RV32IBA-NEXT: ret
%3 = getelementptr inbounds i64, i64* %1, i64 %0 %3 = getelementptr inbounds i64, i64* %1, i64 %0
%4 = load i64, i64* %3 %4 = load i64, i64* %3
ret i64 %4 ret i64 %4
} }
define i32 @addmul6(i32 %a, i32 %b) {
; RV32I-LABEL: addmul6:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 6
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: addmul6:
; RV32IB: # %bb.0:
; RV32IB-NEXT: addi a2, zero, 6
; RV32IB-NEXT: mul a0, a0, a2
; RV32IB-NEXT: add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul6:
; RV32IBA: # %bb.0:
; RV32IBA-NEXT: addi a2, zero, 6
; RV32IBA-NEXT: mul a0, a0, a2
; RV32IBA-NEXT: add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 6
%d = add i32 %c, %b
ret i32 %d
}
define i32 @addmul10(i32 %a, i32 %b) {
; RV32I-LABEL: addmul10:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 10
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: addmul10:
; RV32IB: # %bb.0:
; RV32IB-NEXT: addi a2, zero, 10
; RV32IB-NEXT: mul a0, a0, a2
; RV32IB-NEXT: add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul10:
; RV32IBA: # %bb.0:
; RV32IBA-NEXT: addi a2, zero, 10
; RV32IBA-NEXT: mul a0, a0, a2
; RV32IBA-NEXT: add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 10
%d = add i32 %c, %b
ret i32 %d
}
define i32 @addmul12(i32 %a, i32 %b) {
; RV32I-LABEL: addmul12:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 12
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: addmul12:
; RV32IB: # %bb.0:
; RV32IB-NEXT: addi a2, zero, 12
; RV32IB-NEXT: mul a0, a0, a2
; RV32IB-NEXT: add a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: addmul12:
; RV32IBA: # %bb.0:
; RV32IBA-NEXT: addi a2, zero, 12
; RV32IBA-NEXT: mul a0, a0, a2
; RV32IBA-NEXT: add a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 12
%d = add i32 %c, %b
ret i32 %d
}

llvm/test/CodeGen/RISCV/rv64zba.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-b -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IB ; RUN: | FileCheck %s -check-prefix=RV64IB
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IBA ; RUN: | FileCheck %s -check-prefix=RV64IBA
define i64 @slliuw(i64 %a) nounwind { define i64 @slliuw(i64 %a) nounwind {
; RV64I-LABEL: slliuw: ; RV64I-LABEL: slliuw:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 31 ; RV64I-NEXT: srli a0, a0, 31
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 350 Lines • ▼ Show 20 Lines
; RV64IBA: # %bb.0: ; RV64IBA: # %bb.0:
; RV64IBA-NEXT: sh3add.uw a0, a0, a1 ; RV64IBA-NEXT: sh3add.uw a0, a0, a1
; RV64IBA-NEXT: ret ; RV64IBA-NEXT: ret
%3 = shl i64 %0, 3 %3 = shl i64 %0, 3
%4 = and i64 %3, 34359738360 %4 = and i64 %3, 34359738360
%5 = add i64 %4, %1 %5 = add i64 %4, %1
ret i64 %5 ret i64 %5
} }
define i64 @addmul6(i64 %a, i64 %b) {
; RV64I-LABEL: addmul6:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 6
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: addmul6:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a2, zero, 6
; RV64IB-NEXT: mul a0, a0, a2
; RV64IB-NEXT: add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul6:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: addi a2, zero, 6
; RV64IBA-NEXT: mul a0, a0, a2
; RV64IBA-NEXT: add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 6
%d = add i64 %c, %b
ret i64 %d
}
define i64 @addmul10(i64 %a, i64 %b) {
; RV64I-LABEL: addmul10:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 10
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: addmul10:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a2, zero, 10
; RV64IB-NEXT: mul a0, a0, a2
; RV64IB-NEXT: add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul10:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: addi a2, zero, 10
; RV64IBA-NEXT: mul a0, a0, a2
; RV64IBA-NEXT: add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 10
%d = add i64 %c, %b
ret i64 %d
}
define i64 @addmul12(i64 %a, i64 %b) {
; RV64I-LABEL: addmul12:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 12
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: addmul12:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a2, zero, 12
; RV64IB-NEXT: mul a0, a0, a2
; RV64IB-NEXT: add a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmul12:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: addi a2, zero, 12
; RV64IBA-NEXT: mul a0, a0, a2
; RV64IBA-NEXT: add a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 12
%d = add i64 %c, %b
ret i64 %d
}
define i32 @addmulw6(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addmulw6:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 6
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: addmulw6:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a2, zero, 6
; RV64IB-NEXT: mul a0, a0, a2
; RV64IB-NEXT: addw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmulw6:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: addi a2, zero, 6
; RV64IBA-NEXT: mul a0, a0, a2
; RV64IBA-NEXT: addw a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i32 %a, 6
%d = add i32 %c, %b
ret i32 %d
}
define i32 @addmulw10(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addmulw10:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 10
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: addmulw10:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a2, zero, 10
; RV64IB-NEXT: mul a0, a0, a2
; RV64IB-NEXT: addw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmulw10:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: addi a2, zero, 10
; RV64IBA-NEXT: mul a0, a0, a2
; RV64IBA-NEXT: addw a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i32 %a, 10
%d = add i32 %c, %b
ret i32 %d
}
define i32 @addmulw12(i32 signext %a, i32 signext %b) {
; RV64I-LABEL: addmulw12:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 12
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: addmulw12:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a2, zero, 12
; RV64IB-NEXT: mul a0, a0, a2
; RV64IB-NEXT: addw a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: addmulw12:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: addi a2, zero, 12
; RV64IBA-NEXT: mul a0, a0, a2
; RV64IBA-NEXT: addw a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i32 %a, 12
%d = add i32 %c, %b
ret i32 %d
}