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[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
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Authored by craig.topper on Jun 10 2021, 5:11 PM.

Details

Summary

This helps us select W instructions in more cases. Most of the
affected tests have had the sign_extend_inreg or AND folded into
sextload/zextload.

Diff Detail

Event Timeline

craig.topper created this revision.Jun 10 2021, 5:11 PM
craig.topper requested review of this revision.Jun 10 2021, 5:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 10 2021, 5:11 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
jrtc27 added inline comments.Jun 10 2021, 5:53 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
1341

Narrator: yes, yes they should :)

1352–1356

You could generalise this with computeKnownBits. I don't know if that is a useful thing to do or not though.

jrtc27 accepted this revision.Jun 10 2021, 5:54 PM
This revision is now accepted and ready to land.Jun 10 2021, 5:54 PM
craig.topper added inline comments.Jun 10 2021, 6:58 PM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
1352–1356

We try to favor 0xffffffff through targetShrinkDemandedConstant during DAG combine.

This revision was landed with ongoing or failed builds.Jun 10 2021, 7:18 PM
This revision was automatically updated to reflect the committed changes.