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Differential D102859

[NFC][AMDGPU] Add documentation for AMD Instinct MI100 accelerator
ClosedPublic

Authored by t-tye on May 20 2021, 11:48 AM.

Details

Reviewers
kzhuravl
rampitec
b-sumner
dp
Commits
rG355114a7532d: [NFC][AMDGPU] Add documentation for AMD Instinct MI100 accelerator
Summary

Add link to documentation for "AMD Instinct MI100 Instruction Set
Architecture" to AMDGPUUsage.rst.

Diff Detail

Event Timeline

t-tye created this revision.May 20 2021, 11:48 AM
Herald added subscribers: kerbowa, tpr, dstuttard and 3 others. · View Herald TranscriptMay 20 2021, 11:48 AM
t-tye requested review of this revision.May 20 2021, 11:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 20 2021, 11:48 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
rampitec accepted this revision.May 20 2021, 11:54 AM
This revision is now accepted and ready to land.May 20 2021, 11:54 AM
kzhuravl accepted this revision.May 20 2021, 11:55 AM
Harbormaster completed remote builds in B105478: Diff 346810.May 20 2021, 12:43 PM
t-tye mentioned this in D102837: [AMDGPU][DOC][NFC] Added links to public description of MI100 ISA.May 20 2021, 1:15 PM
t-tye updated this revision to Diff 346839.May 20 2021, 1:25 PM
t-tye added a subscriber: dp.

Add feedback from @dp .

t-tye added a reviewer: dp.May 20 2021, 1:26 PM
Harbormaster completed remote builds in B105495: Diff 346839.May 20 2021, 1:59 PM
dp accepted this revision.May 21 2021, 5:09 AM

LGTM

Closed by commit rG355114a7532d: [NFC][AMDGPU] Add documentation for AMD Instinct MI100 accelerator (authored by t-tye). · Explain WhyMay 21 2021, 9:52 AM
This revision was automatically updated to reflect the committed changes.
t-tye added a commit: rG355114a7532d: [NFC][AMDGPU] Add documentation for AMD Instinct MI100 accelerator.

Revision Contents

PathSize
llvm/
docs/
11 lines

Diff 347067

llvm/docs/AMDGPUUsage.rst

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 312 Lines • ▼ Show 20 Lines ``gfx805`` - ``tongapro`` ``amdgcn`` dGPU - Offset - *rocm-amdhsa* - FirePro S7150
M7170 M7170
``gfx810`` - ``stoney`` ``amdgcn`` APU - xnack - Offset - *rocm-amdhsa* *TBA* ``gfx810`` - ``stoney`` ``amdgcn`` APU - xnack - Offset - *rocm-amdhsa* *TBA*
flat - *pal-amdhsa* flat - *pal-amdhsa*
scratch - *pal-amdpal* .. TODO:: scratch - *pal-amdpal* .. TODO::
Add product Add product
names. names.
**GCN GFX9 (Vega)** [AMD-GCN-GFX9]_ **GCN GFX9 (Vega)** [AMD-GCN-GFX9]_ [AMD-GCN-GFX908-CDNA1]_
----------------------------------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------------------------------
``gfx900`` ``amdgcn`` dGPU - xnack - Absolute - *rocm-amdhsa* - Radeon Vega ``gfx900`` ``amdgcn`` dGPU - xnack - Absolute - *rocm-amdhsa* - Radeon Vega
flat - *pal-amdhsa* Frontier Edition flat - *pal-amdhsa* Frontier Edition
scratch - *pal-amdpal* - Radeon RX Vega 56 scratch - *pal-amdpal* - Radeon RX Vega 56
- Radeon RX Vega 64 - Radeon RX Vega 64
- Radeon RX Vega 64 - Radeon RX Vega 64
Liquid Liquid
- Radeon Instinct MI25 - Radeon Instinct MI25
▲ Show 20 Lines • Show All 11,080 Lines • ▼ Show 20 Linesin this description.
:doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>` :doc:`gfx1011<AMDGPU/AMDGPUAsmGFX1011>` :doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>` :doc:`gfx1011<AMDGPU/AMDGPUAsmGFX1011>`
:doc:`gfx1012<AMDGPU/AMDGPUAsmGFX1011>` :doc:`gfx1012<AMDGPU/AMDGPUAsmGFX1011>`
=================================== ======================================= =================================== =======================================
For more information about instructions, their semantics and supported For more information about instructions, their semantics and supported
combinations of operands, refer to one of instruction set architecture manuals combinations of operands, refer to one of instruction set architecture manuals
[AMD-GCN-GFX6]_, [AMD-GCN-GFX7]_, [AMD-GCN-GFX8]_, [AMD-GCN-GFX9]_, [AMD-GCN-GFX6]_, [AMD-GCN-GFX7]_, [AMD-GCN-GFX8]_, [AMD-GCN-GFX9]_,
[AMD-GCN-GFX10-RDNA1]_ and [AMD-GCN-GFX10-RDNA2]_. [AMD-GCN-GFX908-CDNA1]_, [AMD-GCN-GFX10-RDNA1]_ and [AMD-GCN-GFX10-RDNA2]_.
Operands Operands
~~~~~~~~ ~~~~~~~~
Detailed description of operands may be found :doc:`here<AMDGPUOperandSyntax>`. Detailed description of operands may be found :doc:`here<AMDGPUOperandSyntax>`.
Modifiers Modifiers
~~~~~~~~~ ~~~~~~~~~
▲ Show 20 Lines • Show All 725 Lines • ▼ Show 20 Lines
effort required to accurately calculate GPR usage. effort required to accurately calculate GPR usage.
Additional Documentation Additional Documentation
======================== ========================
.. [AMD-GCN-GFX6] `AMD Southern Islands Series ISA <http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf>`__ .. [AMD-GCN-GFX6] `AMD Southern Islands Series ISA <http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf>`__
.. [AMD-GCN-GFX7] `AMD Sea Islands Series ISA <http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Instruction_Set_Architecture.pdf>`_ .. [AMD-GCN-GFX7] `AMD Sea Islands Series ISA <http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Instruction_Set_Architecture.pdf>`_
.. [AMD-GCN-GFX8] `AMD GCN3 Instruction Set Architecture <http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_Architecture_rev1.1.pdf>`__ .. [AMD-GCN-GFX8] `AMD GCN3 Instruction Set Architecture <http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_Architecture_rev1.1.pdf>`__
.. [AMD-GCN-GFX9] `AMD "Vega" Instruction Set Architecture <http://developer.amd.com/wordpress/media/2013/12/Vega_Shader_ISA_28July2017.pdf>`__ .. [AMD-GCN-GFX9] `AMD Vega Instruction Set Architecture <http://developer.amd.com/wordpress/media/2013/12/Vega_Shader_ISA_28July2017.pdf>`__
.. [AMD-GCN-GFX10-RDNA1] `AMD "RDNA 1.0" Instruction Set Architecture <https://gpuopen.com/wp-content/uploads/2019/08/RDNA_Shader_ISA_5August2019.pdf>`__ .. [AMD-GCN-GFX908-CDNA1] `AMD Instinct MI100 Instruction Set Architecture <https://developer.amd.com/wp-content/resources/CDNA1_Shader_ISA_14December2020.pdf>`__
.. [AMD-GCN-GFX10-RDNA2] `AMD "RDNA 2" Instruction Set Architecture <https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf>`__ .. [AMD-GCN-GFX10-RDNA1] `AMD RDNA 1.0 Instruction Set Architecture <https://gpuopen.com/wp-content/uploads/2019/08/RDNA_Shader_ISA_5August2019.pdf>`__
.. [AMD-GCN-GFX10-RDNA2] `AMD RDNA 2 Instruction Set Architecture <https://developer.amd.com/wp-content/resources/RDNA2_Shader_ISA_November2020.pdf>`__
.. [AMD-RADEON-HD-2000-3000] `AMD R6xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf>`__ .. [AMD-RADEON-HD-2000-3000] `AMD R6xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf>`__
.. [AMD-RADEON-HD-4000] `AMD R7xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf>`__ .. [AMD-RADEON-HD-4000] `AMD R7xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf>`__
.. [AMD-RADEON-HD-5000] `AMD Evergreen shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf>`__ .. [AMD-RADEON-HD-5000] `AMD Evergreen shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf>`__
.. [AMD-RADEON-HD-6000] `AMD Cayman/Trinity shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf>`__ .. [AMD-RADEON-HD-6000] `AMD Cayman/Trinity shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf>`__
.. [AMD-ROCm] `AMD ROCm™ Platform <https://rocmdocs.amd.com/>`__ .. [AMD-ROCm] `AMD ROCm™ Platform <https://rocmdocs.amd.com/>`__
.. [AMD-ROCm-github] `AMD ROCm™ github <http://github.com/RadeonOpenCompute>`__ .. [AMD-ROCm-github] `AMD ROCm™ github <http://github.com/RadeonOpenCompute>`__
.. [AMD-ROCm-Release-Notes] `AMD ROCm Release Notes <https://github.com/RadeonOpenCompute/ROCm>`__ .. [AMD-ROCm-Release-Notes] `AMD ROCm Release Notes <https://github.com/RadeonOpenCompute/ROCm>`__
.. [CLANG-ATTR] `Attributes in Clang <https://clang.llvm.org/docs/AttributeReference.html>`__ .. [CLANG-ATTR] `Attributes in Clang <https://clang.llvm.org/docs/AttributeReference.html>`__
.. [DWARF] `DWARF Debugging Information Format <http://dwarfstd.org/>`__ .. [DWARF] `DWARF Debugging Information Format <http://dwarfstd.org/>`__
.. [ELF] `Executable and Linkable Format (ELF) <http://www.sco.com/developers/gabi/>`__ .. [ELF] `Executable and Linkable Format (ELF) <http://www.sco.com/developers/gabi/>`__
.. [HRF] `Heterogeneous-race-free Memory Models <http://benedictgaster.org/wp-content/uploads/2014/01/asplos269-FINAL.pdf>`__ .. [HRF] `Heterogeneous-race-free Memory Models <http://benedictgaster.org/wp-content/uploads/2014/01/asplos269-FINAL.pdf>`__
.. [HSA] `Heterogeneous System Architecture (HSA) Foundation <http://www.hsafoundation.com/>`__ .. [HSA] `Heterogeneous System Architecture (HSA) Foundation <http://www.hsafoundation.com/>`__
.. [MsgPack] `Message Pack <http://www.msgpack.org/>`__ .. [MsgPack] `Message Pack <http://www.msgpack.org/>`__
.. [OpenCL] `The OpenCL Specification Version 2.0 <http://www.khronos.org/registry/cl/specs/opencl-2.0.pdf>`__ .. [OpenCL] `The OpenCL Specification Version 2.0 <http://www.khronos.org/registry/cl/specs/opencl-2.0.pdf>`__
.. [SEMVER] `Semantic Versioning <https://semver.org/>`__ .. [SEMVER] `Semantic Versioning <https://semver.org/>`__
.. [YAML] `YAML Ain't Markup Language (YAML™) Version 1.2 <http://www.yaml.org/spec/1.2/spec.html>`__ .. [YAML] `YAML Ain't Markup Language (YAML™) Version 1.2 <http://www.yaml.org/spec/1.2/spec.html>`__