[RISCV][test] Add new tests of or/xor in the zbs extension

[benshi001]

These tests will show how

; RV32IBS-NEXT:    lui a1, 16
; RV32IBS-NEXT:    addi a1, a1, 1365
; RV32IBS-NEXT:    or a0, a0, a1

will be optimized to

; RV32IBS-NEXT:    ori a0, a0, 1365
; RV32IBS-NEXT:    bseti a0, 16

[craig.topper]

LGTM

llvm/test/CodeGen/RISCV/rv32zbs.ll

 ; RV32IBS-LABEL: xor_i32_96:
 ; RV32IBS:       # %bb.0:
 ; RV32IBS-NEXT:    xori a0, a0, 96
 ; RV32IBS-NEXT:    ret
   %xor = xor i32 %a, 96
   ret i32 %xor
 }
 
+define i32 @xor_i32_66901(i32 %a) nounwind {
+; RV32I-LABEL: xor_i32_66901:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 16
+; RV32I-NEXT:    addi a1, a1, 1365
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: xor_i32_66901:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 16
+; RV32IB-NEXT:    addi a1, a1, 1365
+; RV32IB-NEXT:    xor a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: xor_i32_66901:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 16
+; RV32IBS-NEXT:    addi a1, a1, 1365
+; RV32IBS-NEXT:    xor a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %xor = xor i32 %a, 66901
+  ret i32 %xor
+}
+
 define i32 @or_i32_4098(i32 %a) nounwind {
 ; RV32I-LABEL: or_i32_4098:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;

 ;
 ; RV32IBS-LABEL: or_i32_96:
 ; RV32IBS:       # %bb.0:
 ; RV32IBS-NEXT:    ori a0, a0, 96
 ; RV32IBS-NEXT:    ret
   %or = or i32 %a, 96
   ret i32 %or
 }
+
+define i32 @or_i32_66901(i32 %a) nounwind {
+; RV32I-LABEL: or_i32_66901:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 16
+; RV32I-NEXT:    addi a1, a1, 1365
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: or_i32_66901:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 16
+; RV32IB-NEXT:    addi a1, a1, 1365
+; RV32IB-NEXT:    or a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: or_i32_66901:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 16
+; RV32IBS-NEXT:    addi a1, a1, 1365
+; RV32IBS-NEXT:    or a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %or = or i32 %a, 66901
+  ret i32 %or
+}

llvm/test/CodeGen/RISCV/rv64zbs.ll

 ; RV64IBS:       # %bb.0:
 ; RV64IBS-NEXT:    bseti a0, a0, 0
 ; RV64IBS-NEXT:    bseti a0, a0, 32
 ; RV64IBS-NEXT:    ret
   %or = or i64 %a, 4294967297
   ret i64 %or
 }
 
+define i64 @xor_i64_66901(i64 %a) nounwind {
+; RV64I-LABEL: xor_i64_66901:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw a1, a1, 1365
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: xor_i64_66901:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 16
+; RV64IB-NEXT:    addiw a1, a1, 1365
+; RV64IB-NEXT:    xor a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: xor_i64_66901:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    lui a1, 16
+; RV64IBS-NEXT:    addiw a1, a1, 1365
+; RV64IBS-NEXT:    xor a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %xor = xor i64 %a, 66901
+  ret i64 %xor
+}
+
 define i64 @or_i64_4099(i64 %a) nounwind {
 ; RV64I-LABEL: or_i64_4099:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, 3
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;

 ;
 ; RV64IBS-LABEL: or_i64_96:
 ; RV64IBS:       # %bb.0:
 ; RV64IBS-NEXT:    ori a0, a0, 96
 ; RV64IBS-NEXT:    ret
   %or = or i64 %a, 96
   ret i64 %or
 }
+
+define i64 @or_i64_66901(i64 %a) nounwind {
+; RV64I-LABEL: or_i64_66901:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw a1, a1, 1365
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: or_i64_66901:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 16
+; RV64IB-NEXT:    addiw a1, a1, 1365
+; RV64IB-NEXT:    or a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: or_i64_66901:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    lui a1, 16
+; RV64IBS-NEXT:    addiw a1, a1, 1365
+; RV64IBS-NEXT:    or a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %or = or i64 %a, 66901
+  ret i64 %or
+}