[PowerPC] Canonicalize shuffles on big endian targets as well

[nemanjai]

Summary

Extend shuffle canonicalization and conversion of shuffles fed by vectorized scalars to big endian subtargets. For big endian subtargets, loads and direct moves of scalars into vector registers put the data in the correct element for SCALAR_TO_VECTOR if the data type is 8 bytes wide. However, if the data type is narrower, the value still ends up in the wrong place - althouth a different wrong place than on little endian targets.
This patch extends the combine that keeps values where they are if they feed a shuffle to big endian targets.

[jsji]

LGTM with some nits.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

9580

Do we need to update the comments to be more specific about 8 bytes?

9597

Is this affecting little endian as well? If so, any test that can show the behavior change?

14220

unsigned ElemSizeInBytes?

14252

Is it possible that getVectorNumElements is 1? Then we will overflow the NewMask here?

14260

comments need update?

14298

should be unsigned here.? getScalarSizeInBits returning unsigned.
Also ElemSizeInBits?

14329

nit: Should we use local var instead? bool isLittleEndian = Subtarget.isLittleEndian();

14402

nit:

How about something like:

if(isLittleEndian)
   RHS = TheSplat;
else
   LHS = TheSplat;

Res = DAG.getVectorShuffle(SVN->getValueType(0), dl, LHS, RHS, ShuffV);

[pjeeva01]

LGTM.

[nemanjai]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

9580

I will change it to: Unexpected size for permuted load on big endian target

9597

In theory, yes. However, we cannot get any offset other than 0 here on LE.
SplatIdx can only be {0, 1} for 8-byte permutes and {0, 1, 2, 3} for 4 byte permutes.

If the splat and load are 8 bytes, SplatIdx must be 1 because otherwise we wouldn't be splatting the value we loaded.

If the splat and load are 4 bytes, SplatIdx must be 3 because otherwise we wouldn't be splatting the value we loaded.

So the conditional above will ensure that 1 - SplatIdx/3 - SplatIdx is 0 respectively.
On BE, this is not necessarily true because we don't adjust SplatIdx in the condition on line 9578. I could of course add the code up there to account for this but felt that it is clearer to just set the offset to zero when the load size and the splat element size are the same.

14220

Sounds good.

14252

I will add an assert for that.

14260

I'll add a note about what this does on BE.

14267

// On big endian targets, this is still useful for SCALAR_TO_VECTOR
// nodes with elements smaller than doubleword because all the ways
// of getting scalar data into a vector register put the value in the
// rightmost element of the left half of the vector.

14298

OK.

14329

Absolutely, will do. Thanks.

14402

Makes sense.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (InputLoad && Subtarget.hasVSX() && V2.isUndef() &&
     bool IsFourByte = PPC::isSplatShuffleMask(SVOp, 4);
     int SplatIdx =
       PPC::getSplatIdxForPPCMnemonics(SVOp, IsFourByte ? 4 : 8, DAG);
 
     // The splat index for permuted loads will be in the left half of the vector
     // which is strictly wider than the loaded value by 8 bytes. So we need to
     // adjust the splat index to point to the correct address in memory.
     if (IsPermutedLoad) {
-      assert(isLittleEndian && "Unexpected permuted load on big endian target");
+      assert((isLittleEndian || IsFourByte) &&
+             "Unexpected permuted load on big endian target");
       SplatIdx += IsFourByte ? 2 : 1;
       assert((SplatIdx < (IsFourByte ? 4 : 2)) &&
              "Splat of a value outside of the loaded memory");
     }
 
     LoadSDNode *LD = cast<LoadSDNode>(*InputLoad);
     // For 4-byte load-and-splat, we need Power9.
     if ((IsFourByte && Subtarget.hasP9Vector()) || !IsFourByte) {
       uint64_t Offset = 0;
       if (IsFourByte)
         Offset = isLittleEndian ? (3 - SplatIdx) * 4 : SplatIdx * 4;
       else
         Offset = isLittleEndian ? (1 - SplatIdx) * 8 : SplatIdx * 8;
 
+      // If the width of the load is the same as the width of the splat,
+      // loading with an offset would load the wrong memory.
+      if (LD->getValueType(0).getSizeInBits() == (IsFourByte ? 32 : 64))
+        Offset = 0;
+
       SDValue BasePtr = LD->getBasePtr();
       if (Offset != 0)
         BasePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
                               BasePtr, DAG.getIntPtrConstant(Offset, dl));
       SDValue Ops[] = {
         LD->getChain(),    // Chain
         BasePtr,           // BasePtr
         DAG.getValueType(Op.getValueType()) // VT
static SDValue isScalarToVec(SDValue Op) {
   Op = Op.getOperand(0);
   if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR)
     return Op;
   return SDValue();
 }
 
 static void fixupShuffleMaskForPermutedSToV(SmallVectorImpl<int> &ShuffV,
                                             int LHSMaxIdx, int RHSMinIdx,
-                                            int RHSMaxIdx, int HalfVec) {
+                                            int RHSMaxIdx, int HalfVec,
+                                            int ElemSize,
+                                            const PPCSubtarget &Subtarget) {
   for (int i = 0, e = ShuffV.size(); i < e; i++) {
     int Idx = ShuffV[i];
     if ((Idx >= 0 && Idx < LHSMaxIdx) || (Idx >= RHSMinIdx && Idx < RHSMaxIdx))
-      ShuffV[i] += HalfVec;
+      ShuffV[i] += Subtarget.isLittleEndian() ? HalfVec : HalfVec - ElemSize;
   }
 }
 
 // Replace a SCALAR_TO_VECTOR with a SCALAR_TO_VECTOR_PERMUTED except if
 // the original is:
 // (<n x Ty> (scalar_to_vector (Ty (extract_elt <n x Ty> %a, C))))
 // In such a case, just change the shuffle mask to extract the element
 // from the permuted index.
-static SDValue getSToVPermuted(SDValue OrigSToV, SelectionDAG &DAG) {
+static SDValue getSToVPermuted(SDValue OrigSToV, SelectionDAG &DAG,
+                               const PPCSubtarget &Subtarget) {
   SDLoc dl(OrigSToV);
   EVT VT = OrigSToV.getValueType();
   assert(OrigSToV.getOpcode() == ISD::SCALAR_TO_VECTOR &&
          "Expecting a SCALAR_TO_VECTOR here");
   SDValue Input = OrigSToV.getOperand(0);
 
   if (Input.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
     ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Input.getOperand(1));
     SDValue OrigVector = Input.getOperand(0);
 
     // Can't handle non-const element indices or different vector types
     // for the input to the extract and the output of the scalar_to_vector.
     if (Idx && VT == OrigVector.getValueType()) {
       SmallVector<int, 16> NewMask(VT.getVectorNumElements(), -1);
-      NewMask[VT.getVectorNumElements() / 2] = Idx->getZExtValue();
+      unsigned ResultInElt = VT.getVectorNumElements() / 2;
+      ResultInElt -= Subtarget.isLittleEndian() ? 0 : 1;
+      NewMask[ResultInElt] = Idx->getZExtValue();
       return DAG.getVectorShuffle(VT, dl, OrigVector, OrigVector, NewMask);
     }
   }
   return DAG.getNode(PPCISD::SCALAR_TO_VECTOR_PERMUTED, dl, VT,
                      OrigSToV.getOperand(0));
 }
 
 // On little endian subtargets, combine shuffles such as:
 // vector_shuffle<16,1,17,3,18,5,19,7,20,9,21,11,22,13,23,15>, <zero>, %b
 // into:
 // vector_shuffle<16,0,17,1,18,2,19,3,20,4,21,5,22,6,23,7>, <zero>, %b
 // because the latter can be matched to a single instruction merge.
 // Furthermore, SCALAR_TO_VECTOR on little endian always involves a permute
 // to put the value into element zero. Adjust the shuffle mask so that the
 // vector can remain in permuted form (to prevent a swap prior to a shuffle).
 SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN,
                                                 SelectionDAG &DAG) const {
   SDValue LHS = SVN->getOperand(0);
   SDValue RHS = SVN->getOperand(1);
   auto Mask = SVN->getMask();
   int NumElts = LHS.getValueType().getVectorNumElements();
   SDValue Res(SVN, 0);
   SDLoc dl(SVN);
 
-  // None of these combines are useful on big endian systems since the ISA
-  // already has a big endian bias.
-  if (!Subtarget.isLittleEndian() || !Subtarget.hasVSX())
+  // Without direct moves, there isn't really any point in doing this because
+  // conversion between scalars and vectors for integers goes through the stack.
+  if (!Subtarget.hasDirectMove())
     return Res;
 
   // If this is not a shuffle of a shuffle and the first element comes from
   // the second vector, canonicalize to the commuted form. This will make it
   // more likely to match one of the single instruction patterns.
   if (Mask[0] >= NumElts && LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
       RHS.getOpcode() != ISD::VECTOR_SHUFFLE) {
     std::swap(LHS, RHS);
     Res = DAG.getCommutedVectorShuffle(*SVN);
     Mask = cast<ShuffleVectorSDNode>(Res)->getMask();
   }
 
   // Adjust the shuffle mask if either input vector comes from a
   // SCALAR_TO_VECTOR and keep the respective input vector in permuted
   // form (to prevent the need for a swap).
   SmallVector<int, 16> ShuffV(Mask.begin(), Mask.end());
   SDValue SToVLHS = isScalarToVec(LHS);
   SDValue SToVRHS = isScalarToVec(RHS);
+  int ElemSize = 0;
   if (SToVLHS || SToVRHS) {
     int NumEltsIn = SToVLHS ? SToVLHS.getValueType().getVectorNumElements()
                             : SToVRHS.getValueType().getVectorNumElements();
     int NumEltsOut = ShuffV.size();
+    ElemSize = SToVLHS ? SToVLHS.getValueType().getScalarSizeInBits()
+                       : SToVRHS.getValueType().getScalarSizeInBits();
 
     // Initially assume that neither input is permuted. These will be adjusted
     // accordingly if either input is.
     int LHSMaxIdx = -1;
     int RHSMinIdx = -1;
     int RHSMaxIdx = -1;
     int HalfVec = LHS.getValueType().getVectorNumElements() / 2;
 
     // Get the permuted scalar to vector nodes for the source(s) that come from
     // ISD::SCALAR_TO_VECTOR.
+    // On big endian systems, this only makes sense for element sizes smaller
+    // than 64 bits since for 64-bit elements, all instructions already put
+    // the value into element zero.
     if (SToVLHS) {
+      if (!Subtarget.isLittleEndian() && ElemSize >= 64)
+        return Res;
       // Set up the values for the shuffle vector fixup.
       LHSMaxIdx = NumEltsOut / NumEltsIn;
-      SToVLHS = getSToVPermuted(SToVLHS, DAG);
+      SToVLHS = getSToVPermuted(SToVLHS, DAG, Subtarget);
       if (SToVLHS.getValueType() != LHS.getValueType())
         SToVLHS = DAG.getBitcast(LHS.getValueType(), SToVLHS);
       LHS = SToVLHS;
     }
     if (SToVRHS) {
+      if (!Subtarget.isLittleEndian() && ElemSize >= 64)
+        return Res;
       RHSMinIdx = NumEltsOut;
       RHSMaxIdx = NumEltsOut / NumEltsIn + RHSMinIdx;
-      SToVRHS = getSToVPermuted(SToVRHS, DAG);
+      SToVRHS = getSToVPermuted(SToVRHS, DAG, Subtarget);
       if (SToVRHS.getValueType() != RHS.getValueType())
         SToVRHS = DAG.getBitcast(RHS.getValueType(), SToVRHS);
       RHS = SToVRHS;
     }
 
     // Fix up the shuffle mask to reflect where the desired element actually is.
     // The minimum and maximum indices that correspond to element zero for both
     // the LHS and RHS are computed and will control which shuffle mask entries
     // are to be changed. For example, if the RHS is permuted, any shuffle mask
     // entries in the range [RHSMinIdx,RHSMaxIdx) will be incremented by
     // HalfVec to refer to the corresponding element in the permuted vector.
     fixupShuffleMaskForPermutedSToV(ShuffV, LHSMaxIdx, RHSMinIdx, RHSMaxIdx,
-                                    HalfVec);
+                                    HalfVec, ElemSize / 8, Subtarget);
     Res = DAG.getVectorShuffle(SVN->getValueType(0), dl, LHS, RHS, ShuffV);
 
     // We may have simplified away the shuffle. We won't be able to do anything
     // further with it here.
     if (!isa<ShuffleVectorSDNode>(Res))
       return Res;
     Mask = cast<ShuffleVectorSDNode>(Res)->getMask();
   }
 
+  SDValue TheSplat = Subtarget.isLittleEndian() ? RHS : LHS;
   // The common case after we commuted the shuffle is that the RHS is a splat
   // and we have elements coming in from the splat at indices that are not
   // conducive to using a merge.
   // Example:
   // vector_shuffle<0,17,1,19,2,21,3,23,4,25,5,27,6,29,7,31> t1, <zero>
-  if (!isSplatBV(RHS))
+  if (!isSplatBV(TheSplat))
     return Res;
 
   // We are looking for a mask such that all even elements are from
   // one vector and all odd elements from the other.
   if (!isAlternatingShuffMask(Mask, NumElts))
     return Res;
 
   // Adjust the mask so we are pulling in the same index from the splat
   // as the index from the interesting vector in consecutive elements.
+  if (Subtarget.isLittleEndian()) {
     // Example (even elements from first vector):
     // vector_shuffle<0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23> t1, <zero>
     if (Mask[0] < NumElts)
       for (int i = 1, e = Mask.size(); i < e; i += 2)
         ShuffV[i] = (ShuffV[i - 1] + NumElts);
     // Example (odd elements from first vector):
     // vector_shuffle<16,0,17,1,18,2,19,3,20,4,21,5,22,6,23,7> t1, <zero>
     else
       for (int i = 0, e = Mask.size(); i < e; i += 2)
         ShuffV[i] = (ShuffV[i + 1] + NumElts);
+  } else {
+    // Example (even elements from first vector):
+    // vector_shuffle<0,16,1,17,2,18,3,19,4,20,5,21,6,22,7,23> <zero>, t1
+    if (Mask[0] < NumElts)
+      for (int i = 0, e = Mask.size(); i < e; i += 2)
+        ShuffV[i] = ShuffV[i + 1] - NumElts;
+    // Example (odd elements from first vector):
+    // vector_shuffle<16,0,17,1,18,2,19,3,20,4,21,5,22,6,23,7> <zero>, t1
+    else
+      for (int i = 1, e = Mask.size(); i < e; i += 2)
+        ShuffV[i] = ShuffV[i - 1] - NumElts;
+  }
 
   // If the RHS has undefs, we need to remove them since we may have created
   // a shuffle that adds those instead of the splat value.
-  SDValue SplatVal = cast<BuildVectorSDNode>(RHS.getNode())->getSplatValue();
-  RHS = DAG.getSplatBuildVector(RHS.getValueType(), dl, SplatVal);
+  SDValue SplatVal =
+      cast<BuildVectorSDNode>(TheSplat.getNode())->getSplatValue();
+  TheSplat = DAG.getSplatBuildVector(TheSplat.getValueType(), dl, SplatVal);
 
-  Res = DAG.getVectorShuffle(SVN->getValueType(0), dl, LHS, RHS, ShuffV);
+  if (Subtarget.isLittleEndian())
+    Res = DAG.getVectorShuffle(SVN->getValueType(0), dl, LHS, TheSplat, ShuffV);
+  else
+    Res = DAG.getVectorShuffle(SVN->getValueType(0), dl, TheSplat, RHS, ShuffV);
   return Res;
 }
 
 SDValue PPCTargetLowering::combineVReverseMemOP(ShuffleVectorSDNode *SVN,
                                                 LSBaseSDNode *LSBase,
                                                 DAGCombinerInfo &DCI) const {
   assert((ISD::isNormalLoad(LSBase) || ISD::isNormalStore(LSBase)) &&
         "Not a reverse memop pattern!");

llvm/lib/Target/PowerPC/PPCInstrVSX.td

let Predicates = [HasVSX, HasOnlySwappingMemOps, IsBigEndian] in {
   def : Pat<(v2i64 (load xoaddr:$src)), (LXVD2X xoaddr:$src)>;
   def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>;
   def : Pat<(v4i32 (int_ppc_vsx_lxvw4x xoaddr:$src)), (LXVW4X xoaddr:$src)>;
   def : Pat<(store v2f64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
   def : Pat<(store v2i64:$rS, xoaddr:$dst), (STXVD2X $rS, xoaddr:$dst)>;
   def : Pat<(store v4i32:$XT, xoaddr:$dst), (STXVW4X $XT, xoaddr:$dst)>;
   def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst),
             (STXVW4X $rS, xoaddr:$dst)>;
+  def : Pat<(v2i64 (scalar_to_vector (i64 (load xoaddr:$src)))),
+           (SUBREG_TO_REG (i64 1), (XFLOADf64 xoaddr:$src), sub_64)>;
 } // HasVSX, HasOnlySwappingMemOps, IsBigEndian
 
 // Any Power8 VSX subtarget.
 let Predicates = [HasVSX, HasP8Vector] in {
 def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
           (XXLEQV $A, $B)>;
 def : Pat<(f64 (extloadf32 xoaddr:$src)),
           (COPY_TO_REGCLASS (XFLOADf32 xoaddr:$src), VSFRC)>;

 def : Pat<DWToSPExtractConv.El1SS1,
           (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
 def : Pat<DWToSPExtractConv.El0US1,
           (f32 (XSCVUXDSP (COPY_TO_REGCLASS $S1, VSFRC)))>;
 def : Pat<DWToSPExtractConv.El1US1,
           (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
 
 // v4f32 scalar <-> vector conversions (BE)
-def : Pat<(v4f32 (scalar_to_vector f32:$A)),
-          (v4f32 (XSCVDPSPN $A))>;
+defm : ScalToVecWPermute<v4f32, (f32 f32:$A), (XSCVDPSPN $A), (XSCVDPSPN $A)>;
 def : Pat<(f32 (vector_extract v4f32:$S, 0)),
           (f32 (XSCVSPDPN $S))>;
 def : Pat<(f32 (vector_extract v4f32:$S, 1)),
           (f32 (XSCVSPDPN (XXSLDWI $S, $S, 1)))>;
 def : Pat<(f32 (vector_extract v4f32:$S, 2)),
           (f32 (XSCVSPDPN (XXPERMDI $S, $S, 2)))>;
 def : Pat<(f32 (vector_extract v4f32:$S, 3)),
           (f32 (XSCVSPDPN (XXSLDWI $S, $S, 3)))>;

 
 // LIWAX - This instruction is used for sign extending i32 -> i64.
 // LIWZX - This instruction will be emitted for i32, f32, and when
 //         zero-extending i32 to i64 (zext i32 -> i64).
 def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))),
           (v2i64 (SUBREG_TO_REG (i64 1), (LIWAX xoaddr:$src), sub_64))>;
 def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))),
           (v2i64 (SUBREG_TO_REG (i64 1), (LIWZX xoaddr:$src), sub_64))>;
-def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))),
-          (v4i32 (XXSLDWIs (LIWZX xoaddr:$src), 1))>;
-def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))),
-          (v4f32 (XXSLDWIs (LIWZX xoaddr:$src), 1))>;
+defm : ScalToVecWPermute<
+  v4i32, (i32 (load xoaddr:$src)),
+  (XXSLDWIs (LIWZX xoaddr:$src), 1),
+  (SUBREG_TO_REG (i64 1), (LIWZX xoaddr:$src), sub_64)>;
+defm : ScalToVecWPermute<
+  v4f32, (f32 (load xoaddr:$src)),
+  (XXSLDWIs (LIWZX xoaddr:$src), 1),
+  (SUBREG_TO_REG (i64 1), (LIWZX xoaddr:$src), sub_64)>;
 
 def : Pat<DWToSPExtractConv.BVU,
           (v4f32 (VPKUDUM (XXSLDWI (XVCVUXDSP $S1), (XVCVUXDSP $S1), 3),
                           (XXSLDWI (XVCVUXDSP $S2), (XVCVUXDSP $S2), 3)))>;
 def : Pat<DWToSPExtractConv.BVS,
           (v4f32 (VPKUDUM (XXSLDWI (XVCVSXDSP $S1), (XVCVSXDSP $S1), 3),
                           (XXSLDWI (XVCVSXDSP $S2), (XVCVSXDSP $S2), 3)))>;
 def : Pat<(store (i32 (extractelt v4i32:$A, 1)), xoaddr:$src),

 def : Pat<(v4i32 (build_vector immSExt5NonZero:$A, immSExt5NonZero:$A,
                                immSExt5NonZero:$A, immSExt5NonZero:$A)),
           (v4i32 (VSPLTISW imm:$A))>;
 } // HasVSX, HasDirectMove
 
 // Big endian VSX subtarget with direct moves.
 let Predicates = [HasVSX, HasDirectMove, IsBigEndian] in {
 // v16i8 scalar <-> vector conversions (BE)
-def : Pat<(v16i8 (scalar_to_vector i32:$A)),
-          (v16i8 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64))>;
-def : Pat<(v8i16 (scalar_to_vector i32:$A)),
-          (v8i16 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64))>;
-def : Pat<(v4i32 (scalar_to_vector i32:$A)),
-          (v4i32 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64))>;
+defm : ScalToVecWPermute<
+  v16i8, (i32 i32:$A),
+  (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64),
+  (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
+defm : ScalToVecWPermute<
+  v8i16, (i32 i32:$A),
+  (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64),
+  (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
+defm : ScalToVecWPermute<
+  v4i32, (i32 i32:$A),
+  (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64),
+  (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
 def : Pat<(v2i64 (scalar_to_vector i64:$A)),
           (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>;
 
 // v2i64 scalar <-> vector conversions (BE)
 def : Pat<(i64 (vector_extract v2i64:$S, 0)),
           (i64 VectorExtractions.LE_DWORD_1)>;
 def : Pat<(i64 (vector_extract v2i64:$S, 1)),
           (i64 VectorExtractions.LE_DWORD_0)>;

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

 ; P9LE-LABEL: spltMemVali:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxvwsx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltMemVali:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwzx f0, 0, r3
-; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
-; P8BE-NEXT:    xxspltw v2, vs0, 0
+; P8BE-NEXT:    xxspltw v2, vs0, 1
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltMemVali:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    xxspltw v2, vs0, 1
 ; P8LE-NEXT:    blr
 entry:

 ; P9LE-LABEL: spltMemValui:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxvwsx v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: spltMemValui:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    lfiwzx f0, 0, r3
-; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
-; P8BE-NEXT:    xxspltw v2, vs0, 0
+; P8BE-NEXT:    xxspltw v2, vs0, 1
 ; P8BE-NEXT:    blr
 ;
 ; P8LE-LABEL: spltMemValui:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    lfiwzx f0, 0, r3
 ; P8LE-NEXT:    xxspltw v2, vs0, 1
 ; P8LE-NEXT:    blr
 entry:

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P8
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr8 -mattr=-vsx -ppc-asm-full-reg-names \
 ; RUN:     -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-NOVSX
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN: FileCheck %s --check-prefix=CHECK-P7
 
 define dso_local <16 x i8> @testmrghb(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: testmrghb:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrghb:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrghb:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrglb v2, v2, v3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrghb:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    vmrghb v2, v3, v2
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: testmrghb:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P7-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrghb2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: testmrghb2:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrghb2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrghb v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrghb2:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrglb v2, v3, v2
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrghb2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 ;

 ; CHECK-P8-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrghh:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrghh:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrglh v2, v2, v3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrghh:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    vmrghh v2, v3, v2
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: testmrghh:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P7-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrghh2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: testmrghh2:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    vmrghh v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrghh2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrghh v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrghh2:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrglh v2, v3, v2
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrghh2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI3_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 ;

 ; CHECK-P8-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrglb:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrglb:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrghb v2, v2, v3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrglb:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    vmrglb v2, v3, v2
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: testmrglb:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    vmrglb v2, v3, v2
 ; CHECK-P7-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrglb2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: testmrglb2:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrglb2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrglb v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrglb2:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrghb v2, v3, v2
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrglb2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI5_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 ;

 ; CHECK-P8-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrglh:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrglh:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrglh:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    vmrglh v2, v3, v2
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: testmrglh:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P7-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrglh2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: testmrglh2:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrglh2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrglh2:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrglh2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI7_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 ;

 ; CHECK-P8-NEXT:    vmrghw v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrghw:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrghw:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrglw v2, v2, v3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrghw:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    vmrghw v2, v3, v2
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: testmrghw:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    vmrghw v2, v3, v2
 ; CHECK-P7-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrghw2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: testmrghw2:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrghw2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrghw v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrghw2:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrglw v2, v3, v2
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrghw2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI9_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 ;

 ; CHECK-P8-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrglw:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrglw:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrglw:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    vmrglw v2, v3, v2
 ; CHECK-NOVSX-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: testmrglw:
 ; CHECK-P7:       # %bb.0: # %entry
 ; CHECK-P7-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P7-NEXT:    blr
 entry:
   %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
   ret <16 x i8> %shuffle
 }
 define dso_local <16 x i8> @testmrglw2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
 ; CHECK-P8-LABEL: testmrglw2:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testmrglw2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrglw2:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrglw2:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI11_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI11_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3
 ; CHECK-NOVSX-NEXT:    vperm v2, v3, v2, v4
 ; CHECK-NOVSX-NEXT:    blr
 ;

 ;
 ; CHECK-P9-LABEL: testmrglb3:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxsd v2, 0(r3)
 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testmrglb3:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    lxsd v2, 0(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI12_0@toc@ha
+; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI12_0@toc@l
+; CHECK-BE-NEXT:    lxvx v3, 0, r3
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testmrglb3:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    vxor v2, v2, v2
 ; CHECK-NOVSX-NEXT:    ld r3, 0(r3)
 ; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI12_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r4, r4, .LCPI12_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r4
 ; CHECK-NOVSX-NEXT:    std r3, -16(r1)

 ; CHECK-P9-NEXT:    mr r30, r3
 ; CHECK-P9-NEXT:    bl dummy
 ; CHECK-P9-NEXT:    nop
 ; CHECK-P9-NEXT:    xxlxor f0, f0, f0
 ; CHECK-P9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; CHECK-P9-NEXT:    xxmrghd vs0, vs1, vs0
 ; CHECK-P9-NEXT:    stxv vs0, 0(r30)
 ;
+; CHECK-BE-LABEL: no_crash_elt0_from_RHS:
+; CHECK-BE:       # %bb.0: # %test_entry
+; CHECK-BE-NEXT:    mflr r0
+; CHECK-BE-NEXT:    std r0, 16(r1)
+; CHECK-BE-NEXT:    stdu r1, -128(r1)
+; CHECK-BE-NEXT:    std r30, 112(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    mr r30, r3
+; CHECK-BE-NEXT:    bl dummy
+; CHECK-BE-NEXT:    nop
+; CHECK-BE-NEXT:    xxlxor f0, f0, f0
+; CHECK-BE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
+; CHECK-BE-NEXT:    xxmrghd vs0, vs0, vs1
+; CHECK-BE-NEXT:    stxv vs0, 0(r30)
+;
 ; CHECK-NOVSX-LABEL: no_crash_elt0_from_RHS:
 ; CHECK-NOVSX:       # %bb.0: # %test_entry
 ; CHECK-NOVSX-NEXT:    mflr r0
 ; CHECK-NOVSX-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NOVSX-NEXT:    std r0, 16(r1)
 ; CHECK-NOVSX-NEXT:    stdu r1, -48(r1)
 ; CHECK-NOVSX-NEXT:    mr r30, r3
 ; CHECK-NOVSX-NEXT:    bl dummy

 ; CHECK-P8-NEXT:    mtvsrwz v2, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: no_crash_bitcast:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: no_crash_bitcast:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    mtvsrws v2, r3
+; CHECK-BE-NEXT:    vmrghw v2, v2, v2
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: no_crash_bitcast:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI14_0@toc@ha
 ; CHECK-NOVSX-NEXT:    stw r3, -16(r1)
 ; CHECK-NOVSX-NEXT:    addi r3, r1, -16
 ; CHECK-NOVSX-NEXT:    addi r4, r4, .LCPI14_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
 ; CHECK-NOVSX-NEXT:    lvx v2, 0, r4

 ; CHECK-P9-LABEL: replace_undefs_in_splat:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI15_0@toc@l
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-NEXT:    vmrgow v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: replace_undefs_in_splat:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI15_0@toc@l
+; CHECK-BE-NEXT:    lxvx v3, 0, r3
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI15_1@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI15_1@toc@l
+; CHECK-BE-NEXT:    lxvx v4, 0, r3
+; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: replace_undefs_in_splat:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI15_1@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI15_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r3
 ; CHECK-NOVSX-NEXT:    addi r3, r4, .LCPI15_1@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v4, 0, r3

 ; CHECK-P9-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P9-NEXT:    lxsiwzx v2, r3, r4
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI16_0@toc@l
 ; CHECK-P9-NEXT:    lxvx v3, 0, r3
 ; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: no_RAUW_in_combine_during_legalize:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    sldi r4, r4, 2
+; CHECK-BE-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-NEXT:    lxsiwzx v2, r3, r4
+; CHECK-BE-NEXT:    vmrghb v2, v2, v3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: no_RAUW_in_combine_during_legalize:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    sldi r4, r4, 2
 ; CHECK-NOVSX-NEXT:    vxor v2, v2, v2
 ; CHECK-NOVSX-NEXT:    lwzx r3, r3, r4
 ; CHECK-NOVSX-NEXT:    std r3, -16(r1)
 ; CHECK-NOVSX-NEXT:    addi r3, r1, -16
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r3

 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testSplat4Low:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addi r3, r3, 4
 ; CHECK-P9-NEXT:    lxvwsx v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testSplat4Low:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    addi r3, r3, 4
+; CHECK-BE-NEXT:    lxvwsx v2, 0, r3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testSplat4Low:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    ld r3, 0(r3)
 ; CHECK-NOVSX-NEXT:    addi r4, r1, -16
 ; CHECK-NOVSX-NEXT:    std r3, -16(r1)
 ; CHECK-NOVSX-NEXT:    lvx v2, 0, r4
 ; CHECK-NOVSX-NEXT:    vspltw v2, v2, 2
 ; CHECK-NOVSX-NEXT:    blr

 ; CHECK-P8-NEXT:    xxspltw v2, vs0, 1
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testSplat4hi:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxvwsx v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testSplat4hi:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    lxvwsx v2, 0, r3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testSplat4hi:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    ld r3, 0(r3)
 ; CHECK-NOVSX-NEXT:    addi r4, r1, -16
 ; CHECK-NOVSX-NEXT:    std r3, -16(r1)
 ; CHECK-NOVSX-NEXT:    lvx v2, 0, r4
 ; CHECK-NOVSX-NEXT:    vspltw v2, v2, 3
 ; CHECK-NOVSX-NEXT:    blr

 ; CHECK-P8-NEXT:    lxvdsx v2, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testSplat8:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxvdsx v2, 0, r3
 ; CHECK-P9-NEXT:    blr
 ;
+; CHECK-BE-LABEL: testSplat8:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    lxvdsx v2, 0, r3
+; CHECK-BE-NEXT:    blr
+;
 ; CHECK-NOVSX-LABEL: testSplat8:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    ld r3, 0(r3)
 ; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI19_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r4, r4, .LCPI19_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v2, 0, r4
 ; CHECK-NOVSX-NEXT:    std r3, -16(r1)
 ; CHECK-NOVSX-NEXT:    addi r3, r1, -16

llvm/test/CodeGen/PowerPC/fp-strict-round.ll

 define <2 x float> @fptrunc_v2f32_v2f64(<2 x double> %vf1) {
 ; P8-LABEL: fptrunc_v2f32_v2f64:
 ; P8:       # %bb.0:
 ; P8-NEXT:    xxswapd vs0, v2
 ; P8-NEXT:    xsrsp f1, v2
 ; P8-NEXT:    xsrsp f0, f0
 ; P8-NEXT:    xscvdpspn v2, f1
 ; P8-NEXT:    xscvdpspn v3, f0
-; P8-NEXT:    vmrghw v2, v2, v3
+; P8-NEXT:    vmrgow v2, v2, v3
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fptrunc_v2f32_v2f64:
 ; P9:       # %bb.0:
 ; P9-NEXT:    xsrsp f0, v2
 ; P9-NEXT:    xscvdpspn vs0, f0
 ; P9-NEXT:    xxsldwi v3, vs0, vs0, 3
 ; P9-NEXT:    xxswapd vs0, v2

llvm/test/CodeGen/PowerPC/load-and-splat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
 ; RUN:   -check-prefix=P9
-; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
+; RUN:   -check-prefix=P9LE
+; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
 ; RUN:   -check-prefix=P8
+; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
+; RUN:   -check-prefix=P8LE
+
 define dso_local void @test(<2 x double>* nocapture %c, double* nocapture readonly %a) local_unnamed_addr {
 ; P9-LABEL: test:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r4, r4, 24
 ; P9-NEXT:    lxvdsx vs0, 0, r4
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: test:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    addi r4, r4, 24
+; P9LE-NEXT:    lxvdsx vs0, 0, r4
+; P9LE-NEXT:    stxv vs0, 0(r3)
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: test:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r4, r4, 24
 ; P8-NEXT:    lxvdsx vs0, 0, r4
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: test:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    addi r4, r4, 24
+; P8LE-NEXT:    lxvdsx vs0, 0, r4
+; P8LE-NEXT:    stxvd2x vs0, 0, r3
+; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds double, double* %a, i64 3
   %0 = load double, double* %arrayidx, align 8
   %splat.splatinsert.i = insertelement <2 x double> undef, double %0, i32 0
   %splat.splat.i = shufflevector <2 x double> %splat.splatinsert.i, <2 x double> undef, <2 x i32> zeroinitializer
   store <2 x double> %splat.splat.i, <2 x double>* %c, align 16
   ret void
 }
 
 define dso_local void @test2(<4 x float>* nocapture %c, float* nocapture readonly %a) local_unnamed_addr {
 ; P9-LABEL: test2:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r4, r4, 12
 ; P9-NEXT:    lxvwsx vs0, 0, r4
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: test2:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    addi r4, r4, 12
+; P9LE-NEXT:    lxvwsx vs0, 0, r4
+; P9LE-NEXT:    stxv vs0, 0(r3)
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: test2:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r4, r4, 12
 ; P8-NEXT:    lfiwzx f0, 0, r4
-; P8-NEXT:    xxspltw v2, vs0, 1
-; P8-NEXT:    stvx v2, 0, r3
+; P8-NEXT:    xxspltw vs0, vs0, 1
+; P8-NEXT:    stxvw4x vs0, 0, r3
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: test2:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    addi r4, r4, 12
+; P8LE-NEXT:    lfiwzx f0, 0, r4
+; P8LE-NEXT:    xxspltw v2, vs0, 1
+; P8LE-NEXT:    stvx v2, 0, r3
+; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %a, i64 3
   %0 = load float, float* %arrayidx, align 4
   %splat.splatinsert.i = insertelement <4 x float> undef, float %0, i32 0
   %splat.splat.i = shufflevector <4 x float> %splat.splatinsert.i, <4 x float> undef, <4 x i32> zeroinitializer
   store <4 x float> %splat.splat.i, <4 x float>* %c, align 16
   ret void
 }
 
 define dso_local void @test3(<4 x i32>* nocapture %c, i32* nocapture readonly %a) local_unnamed_addr {
 ; P9-LABEL: test3:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r4, r4, 12
 ; P9-NEXT:    lxvwsx vs0, 0, r4
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: test3:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    addi r4, r4, 12
+; P9LE-NEXT:    lxvwsx vs0, 0, r4
+; P9LE-NEXT:    stxv vs0, 0(r3)
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: test3:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r4, r4, 12
 ; P8-NEXT:    lfiwzx f0, 0, r4
-; P8-NEXT:    xxspltw v2, vs0, 1
-; P8-NEXT:    stvx v2, 0, r3
+; P8-NEXT:    xxspltw vs0, vs0, 1
+; P8-NEXT:    stxvw4x vs0, 0, r3
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: test3:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    addi r4, r4, 12
+; P8LE-NEXT:    lfiwzx f0, 0, r4
+; P8LE-NEXT:    xxspltw v2, vs0, 1
+; P8LE-NEXT:    stvx v2, 0, r3
+; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %a, i64 3
   %0 = load i32, i32* %arrayidx, align 4
   %splat.splatinsert.i = insertelement <4 x i32> undef, i32 %0, i32 0
   %splat.splat.i = shufflevector <4 x i32> %splat.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer
   store <4 x i32> %splat.splat.i, <4 x i32>* %c, align 16
   ret void
 }
 
 define dso_local void @test4(<2 x i64>* nocapture %c, i64* nocapture readonly %a) local_unnamed_addr {
 ; P9-LABEL: test4:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r4, r4, 24
 ; P9-NEXT:    lxvdsx vs0, 0, r4
 ; P9-NEXT:    stxv vs0, 0(r3)
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: test4:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    addi r4, r4, 24
+; P9LE-NEXT:    lxvdsx vs0, 0, r4
+; P9LE-NEXT:    stxv vs0, 0(r3)
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: test4:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r4, r4, 24
 ; P8-NEXT:    lxvdsx vs0, 0, r4
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: test4:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    addi r4, r4, 24
+; P8LE-NEXT:    lxvdsx vs0, 0, r4
+; P8LE-NEXT:    stxvd2x vs0, 0, r3
+; P8LE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i64, i64* %a, i64 3
   %0 = load i64, i64* %arrayidx, align 8
   %splat.splatinsert.i = insertelement <2 x i64> undef, i64 %0, i32 0
   %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> undef, <2 x i32> zeroinitializer
   store <2 x i64> %splat.splat.i, <2 x i64>* %c, align 16
   ret void
 }
 
 define <16 x i8> @unadjusted_lxvwsx(i32* %s, i32* %t) {
 ; P9-LABEL: unadjusted_lxvwsx:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lxvwsx v2, 0, r3
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: unadjusted_lxvwsx:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    lxvwsx v2, 0, r3
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: unadjusted_lxvwsx:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfiwzx f0, 0, r3
 ; P8-NEXT:    xxspltw v2, vs0, 1
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: unadjusted_lxvwsx:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    lfiwzx f0, 0, r3
+; P8LE-NEXT:    xxspltw v2, vs0, 1
+; P8LE-NEXT:    blr
   entry:
     %0 = bitcast i32* %s to <4 x i8>*
     %1 = load <4 x i8>, <4 x i8>* %0, align 4
     %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
     ret <16 x i8> %2
 }
 
 define <16 x i8> @adjusted_lxvwsx(i64* %s, i64* %t) {
 ; P9-LABEL: adjusted_lxvwsx:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r3, r3, 4
 ; P9-NEXT:    lxvwsx v2, 0, r3
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: adjusted_lxvwsx:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    addi r3, r3, 4
+; P9LE-NEXT:    lxvwsx v2, 0, r3
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: adjusted_lxvwsx:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lfdx f0, 0, r3
-; P8-NEXT:    xxspltw v2, vs0, 0
+; P8-NEXT:    xxspltw v2, vs0, 1
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: adjusted_lxvwsx:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    lfdx f0, 0, r3
+; P8LE-NEXT:    xxspltw v2, vs0, 0
+; P8LE-NEXT:    blr
   entry:
     %0 = bitcast i64* %s to <8 x i8>*
     %1 = load <8 x i8>, <8 x i8>* %0, align 8
     %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
     ret <16 x i8> %2
 }
 
 define <16 x i8> @unadjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
 ; P9-LABEL: unadjusted_lxvwsx_v16i8:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lxvwsx v2, 0, r3
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: unadjusted_lxvwsx_v16i8:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    lxvwsx v2, 0, r3
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: unadjusted_lxvwsx_v16i8:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    lvx v2, 0, r3
-; P8-NEXT:    xxspltw v2, v2, 3
+; P8-NEXT:    lxvw4x vs0, 0, r3
+; P8-NEXT:    xxspltw v2, vs0, 0
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: unadjusted_lxvwsx_v16i8:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    lvx v2, 0, r3
+; P8LE-NEXT:    xxspltw v2, v2, 3
+; P8LE-NEXT:    blr
   entry:
     %0 = load <16 x i8>, <16 x i8>* %s, align 16
     %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
     ret <16 x i8> %1
 }
 
 define <16 x i8> @adjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
 ; P9-LABEL: adjusted_lxvwsx_v16i8:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r3, r3, 4
 ; P9-NEXT:    lxvwsx v2, 0, r3
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: adjusted_lxvwsx_v16i8:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    addi r3, r3, 4
+; P9LE-NEXT:    lxvwsx v2, 0, r3
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: adjusted_lxvwsx_v16i8:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    lvx v2, 0, r3
-; P8-NEXT:    xxspltw v2, v2, 2
+; P8-NEXT:    lxvw4x vs0, 0, r3
+; P8-NEXT:    xxspltw v2, vs0, 1
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: adjusted_lxvwsx_v16i8:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    lvx v2, 0, r3
+; P8LE-NEXT:    xxspltw v2, v2, 2
+; P8LE-NEXT:    blr
   entry:
     %0 = load <16 x i8>, <16 x i8>* %s, align 16
     %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
     ret <16 x i8> %1
 }
 
 define <16 x i8> @adjusted_lxvwsx_v16i8_2(<16 x i8> *%s, <16 x i8> %t) {
 ; P9-LABEL: adjusted_lxvwsx_v16i8_2:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r3, r3, 8
 ; P9-NEXT:    lxvwsx v2, 0, r3
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: adjusted_lxvwsx_v16i8_2:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    addi r3, r3, 8
+; P9LE-NEXT:    lxvwsx v2, 0, r3
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: adjusted_lxvwsx_v16i8_2:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    lvx v2, 0, r3
-; P8-NEXT:    xxspltw v2, v2, 1
+; P8-NEXT:    lxvw4x vs0, 0, r3
+; P8-NEXT:    xxspltw v2, vs0, 2
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: adjusted_lxvwsx_v16i8_2:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    lvx v2, 0, r3
+; P8LE-NEXT:    xxspltw v2, v2, 1
+; P8LE-NEXT:    blr
   entry:
     %0 = load <16 x i8>, <16 x i8>* %s, align 16
     %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
     ret <16 x i8> %1
 }
 
 define <16 x i8> @adjusted_lxvwsx_v16i8_3(<16 x i8> *%s, <16 x i8> %t) {
 ; P9-LABEL: adjusted_lxvwsx_v16i8_3:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r3, r3, 12
 ; P9-NEXT:    lxvwsx v2, 0, r3
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: adjusted_lxvwsx_v16i8_3:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    addi r3, r3, 12
+; P9LE-NEXT:    lxvwsx v2, 0, r3
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: adjusted_lxvwsx_v16i8_3:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    lvx v2, 0, r3
-; P8-NEXT:    xxspltw v2, v2, 0
+; P8-NEXT:    lxvw4x vs0, 0, r3
+; P8-NEXT:    xxspltw v2, vs0, 3
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: adjusted_lxvwsx_v16i8_3:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    lvx v2, 0, r3
+; P8LE-NEXT:    xxspltw v2, v2, 0
+; P8LE-NEXT:    blr
   entry:
     %0 = load <16 x i8>, <16 x i8>* %s, align 16
     %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
     ret <16 x i8> %1
 }
 
 define <16 x i8> @unadjusted_lxvdsx(i64* %s, i64* %t) {
 ; P9-LABEL: unadjusted_lxvdsx:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lxvdsx v2, 0, r3
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: unadjusted_lxvdsx:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    lxvdsx v2, 0, r3
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: unadjusted_lxvdsx:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lxvdsx v2, 0, r3
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: unadjusted_lxvdsx:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    lxvdsx v2, 0, r3
+; P8LE-NEXT:    blr
   entry:
     %0 = bitcast i64* %s to <8 x i8>*
     %1 = load <8 x i8>, <8 x i8>* %0, align 8
     %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
     ret <16 x i8> %2
 }
 
 define <16 x i8> @unadjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
 ; P9-LABEL: unadjusted_lxvdsx_v16i8:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    lxvdsx v2, 0, r3
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: unadjusted_lxvdsx_v16i8:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    lxvdsx v2, 0, r3
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: unadjusted_lxvdsx_v16i8:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    lxvdsx v2, 0, r3
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: unadjusted_lxvdsx_v16i8:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    lxvdsx v2, 0, r3
+; P8LE-NEXT:    blr
   entry:
     %0 = load <16 x i8>, <16 x i8>* %s, align 16
     %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
     ret <16 x i8> %1
 }
 
 define <16 x i8> @adjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
 ; P9-LABEL: adjusted_lxvdsx_v16i8:
 ; P9:       # %bb.0: # %entry
 ; P9-NEXT:    addi r3, r3, 8
 ; P9-NEXT:    lxvdsx v2, 0, r3
 ; P9-NEXT:    blr
 ;
+; P9LE-LABEL: adjusted_lxvdsx_v16i8:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    addi r3, r3, 8
+; P9LE-NEXT:    lxvdsx v2, 0, r3
+; P9LE-NEXT:    blr
+;
 ; P8-LABEL: adjusted_lxvdsx_v16i8:
 ; P8:       # %bb.0: # %entry
 ; P8-NEXT:    addi r3, r3, 8
 ; P8-NEXT:    lxvdsx v2, 0, r3
 ; P8-NEXT:    blr
+;
+; P8LE-LABEL: adjusted_lxvdsx_v16i8:
+; P8LE:       # %bb.0: # %entry
+; P8LE-NEXT:    addi r3, r3, 8
+; P8LE-NEXT:    lxvdsx v2, 0, r3
+; P8LE-NEXT:    blr
   entry:
     %0 = load <16 x i8>, <16 x i8>* %s, align 16
     %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
     ret <16 x i8> %1
 }

llvm/test/CodeGen/PowerPC/load-v4i8-improved.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck --check-prefix=CHECK-LE \
 ; RUN:   -implicit-check-not vmrg -implicit-check-not=vperm %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \
 ; RUN:   -implicit-check-not vmrg -implicit-check-not=vperm %s
 
 define <16 x i8> @test(i32* %s, i32* %t) {
 ; CHECK-LE-LABEL: test:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-LE-NEXT:    xxspltw v2, vs0, 1
 ; CHECK-LE-NEXT:    blr
-
+;
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lfiwzx f0, 0, r3
-; CHECK-NEXT:    xxsldwi vs0, f0, f0, 1
-; CHECK-NEXT:    xxspltw v2, vs0, 0
+; CHECK-NEXT:    xxspltw v2, vs0, 1
 ; CHECK-NEXT:    blr
+
 entry:
   %0 = bitcast i32* %s to <4 x i8>*
   %1 = load <4 x i8>, <4 x i8>* %0, align 4
   %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
   ret <16 x i8> %2
 }

llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:       -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \
 ; RUN:       | FileCheck %s
 ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:       -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 -relocation-model=pic \
 ; RUN:       | FileCheck %s -check-prefix=CHECK-LE
 
 ; The build[csilf] functions simply test the scalar_to_vector handling with
 ; direct moves. This corresponds to the "insertelement" instruction. Subsequent
 ; to this, there will be a splat corresponding to the shufflevector.
 
 @d = common global double 0.000000e+00, align 8
 
 ; Function Attrs: norecurse nounwind readnone
 define <16 x i8> @buildc(i8 zeroext %a) {
+; CHECK-LABEL: buildc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrwz v2, r3
+; CHECK-NEXT:    vspltb v2, v2, 7
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: buildc:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mtvsrd v2, r3
+; CHECK-LE-NEXT:    vspltb v2, v2, 7
+; CHECK-LE-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 0
   %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
   ret <16 x i8> %splat.splat
-; CHECK-LABEL: buildc
-; CHECK: sldi r3, r3, 56
-; CHECK: mtvsrd v2, r3
-; CHECK-LE-LABEL: buildc
-; CHECK-LE: mtvsrd v2, r3
-; CHECK-LE: vspltb v2, v2, 7
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <8 x i16> @builds(i16 zeroext %a) {
+; CHECK-LABEL: builds:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrwz v2, r3
+; CHECK-NEXT:    vsplth v2, v2, 3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: builds:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mtvsrd v2, r3
+; CHECK-LE-NEXT:    vsplth v2, v2, 3
+; CHECK-LE-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0
   %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
   ret <8 x i16> %splat.splat
-; CHECK-LABEL: builds
-; CHECK: sldi r3, r3, 48
-; CHECK: mtvsrd v2, r3
-; CHECK-LE-LABEL: builds
-; CHECK-LE: mtvsrd v2, r3
-; CHECK-LE: vsplth v2, v2, 3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <4 x i32> @buildi(i32 zeroext %a) {
+; CHECK-LABEL: buildi:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtfprwz f0, r3
+; CHECK-NEXT:    xxspltw v2, vs0, 1
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: buildi:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mtfprwz f0, r3
+; CHECK-LE-NEXT:    xxspltw v2, vs0, 1
+; CHECK-LE-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0
   %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
   ret <4 x i32> %splat.splat
-; CHECK-LABEL: buildi
-; CHECK: mtfprwz f0, r3
-; CHECK: xxspltw v2, vs0, 1
-; CHECK-LE-LABEL: buildi
-; CHECK-LE: mtfprwz f0, r3
-; CHECK-LE: xxspltw v2, vs0, 1
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <2 x i64> @buildl(i64 %a) {
+; CHECK-LABEL: buildl:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtfprd f0, r3
+; CHECK-NEXT:    xxspltd v2, vs0, 0
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: buildl:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mtfprd f0, r3
+; CHECK-LE-NEXT:    xxspltd v2, vs0, 0
+; CHECK-LE-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <2 x i64> undef, i64 %a, i32 0
   %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
   ret <2 x i64> %splat.splat
-; CHECK-LABEL: buildl
-; CHECK: mtfprd f0, r3
-; CHECK-LE-LABEL: buildl
-; CHECK-LE: mtfprd f0, r3
-; CHECK-LE: xxspltd v2, vs0, 0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define <4 x float> @buildf(float %a) {
+; CHECK-LABEL: buildf:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvdpspn vs0, f1
+; CHECK-NEXT:    xxspltw v2, vs0, 0
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: buildf:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xscvdpspn vs0, f1
+; CHECK-LE-NEXT:    xxspltw v2, vs0, 0
+; CHECK-LE-NEXT:    blr
 entry:
   %splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0
   %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
   ret <4 x float> %splat.splat
-; CHECK-LABEL: buildf
-; CHECK: xscvdpspn vs0, f1
-; CHECK: xxspltw v2, vs0, 0
-; CHECK-LE-LABEL: buildf
-; CHECK-LE: xscvdpspn vs0, f1
-; CHECK-LE: xxspltw v2, vs0, 0
 }
 
 ; The optimization to remove stack operations from PPCDAGToDAGISel::Select
 ; should still trigger for v2f64, producing an lxvdsx.
 ; Function Attrs: norecurse nounwind readonly
 define <2 x double> @buildd() {
+; CHECK-LABEL: buildd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-NEXT:    ld r3, .LC0@toc@l(r3)
+; CHECK-NEXT:    lxvdsx v2, 0, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: buildd:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    addis r3, r2, .LC0@toc@ha
+; CHECK-LE-NEXT:    ld r3, .LC0@toc@l(r3)
+; CHECK-LE-NEXT:    lxvdsx v2, 0, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %0 = load double, double* @d, align 8
   %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0
   %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %splat.splat
-; CHECK-LABEL: buildd
-; CHECK: ld r3, .LC0@toc@l(r3)
-; CHECK: lxvdsx v2, 0, r3
-; CHECK-LE-LABEL: buildd
-; CHECK-LE: ld r3, .LC0@toc@l(r3)
-; CHECK-LE: lxvdsx v2, 0, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc0(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 8, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc0:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 0
   ret i8 %vecext
-; CHECK-LABEL: @getsc0
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 8, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc0
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: clrldi r3, r3, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc1(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 16, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 1
   ret i8 %vecext
-; CHECK-LABEL: @getsc1
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 16, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc1
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 56, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc2(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 24, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc2:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 48, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 2
   ret i8 %vecext
-; CHECK-LABEL: @getsc2
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 24, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc2
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 48, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc3(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 32, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc3:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 40, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 3
   ret i8 %vecext
-; CHECK-LABEL: @getsc3
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 32, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc3
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 40, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc4(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 40, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc4:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 32, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 4
   ret i8 %vecext
-; CHECK-LABEL: @getsc4
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 40, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc4
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 32, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc5(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 48, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc5:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 24, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 5
   ret i8 %vecext
-; CHECK-LABEL: @getsc5
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 48, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc5
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 24, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc6(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc6:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc6:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 16, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 6
   ret i8 %vecext
-; CHECK-LABEL: @getsc6
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 56, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc6
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 16, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc7(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc7:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc7:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 8, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 7
   ret i8 %vecext
-; CHECK-LABEL: @getsc7
-; CHECK: mfvsrd r3, v2
-; CHECK: clrldi r3, r3, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc7
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 8, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc8(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 8, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc8:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 8
   ret i8 %vecext
-; CHECK-LABEL: @getsc8
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 8, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc8
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: clrldi r3, r3, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc9(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc9:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 16, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc9:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 9
   ret i8 %vecext
-; CHECK-LABEL: @getsc9
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 16, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc9
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 56, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc10(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc10:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 24, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc10:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 48, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 10
   ret i8 %vecext
-; CHECK-LABEL: @getsc10
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 24, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc10
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 48, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc11(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc11:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 32, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc11:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 40, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 11
   ret i8 %vecext
-; CHECK-LABEL: @getsc11
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 32, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc11
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 40, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc12(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc12:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 40, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc12:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 32, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 12
   ret i8 %vecext
-; CHECK-LABEL: @getsc12
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 40, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc12
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 32, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc13(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc13:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 48, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc13:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 24, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 13
   ret i8 %vecext
-; CHECK-LABEL: @getsc13
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 48, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc13
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 24, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc14(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc14:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc14:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 16, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 14
   ret i8 %vecext
-; CHECK-LABEL: @getsc14
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 56, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc14
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 16, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getsc15(<16 x i8> %vsc) {
+; CHECK-LABEL: getsc15:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsc15:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 8, 56
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 15
   ret i8 %vecext
-; CHECK-LABEL: @getsc15
-; CHECK: mffprd r3, f0
-; CHECK: clrldi  r3, r3, 56
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getsc15
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 8, 56
-; CHECK-LE: extsb r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc0(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 8, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc0:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 0
   ret i8 %vecext
-; CHECK-LABEL: @getuc0
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 8, 56
-; CHECK-LE-LABEL: @getuc0
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: clrldi r3, r3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc1(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 16, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 1
   ret i8 %vecext
-; CHECK-LABEL: @getuc1
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 16, 56
-; CHECK-LE-LABEL: @getuc1
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 56, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc2(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 24, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc2:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 48, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 2
   ret i8 %vecext
-; CHECK-LABEL: @getuc2
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 24, 56
-; CHECK-LE-LABEL: @getuc2
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 48, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc3(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 32, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc3:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 40, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 3
   ret i8 %vecext
-; CHECK-LABEL: @getuc3
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 32, 56
-; CHECK-LE-LABEL: @getuc3
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 40, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc4(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 40, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc4:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 32, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 4
   ret i8 %vecext
-; CHECK-LABEL: @getuc4
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 40, 56
-; CHECK-LE-LABEL: @getuc4
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 32, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc5(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 48, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc5:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 24, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 5
   ret i8 %vecext
-; CHECK-LABEL: @getuc5
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 48, 56
-; CHECK-LE-LABEL: @getuc5
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 24, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc6(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc6:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc6:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 16, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 6
   ret i8 %vecext
-; CHECK-LABEL: @getuc6
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 56, 56
-; CHECK-LE-LABEL: @getuc6
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 16, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc7(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc7:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc7:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 8, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 7
   ret i8 %vecext
-; CHECK-LABEL: @getuc7
-; CHECK: mfvsrd r3, v2
-; CHECK: clrldi   r3, r3, 56
-; CHECK-LE-LABEL: @getuc7
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 8, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc8(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 8, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc8:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 8
   ret i8 %vecext
-; CHECK-LABEL: @getuc8
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 8, 56
-; CHECK-LE-LABEL: @getuc8
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: clrldi r3, r3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc9(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc9:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 16, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc9:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 9
   ret i8 %vecext
-; CHECK-LABEL: @getuc9
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 16, 56
-; CHECK-LE-LABEL: @getuc9
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 56, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc10(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc10:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 24, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc10:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 48, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 10
   ret i8 %vecext
-; CHECK-LABEL: @getuc10
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 24, 56
-; CHECK-LE-LABEL: @getuc10
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 48, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc11(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc11:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 32, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc11:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 40, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 11
   ret i8 %vecext
-; CHECK-LABEL: @getuc11
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 32, 56
-; CHECK-LE-LABEL: @getuc11
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 40, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc12(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc12:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 40, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc12:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 32, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 12
   ret i8 %vecext
-; CHECK-LABEL: @getuc12
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 40, 56
-; CHECK-LE-LABEL: @getuc12
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 32, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc13(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc13:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 48, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc13:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 24, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 13
   ret i8 %vecext
-; CHECK-LABEL: @getuc13
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 48, 56
-; CHECK-LE-LABEL: @getuc13
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 24, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc14(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc14:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc14:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 16, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 14
   ret i8 %vecext
-; CHECK-LABEL: @getuc14
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 56, 56
-; CHECK-LE-LABEL: @getuc14
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 16, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getuc15(<16 x i8> %vuc) {
+; CHECK-LABEL: getuc15:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getuc15:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 8, 56
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 15
   ret i8 %vecext
-; CHECK-LABEL: @getuc15
-; CHECK: mffprd r3, f0
-; CHECK: clrldi   r3, r3, 56
-; CHECK-LE-LABEL: @getuc15
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 8, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) {
-; CHECK-LABEL: @getvelsc
-; CHECK: andi. r4, r5, 8
-; CHECK: li r3, 7
-; CHECK: lvsl v3, 0, r4
-; CHECK: andc r3, r3, r5
-; CHECK: sldi r3, r3, 3
-; CHECK: vperm v2, v2, v2, v3
-; CHECK: mfvsrd r4, v2
-; CHECK: srd r3, r4, r3
-; CHECK: extsb r3, r3
-; CHECK-LE-LABEL: @getvelsc
-; CHECK-LE: li r3, 8
-; CHECK-LE: andc r3, r3, r5
-; CHECK-LE: lvsl v3, 0, r3
-; CHECK-LE: li r3, 7
-; CHECK-LE: and r3, r3, r5
-; CHECK-LE: vperm v2, v2, v2, v3
-; CHECK-LE: sldi r3, r3, 3
-; CHECK-LE: mfvsrd r4, v2
-; CHECK-LE: srd r3, r4, r3
-; CHECK-LE: extsb r3, r3
+; CHECK-LABEL: getvelsc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi. r4, r5, 8
+; CHECK-NEXT:    li r3, 7
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    andc r3, r3, r5
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    vperm v2, v2, v2, v3
+; CHECK-NEXT:    mfvsrd r4, v2
+; CHECK-NEXT:    srd r3, r4, r3
+; CHECK-NEXT:    extsb r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getvelsc:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    li r3, 8
+; CHECK-LE-NEXT:    andc r3, r3, r5
+; CHECK-LE-NEXT:    lvsl v3, 0, r3
+; CHECK-LE-NEXT:    li r3, 7
+; CHECK-LE-NEXT:    and r3, r3, r5
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    sldi r3, r3, 3
+; CHECK-LE-NEXT:    mfvsrd r4, v2
+; CHECK-LE-NEXT:    srd r3, r4, r3
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vsc, i32 %i
   ret i8 %vecext
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) {
-; CHECK-LABEL: @getveluc
-; CHECK: andi. r4, r5, 8
-; CHECK: li r3, 7
-; CHECK: lvsl v3, 0, r4
-; CHECK: andc r3, r3, r5
-; CHECK: sldi r3, r3, 3
-; CHECK: vperm v2, v2, v2, v3
-; CHECK: mfvsrd r4, v2
-; CHECK: srd r3, r4, r3
-; CHECK: clrldi  r3, r3, 5
-; CHECK-LE-LABEL: @getveluc
-; CHECK-LE: li r3, 8
-; CHECK-LE: andc r3, r3, r5
-; CHECK-LE: lvsl v3, 0, r3
-; CHECK-LE: li r3, 7
-; CHECK-LE: and r3, r3, r5
-; CHECK-LE: vperm v2, v2, v2, v3
-; CHECK-LE: sldi r3, r3, 3
-; CHECK-LE: mfvsrd r4, v2
-; CHECK-LE: srd r3, r4, r3
-; CHECK-LE: clrldi r3, r3, 56
+; CHECK-LABEL: getveluc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi. r4, r5, 8
+; CHECK-NEXT:    li r3, 7
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    andc r3, r3, r5
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    vperm v2, v2, v2, v3
+; CHECK-NEXT:    mfvsrd r4, v2
+; CHECK-NEXT:    srd r3, r4, r3
+; CHECK-NEXT:    clrldi r3, r3, 56
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getveluc:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    li r3, 8
+; CHECK-LE-NEXT:    andc r3, r3, r5
+; CHECK-LE-NEXT:    lvsl v3, 0, r3
+; CHECK-LE-NEXT:    li r3, 7
+; CHECK-LE-NEXT:    and r3, r3, r5
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    sldi r3, r3, 3
+; CHECK-LE-NEXT:    mfvsrd r4, v2
+; CHECK-LE-NEXT:    srd r3, r4, r3
+; CHECK-LE-NEXT:    clrldi r3, r3, 56
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 %i
   ret i8 %vecext
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss0(<8 x i16> %vss) {
+; CHECK-LABEL: getss0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 16, 48
+; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getss0:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    extsh r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 0
   ret i16 %vecext
-; CHECK-LABEL: @getss0
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 16, 48
-; CHECK: extsh r3, r3
-; CHECK-LE-LABEL: @getss0
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: clrldi r3, r3, 48
-; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss1(<8 x i16> %vss) {
+; CHECK-LABEL: getss1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 32, 48
+; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getss1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 48, 48
+; CHECK-LE-NEXT:    extsh r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 1
   ret i16 %vecext
-; CHECK-LABEL: @getss1
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 32, 48
-; CHECK: extsh r3, r3
-; CHECK-LE-LABEL: @getss1
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 48, 48
-; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss2(<8 x i16> %vss) {
+; CHECK-LABEL: getss2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 48, 48
+; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getss2:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 32, 48
+; CHECK-LE-NEXT:    extsh r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 2
   ret i16 %vecext
-; CHECK-LABEL: @getss2
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 48, 48
-; CHECK: extsh r3, r3
-; CHECK-LE-LABEL: @getss2
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 32, 48
-; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss3(<8 x i16> %vss) {
+; CHECK-LABEL: getss3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getss3:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 16, 48
+; CHECK-LE-NEXT:    extsh r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 3
   ret i16 %vecext
-; CHECK-LABEL: @getss3
-; CHECK: mfvsrd r3, v2
-; CHECK: clrldi r3, r3, 48
-; CHECK: extsh r3, r3
-; CHECK-LE-LABEL: @getss3
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 16, 48
-; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss4(<8 x i16> %vss) {
+; CHECK-LABEL: getss4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 16, 48
+; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getss4:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    extsh r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 4
   ret i16 %vecext
-; CHECK-LABEL: @getss4
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 16, 48
-; CHECK: extsh r3, r3
-; CHECK-LE-LABEL: @getss4
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: clrldi r3, r3, 48
-; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss5(<8 x i16> %vss) {
+; CHECK-LABEL: getss5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 32, 48
+; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getss5:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 48, 48
+; CHECK-LE-NEXT:    extsh r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 5
   ret i16 %vecext
-; CHECK-LABEL: @getss5
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 32, 48
-; CHECK: extsh r3, r3
-; CHECK-LE-LABEL: @getss5
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 48, 48
-; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss6(<8 x i16> %vss) {
+; CHECK-LABEL: getss6:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 48, 48
+; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getss6:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 32, 48
+; CHECK-LE-NEXT:    extsh r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 6
   ret i16 %vecext
-; CHECK-LABEL: @getss6
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 48, 48
-; CHECK: extsh r3, r3
-; CHECK-LE-LABEL: @getss6
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 32, 48
-; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getss7(<8 x i16> %vss) {
+; CHECK-LABEL: getss7:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getss7:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 16, 48
+; CHECK-LE-NEXT:    extsh r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 7
   ret i16 %vecext
-; CHECK-LABEL: @getss7
-; CHECK: mffprd r3, f0
-; CHECK: clrldi  r3, r3, 48
-; CHECK: extsh r3, r3
-; CHECK-LE-LABEL: @getss7
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 16, 48
-; CHECK-LE: extsh r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus0(<8 x i16> %vus) {
+; CHECK-LABEL: getus0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 16, 48
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getus0:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 0
   ret i16 %vecext
-; CHECK-LABEL: @getus0
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 16, 48
-; CHECK-LE-LABEL: @getus0
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: clrldi r3, r3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus1(<8 x i16> %vus) {
+; CHECK-LABEL: getus1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 32, 48
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getus1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 48, 48
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 1
   ret i16 %vecext
-; CHECK-LABEL: @getus1
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 32, 48
-; CHECK-LE-LABEL: @getus1
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 48, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus2(<8 x i16> %vus) {
+; CHECK-LABEL: getus2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    rldicl r3, r3, 48, 48
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getus2:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 32, 48
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 2
   ret i16 %vecext
-; CHECK-LABEL: @getus2
-; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 48, 48
-; CHECK-LE-LABEL: @getus2
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 32, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus3(<8 x i16> %vus) {
+; CHECK-LABEL: getus3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getus3:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    rldicl r3, r3, 16, 48
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 3
   ret i16 %vecext
-; CHECK-LABEL: @getus3
-; CHECK: mfvsrd r3, v2
-; CHECK: clrldi   r3, r3, 48
-; CHECK-LE-LABEL: @getus3
-; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 16, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus4(<8 x i16> %vus) {
+; CHECK-LABEL: getus4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 16, 48
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getus4:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 4
   ret i16 %vecext
-; CHECK-LABEL: @getus4
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 16, 48
-; CHECK-LE-LABEL: @getus4
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: clrldi r3, r3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus5(<8 x i16> %vus) {
+; CHECK-LABEL: getus5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 32, 48
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getus5:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 48, 48
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 5
   ret i16 %vecext
-; CHECK-LABEL: @getus5
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 32, 48
-; CHECK-LE-LABEL: @getus5
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 48, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus6(<8 x i16> %vus) {
+; CHECK-LABEL: getus6:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    rldicl r3, r3, 48, 48
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getus6:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 32, 48
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 6
   ret i16 %vecext
-; CHECK-LABEL: @getus6
-; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 48, 48
-; CHECK-LE-LABEL: @getus6
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 32, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getus7(<8 x i16> %vus) {
+; CHECK-LABEL: getus7:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getus7:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    rldicl r3, r3, 16, 48
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 7
   ret i16 %vecext
-; CHECK-LABEL: @getus7
-; CHECK: mffprd r3, f0
-; CHECK: clrldi   r3, r3, 48
-; CHECK-LE-LABEL: @getus7
-; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 16, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) {
-; CHECK-LABEL: @getvelss
-; CHECK: andi. r4, r5, 4
-; CHECK: li r3, 3
-; CHECK: sldi r4, r4, 1
-; CHECK: andc r3, r3, r5
-; CHECK: lvsl v3, 0, r4
-; CHECK: sldi r3, r3, 4
-; CHECK: vperm v2, v2, v2, v3
-; CHECK: mfvsrd r4, v2
-; CHECK: srd r3, r4, r3
-; CHECK: extsh r3, r3
-; CHECK-LE-LABEL: @getvelss
-; CHECK-LE: li r3, 4
-; CHECK-LE: andc r3, r3, r5
-; CHECK-LE: sldi r3, r3, 1
-; CHECK-LE: lvsl v3, 0, r3
-; CHECK-LE: li r3, 3
-; CHECK-LE: and r3, r3, r5
-; CHECK-LE: vperm v2, v2, v2, v3
-; CHECK-LE: sldi r3, r3, 4
-; CHECK-LE: mfvsrd r4, v2
-; CHECK-LE: srd r3, r4, r3
-; CHECK-LE: extsh r3, r3
+; CHECK-LABEL: getvelss:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi. r4, r5, 4
+; CHECK-NEXT:    li r3, 3
+; CHECK-NEXT:    sldi r4, r4, 1
+; CHECK-NEXT:    andc r3, r3, r5
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    sldi r3, r3, 4
+; CHECK-NEXT:    vperm v2, v2, v2, v3
+; CHECK-NEXT:    mfvsrd r4, v2
+; CHECK-NEXT:    srd r3, r4, r3
+; CHECK-NEXT:    extsh r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getvelss:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    li r3, 4
+; CHECK-LE-NEXT:    andc r3, r3, r5
+; CHECK-LE-NEXT:    sldi r3, r3, 1
+; CHECK-LE-NEXT:    lvsl v3, 0, r3
+; CHECK-LE-NEXT:    li r3, 3
+; CHECK-LE-NEXT:    and r3, r3, r5
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    sldi r3, r3, 4
+; CHECK-LE-NEXT:    mfvsrd r4, v2
+; CHECK-LE-NEXT:    srd r3, r4, r3
+; CHECK-LE-NEXT:    extsh r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vss, i32 %i
   ret i16 %vecext
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) {
-; CHECK-LABEL: @getvelus
-; CHECK: andi. r4, r5, 4
-; CHECK: li r3, 3
-; CHECK: sldi r4, r4, 1
-; CHECK: andc r3, r3, r5
-; CHECK: lvsl v3, 0, r4
-; CHECK: sldi r3, r3, 4
-; CHECK: vperm v2, v2, v2, v3
-; CHECK: mfvsrd r4, v2
-; CHECK: srd r3, r4, r3
-; CHECK: clrldi  r3, r3, 48
-; CHECK-LE-LABEL: @getvelus
-; CHECK-LE: li r3, 4
-; CHECK-LE: andc r3, r3, r5
-; CHECK-LE: sldi r3, r3, 1
-; CHECK-LE: lvsl v3, 0, r3
-; CHECK-LE: li r3, 3
-; CHECK-LE: and r3, r3, r5
-; CHECK-LE: vperm v2, v2, v2, v3
-; CHECK-LE: sldi r3, r3, 4
-; CHECK-LE: mfvsrd r4, v2
-; CHECK-LE: srd r3, r4, r3
-; CHECK-LE: clrldi r3, r3, 48
+; CHECK-LABEL: getvelus:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi. r4, r5, 4
+; CHECK-NEXT:    li r3, 3
+; CHECK-NEXT:    sldi r4, r4, 1
+; CHECK-NEXT:    andc r3, r3, r5
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    sldi r3, r3, 4
+; CHECK-NEXT:    vperm v2, v2, v2, v3
+; CHECK-NEXT:    mfvsrd r4, v2
+; CHECK-NEXT:    srd r3, r4, r3
+; CHECK-NEXT:    clrldi r3, r3, 48
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getvelus:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    li r3, 4
+; CHECK-LE-NEXT:    andc r3, r3, r5
+; CHECK-LE-NEXT:    sldi r3, r3, 1
+; CHECK-LE-NEXT:    lvsl v3, 0, r3
+; CHECK-LE-NEXT:    li r3, 3
+; CHECK-LE-NEXT:    and r3, r3, r5
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    sldi r3, r3, 4
+; CHECK-LE-NEXT:    mfvsrd r4, v2
+; CHECK-LE-NEXT:    srd r3, r4, r3
+; CHECK-LE-NEXT:    clrldi r3, r3, 48
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <8 x i16> %vus, i32 %i
   ret i16 %vecext
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi0(<4 x i32> %vsi) {
+; CHECK-LABEL: getsi0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsi0:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprwz r3, f0
+; CHECK-LE-NEXT:    extsw r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 0
   ret i32 %vecext
-; CHECK-LABEL: @getsi0
-; CHECK: xxsldwi vs0, v2, v2, 3
-; CHECK: mffprwz r3, f0
-; CHECK: extsw r3, r3
-; CHECK-LE-LABEL: @getsi0
-; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: mffprwz r3, f0
-; CHECK-LE: extsw r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi1(<4 x i32> %vsi) {
+; CHECK-LABEL: getsi1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrwz r3, v2
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsi1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-LE-NEXT:    mffprwz r3, f0
+; CHECK-LE-NEXT:    extsw r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 1
   ret i32 %vecext
-; CHECK-LABEL: @getsi1
-; CHECK: mfvsrwz r3, v2
-; CHECK: extsw r3, r3
-; CHECK-LE-LABEL: @getsi1
-; CHECK-LE: xxsldwi vs0, v2, v2, 1
-; CHECK-LE: mffprwz r3, f0
-; CHECK-LE: extsw r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi2(<4 x i32> %vsi) {
+; CHECK-LABEL: getsi2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsi2:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrwz r3, v2
+; CHECK-LE-NEXT:    extsw r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 2
   ret i32 %vecext
-; CHECK-LABEL: @getsi2
-; CHECK: xxsldwi vs0, v2, v2, 1
-; CHECK: mffprwz r3, f0
-; CHECK: extsw r3, r3
-; CHECK-LE-LABEL: @getsi2
-; CHECK-LE: mfvsrwz r3, v2
-; CHECK-LE: extsw r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getsi3(<4 x i32> %vsi) {
+; CHECK-LABEL: getsi3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsi3:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-LE-NEXT:    mffprwz r3, f0
+; CHECK-LE-NEXT:    extsw r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 3
   ret i32 %vecext
-; CHECK-LABEL: @getsi3
-; CHECK: xxswapd vs0, v2
-; CHECK: mffprwz r3, f0
-; CHECK: extsw r3, r3
-; CHECK-LE-LABEL: @getsi3
-; CHECK-LE: xxsldwi vs0, v2, v2, 3
-; CHECK-LE: mffprwz r3, f0
-; CHECK-LE: extsw r3, r3
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui0(<4 x i32> %vui) {
+; CHECK-LABEL: getui0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getui0:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprwz r3, f0
+; CHECK-LE-NEXT:    clrldi r3, r3, 32
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 0
   ret i32 %vecext
-; CHECK-LABEL: @getui0
-; CHECK: xxsldwi vs0, v2, v2, 3
-; CHECK: mffprwz r3, f0
-; CHECK-LE-LABEL: @getui0
-; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: mffprwz r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui1(<4 x i32> %vui) {
+; CHECK-LABEL: getui1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrwz r3, v2
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getui1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-LE-NEXT:    mffprwz r3, f0
+; CHECK-LE-NEXT:    clrldi r3, r3, 32
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 1
   ret i32 %vecext
-; CHECK-LABEL: @getui1
-; CHECK: mfvsrwz r3, v2
-; CHECK-LE-LABEL: @getui1
-; CHECK-LE: xxsldwi vs0, v2, v2, 1
-; CHECK-LE: mffprwz r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui2(<4 x i32> %vui) {
+; CHECK-LABEL: getui2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getui2:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrwz r3, v2
+; CHECK-LE-NEXT:    clrldi r3, r3, 32
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 2
   ret i32 %vecext
-; CHECK-LABEL: @getui2
-; CHECK: xxsldwi vs0, v2, v2, 1
-; CHECK: mffprwz r3, f0
-; CHECK-LE-LABEL: @getui2
-; CHECK-LE: mfvsrwz r3, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getui3(<4 x i32> %vui) {
+; CHECK-LABEL: getui3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprwz r3, f0
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getui3:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-LE-NEXT:    mffprwz r3, f0
+; CHECK-LE-NEXT:    clrldi r3, r3, 32
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 3
   ret i32 %vecext
-; CHECK-LABEL: @getui3
-; CHECK: xxswapd vs0, v2
-; CHECK: mffprwz r3, f0
-; CHECK-LE-LABEL: @getui3
-; CHECK-LE: xxsldwi vs0, v2, v2, 3
-; CHECK-LE: mffprwz r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) {
+; CHECK-LABEL: getvelsi:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi. r4, r5, 2
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    sldi r4, r4, 2
+; CHECK-NEXT:    andc r3, r3, r5
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    sldi r3, r3, 5
+; CHECK-NEXT:    vperm v2, v2, v2, v3
+; CHECK-NEXT:    mfvsrd r4, v2
+; CHECK-NEXT:    srd r3, r4, r3
+; CHECK-NEXT:    extsw r3, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getvelsi:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    li r3, 2
+; CHECK-LE-NEXT:    andc r3, r3, r5
+; CHECK-LE-NEXT:    sldi r3, r3, 2
+; CHECK-LE-NEXT:    lvsl v3, 0, r3
+; CHECK-LE-NEXT:    li r3, 1
+; CHECK-LE-NEXT:    and r3, r3, r5
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    sldi r3, r3, 5
+; CHECK-LE-NEXT:    mfvsrd r4, v2
+; CHECK-LE-NEXT:    srd r3, r4, r3
+; CHECK-LE-NEXT:    extsw r3, r3
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vsi, i32 %i
   ret i32 %vecext
-; CHECK-LABEL: @getvelsi
-; CHECK-LE-LABEL: @getvelsi
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i32 @getvelui(<4 x i32> %vui, i32 signext %i) {
+; CHECK-LABEL: getvelui:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi. r4, r5, 2
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    sldi r4, r4, 2
+; CHECK-NEXT:    andc r3, r3, r5
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    sldi r3, r3, 5
+; CHECK-NEXT:    vperm v2, v2, v2, v3
+; CHECK-NEXT:    mfvsrd r4, v2
+; CHECK-NEXT:    srd r3, r4, r3
+; CHECK-NEXT:    clrldi r3, r3, 32
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getvelui:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    li r3, 2
+; CHECK-LE-NEXT:    andc r3, r3, r5
+; CHECK-LE-NEXT:    sldi r3, r3, 2
+; CHECK-LE-NEXT:    lvsl v3, 0, r3
+; CHECK-LE-NEXT:    li r3, 1
+; CHECK-LE-NEXT:    and r3, r3, r5
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    sldi r3, r3, 5
+; CHECK-LE-NEXT:    mfvsrd r4, v2
+; CHECK-LE-NEXT:    srd r3, r4, r3
+; CHECK-LE-NEXT:    clrldi r3, r3, 32
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x i32> %vui, i32 %i
   ret i32 %vecext
-; CHECK-LABEL: @getvelui
-; CHECK-LE-LABEL: @getvelui
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getsl0(<2 x i64> %vsl) {
+; CHECK-LABEL: getsl0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsl0:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <2 x i64> %vsl, i32 0
   ret i64 %vecext
-; CHECK-LABEL: @getsl0
-; CHECK: mfvsrd r3, v2
-; CHECK-LE-LABEL: @getsl0
-; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: mffprd r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getsl1(<2 x i64> %vsl) {
+; CHECK-LABEL: getsl1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getsl1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <2 x i64> %vsl, i32 1
   ret i64 %vecext
-; CHECK-LABEL: @getsl1
-; CHECK: xxswapd vs0, v2
-; CHECK: mffprd r3, f0
-; CHECK-LE-LABEL: @getsl1
-; CHECK-LE: mfvsrd r3, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getul0(<2 x i64> %vul) {
+; CHECK-LABEL: getul0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getul0:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    mffprd r3, f0
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <2 x i64> %vul, i32 0
   ret i64 %vecext
-; CHECK-LABEL: @getul0
-; CHECK: mfvsrd r3, v2
-; CHECK-LE-LABEL: @getul0
-; CHECK-LE: xxswapd  vs0, v2
-; CHECK-LE: mffprd r3, f0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getul1(<2 x i64> %vul) {
+; CHECK-LABEL: getul1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    mffprd r3, f0
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getul1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <2 x i64> %vul, i32 1
   ret i64 %vecext
-; CHECK-LABEL: @getul1
-; CHECK: xxswapd vs0, v2
-; CHECK: mffprd r3, f0
-; CHECK-LE-LABEL: @getul1
-; CHECK-LE: mfvsrd r3, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
+; CHECK-LABEL: getvelsl:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi. r3, r5, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    lvsl v3, 0, r3
+; CHECK-NEXT:    vperm v2, v2, v2, v3
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getvelsl:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    li r3, 1
+; CHECK-LE-NEXT:    andc r3, r3, r5
+; CHECK-LE-NEXT:    sldi r3, r3, 3
+; CHECK-LE-NEXT:    lvsl v3, 0, r3
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <2 x i64> %vsl, i32 %i
   ret i64 %vecext
-; CHECK-LABEL: @getvelsl
-; CHECK-LE-LABEL: @getvelsl
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getvelul(<2 x i64> %vul, i32 signext %i) {
+; CHECK-LABEL: getvelul:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi. r3, r5, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    lvsl v3, 0, r3
+; CHECK-NEXT:    vperm v2, v2, v2, v3
+; CHECK-NEXT:    mfvsrd r3, v2
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getvelul:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    li r3, 1
+; CHECK-LE-NEXT:    andc r3, r3, r5
+; CHECK-LE-NEXT:    sldi r3, r3, 3
+; CHECK-LE-NEXT:    lvsl v3, 0, r3
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    mfvsrd r3, v2
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <2 x i64> %vul, i32 %i
   ret i64 %vecext
-; CHECK-LABEL: @getvelul
-; CHECK-LE-LABEL: @getvelul
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getf0(<4 x float> %vf) {
+; CHECK-LABEL: getf0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xscvspdpn f1, v2
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getf0:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-LE-NEXT:    xscvspdpn f1, vs0
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x float> %vf, i32 0
   ret float %vecext
-; CHECK-LABEL: @getf0
-; CHECK: xscvspdpn f1, v2
-; CHECK-LE-LABEL: @getf0
-; CHECK-LE: xxsldwi vs0, v2, v2, 3
-; CHECK-LE: xscvspdpn f1, vs0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getf1(<4 x float> %vf) {
+; CHECK-LABEL: getf1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-NEXT:    xscvspdpn f1, vs0
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getf1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs0, v2
+; CHECK-LE-NEXT:    xscvspdpn f1, vs0
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x float> %vf, i32 1
   ret float %vecext
-; CHECK-LABEL: @getf1
-; CHECK: xxsldwi vs0, v2, v2, 1
-; CHECK: xscvspdpn f1, vs0
-; CHECK-LE-LABEL: @getf1
-; CHECK-LE: xxswapd vs0, v2
-; CHECK-LE: xscvspdpn f1, vs0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getf2(<4 x float> %vf) {
+; CHECK-LABEL: getf2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs0, v2
+; CHECK-NEXT:    xscvspdpn f1, vs0
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getf2:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxsldwi vs0, v2, v2, 1
+; CHECK-LE-NEXT:    xscvspdpn f1, vs0
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x float> %vf, i32 2
   ret float %vecext
-; CHECK-LABEL: @getf2
-; CHECK: xxswapd vs0, v2
-; CHECK: xscvspdpn f1, vs0
-; CHECK-LE-LABEL: @getf2
-; CHECK-LE: xxsldwi vs0, v2, v2, 1
-; CHECK-LE: xscvspdpn f1, vs0
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getf3(<4 x float> %vf) {
+; CHECK-LABEL: getf3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-NEXT:    xscvspdpn f1, vs0
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getf3:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xscvspdpn f1, v2
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x float> %vf, i32 3
   ret float %vecext
-; CHECK-LABEL: @getf3
-; CHECK: xxsldwi vs0, v2, v2, 3
-; CHECK: xscvspdpn f1, vs0
-; CHECK-LE-LABEL: @getf3
-; CHECK-LE: xscvspdpn f1, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @getvelf(<4 x float> %vf, i32 signext %i) {
+; CHECK-LABEL: getvelf:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sldi r3, r5, 2
+; CHECK-NEXT:    lvsl v3, 0, r3
+; CHECK-NEXT:    vperm v2, v2, v2, v3
+; CHECK-NEXT:    xscvspdpn f1, v2
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getvelf:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xori r3, r5, 3
+; CHECK-LE-NEXT:    sldi r3, r3, 2
+; CHECK-LE-NEXT:    lvsl v3, 0, r3
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    xscvspdpn f1, v2
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <4 x float> %vf, i32 %i
   ret float %vecext
-; CHECK-LABEL: @getvelf
-; CHECK-LE-LABEL: @getvelf
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @getd0(<2 x double> %vd) {
+; CHECK-LABEL: getd0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxlor f1, v2, v2
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getd0:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxswapd vs1, v2
+; CHECK-LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <2 x double> %vd, i32 0
   ret double %vecext
-; CHECK-LABEL: @getd0
-; CHECK: xxlor f1, v2, v2
-; CHECK-LE-LABEL: @getd0
-; CHECK-LE: xxswapd vs1, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @getd1(<2 x double> %vd) {
+; CHECK-LABEL: getd1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxswapd vs1, v2
+; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getd1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xxlor f1, v2, v2
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <2 x double> %vd, i32 1
   ret double %vecext
-; CHECK-LABEL: @getd1
-; CHECK: xxswapd vs1, v2
-; CHECK-LE-LABEL: @getd1
-; CHECK-LE: xxlor f1, v2, v2
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @getveld(<2 x double> %vd, i32 signext %i) {
+; CHECK-LABEL: getveld:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi. r3, r5, 1
+; CHECK-NEXT:    sldi r3, r3, 3
+; CHECK-NEXT:    lvsl v3, 0, r3
+; CHECK-NEXT:    vperm v2, v2, v2, v3
+; CHECK-NEXT:    xxlor vs1, v2, v2
+; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
+; CHECK-NEXT:    blr
+;
+; CHECK-LE-LABEL: getveld:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    li r3, 1
+; CHECK-LE-NEXT:    andc r3, r3, r5
+; CHECK-LE-NEXT:    sldi r3, r3, 3
+; CHECK-LE-NEXT:    lvsl v3, 0, r3
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    xxlor vs1, v2, v2
+; CHECK-LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
+; CHECK-LE-NEXT:    blr
 entry:
   %vecext = extractelement <2 x double> %vd, i32 %i
   ret double %vecext
-; CHECK-LABEL: @getveld
-; CHECK-LE-LABEL: @getveld
 ; FIXME: add check patterns when variable element extraction is implemented
 }

llvm/test/CodeGen/PowerPC/pr25080.ll

 ; BE-NEXT:    lxvw4x 0, 0, 3
 ; BE-NEXT:    xxland 35, 35, 0
 ; BE-NEXT:    xxland 34, 34, 0
 ; BE-NEXT:    vcmpequw 3, 3, 4
 ; BE-NEXT:    vcmpequw 2, 2, 4
 ; BE-NEXT:    xxswapd 0, 35
 ; BE-NEXT:    mfvsrwz 3, 35
 ; BE-NEXT:    xxsldwi 1, 35, 35, 1
-; BE-NEXT:    sldi 3, 3, 48
-; BE-NEXT:    mffprwz 4, 0
-; BE-NEXT:    xxsldwi 0, 35, 35, 3
-; BE-NEXT:    mtvsrd 36, 3
-; BE-NEXT:    mffprwz 3, 1
-; BE-NEXT:    sldi 4, 4, 48
-; BE-NEXT:    xxswapd 1, 34
-; BE-NEXT:    mtvsrd 35, 4
 ; BE-NEXT:    mfvsrwz 4, 34
-; BE-NEXT:    sldi 3, 3, 48
-; BE-NEXT:    mtvsrd 37, 3
-; BE-NEXT:    mffprwz 3, 0
-; BE-NEXT:    sldi 4, 4, 48
-; BE-NEXT:    xxsldwi 0, 34, 34, 1
-; BE-NEXT:    vmrghh 3, 5, 3
-; BE-NEXT:    mtvsrd 37, 4
-; BE-NEXT:    sldi 3, 3, 48
-; BE-NEXT:    mffprwz 4, 1
-; BE-NEXT:    xxsldwi 1, 34, 34, 3
-; BE-NEXT:    mtvsrd 34, 3
+; BE-NEXT:    mtvsrwz 36, 3
+; BE-NEXT:    xxsldwi 2, 35, 35, 3
 ; BE-NEXT:    mffprwz 3, 0
-; BE-NEXT:    sldi 4, 4, 48
-; BE-NEXT:    mtvsrd 32, 4
+; BE-NEXT:    xxswapd 0, 34
+; BE-NEXT:    mtvsrwz 35, 4
 ; BE-NEXT:    mffprwz 4, 1
-; BE-NEXT:    sldi 3, 3, 48
-; BE-NEXT:    mtvsrd 33, 3
-; BE-NEXT:    sldi 3, 4, 48
-; BE-NEXT:    vmrghh 2, 2, 4
-; BE-NEXT:    mtvsrd 36, 3
+; BE-NEXT:    xxsldwi 1, 34, 34, 1
+; BE-NEXT:    mtvsrwz 37, 3
 ; BE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
-; BE-NEXT:    vmrghh 0, 1, 0
 ; BE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
-; BE-NEXT:    vmrghh 4, 4, 5
+; BE-NEXT:    mtvsrwz 32, 4
+; BE-NEXT:    mffprwz 4, 0
+; BE-NEXT:    lxvw4x 33, 0, 3
+; BE-NEXT:    xxsldwi 0, 34, 34, 3
+; BE-NEXT:    mffprwz 3, 1
+; BE-NEXT:    mffprwz 5, 2
+; BE-NEXT:    vperm 2, 0, 5, 1
+; BE-NEXT:    mtvsrwz 37, 3
+; BE-NEXT:    mffprwz 3, 0
+; BE-NEXT:    mtvsrwz 38, 5
+; BE-NEXT:    mtvsrwz 39, 4
+; BE-NEXT:    mtvsrwz 32, 3
+; BE-NEXT:    addis 3, 2, .LCPI0_2@toc@ha
+; BE-NEXT:    vperm 4, 6, 4, 1
+; BE-NEXT:    addi 3, 3, .LCPI0_2@toc@l
+; BE-NEXT:    vperm 5, 5, 7, 1
 ; BE-NEXT:    lxvw4x 0, 0, 3
-; BE-NEXT:    vmrghw 2, 2, 3
-; BE-NEXT:    vmrghw 3, 4, 0
+; BE-NEXT:    vperm 3, 0, 3, 1
+; BE-NEXT:    vmrghw 2, 4, 2
+; BE-NEXT:    vmrghw 3, 3, 5
 ; BE-NEXT:    xxmrghd 34, 35, 34
 ; BE-NEXT:    vspltish 3, 15
 ; BE-NEXT:    xxlor 34, 34, 0
 ; BE-NEXT:    vslh 2, 2, 3
 ; BE-NEXT:    vsrah 2, 2, 3
 ; BE-NEXT:    blr
 entry:
   %0 = trunc <8 x i32> %a to <8 x i23>
   %1 = icmp eq <8 x i23> %0, zeroinitializer
   %2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
   %3 = sext <8 x i1> %2 to <8 x i16>
   ret <8 x i16> %3
 }

llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

 ; CHECK-NEXT:    vsubuwm v2, v3, v2
 ; CHECK-NEXT:    xxswapd vs0, v2
 ; CHECK-NEXT:    stxvx vs0, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; P9BE-LABEL: test32:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    add r5, r3, r4
-; P9BE-NEXT:    lfiwzx f0, r3, r4
+; P9BE-NEXT:    lxsiwzx v2, r3, r4
 ; P9BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; P9BE-NEXT:    xxlxor v3, v3, v3
-; P9BE-NEXT:    xxsldwi v2, f0, f0, 1
 ; P9BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
 ; P9BE-NEXT:    lxvx v4, 0, r3
 ; P9BE-NEXT:    li r3, 4
-; P9BE-NEXT:    lfiwzx f0, r5, r3
+; P9BE-NEXT:    lxsiwzx v5, r5, r3
 ; P9BE-NEXT:    vperm v2, v3, v2, v4
-; P9BE-NEXT:    xxsldwi v5, f0, f0, 1
 ; P9BE-NEXT:    vperm v3, v3, v5, v4
 ; P9BE-NEXT:    vspltisw v4, 8
 ; P9BE-NEXT:    vnegw v3, v3
 ; P9BE-NEXT:    vadduwm v4, v4, v4
 ; P9BE-NEXT:    vslw v3, v3, v4
 ; P9BE-NEXT:    vsubuwm v2, v3, v2
 ; P9BE-NEXT:    xxswapd vs0, v2
 ; P9BE-NEXT:    stxvx vs0, 0, r3

 ; CHECK-NEXT:    bgelr+ cr0
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-LABEL: test16:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 1
 ; P9BE-NEXT:    li r7, 16
 ; P9BE-NEXT:    add r6, r3, r4
-; P9BE-NEXT:    lxsihzx v4, r3, r4
-; P9BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; P9BE-NEXT:    lxsihzx v5, r3, r4
+; P9BE-NEXT:    addis r3, r2, .LCPI3_1@toc@ha
 ; P9BE-NEXT:    lxsihzx v2, r6, r7
+; P9BE-NEXT:    addis r6, r2, .LCPI3_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI3_1@toc@l
+; P9BE-NEXT:    addi r6, r6, .LCPI3_0@toc@l
+; P9BE-NEXT:    vsplth v5, v5, 3
+; P9BE-NEXT:    lxvx v3, 0, r6
 ; P9BE-NEXT:    li r6, 0
-; P9BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; P9BE-NEXT:    sldi r6, r6, 48
-; P9BE-NEXT:    vsplth v4, v4, 3
-; P9BE-NEXT:    mtvsrd v3, r6
 ; P9BE-NEXT:    vsplth v2, v2, 3
-; P9BE-NEXT:    vmrghh v4, v3, v4
-; P9BE-NEXT:    vmrghh v2, v3, v2
-; P9BE-NEXT:    vsplth v3, v3, 0
-; P9BE-NEXT:    vmrghw v3, v3, v4
+; P9BE-NEXT:    mtvsrwz v4, r6
+; P9BE-NEXT:    vperm v2, v4, v2, v3
+; P9BE-NEXT:    vperm v3, v4, v5, v3
+; P9BE-NEXT:    vsplth v4, v4, 3
+; P9BE-NEXT:    vmrghw v3, v4, v3
 ; P9BE-NEXT:    lxvx v4, 0, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vperm v2, v3, v2, v4
 ; P9BE-NEXT:    xxspltw v3, v2, 1
 ; P9BE-NEXT:    vadduwm v2, v2, v3
 ; P9BE-NEXT:    vextuwlx r3, r3, v2
 ; P9BE-NEXT:    cmpw r3, r5
 ; P9BE-NEXT:    bgelr+ cr0

 ; CHECK-NEXT:    cmpw r3, r5
 ; CHECK-NEXT:    bgelr+ cr0
 ; CHECK-NEXT:  # %bb.1: # %if.then
 ;
 ; P9BE-LABEL: test8:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    add r6, r3, r4
 ; P9BE-NEXT:    li r7, 8
-; P9BE-NEXT:    lxsibzx v4, r3, r4
-; P9BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; P9BE-NEXT:    lxsibzx v5, r3, r4
+; P9BE-NEXT:    addis r3, r2, .LCPI4_1@toc@ha
 ; P9BE-NEXT:    lxsibzx v2, r6, r7
+; P9BE-NEXT:    addis r6, r2, .LCPI4_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI4_1@toc@l
+; P9BE-NEXT:    addi r6, r6, .LCPI4_0@toc@l
+; P9BE-NEXT:    vspltb v5, v5, 7
+; P9BE-NEXT:    lxvx v3, 0, r6
 ; P9BE-NEXT:    li r6, 0
-; P9BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; P9BE-NEXT:    sldi r6, r6, 56
-; P9BE-NEXT:    vspltb v4, v4, 7
-; P9BE-NEXT:    mtvsrd v3, r6
 ; P9BE-NEXT:    vspltb v2, v2, 7
-; P9BE-NEXT:    vmrghb v4, v3, v4
-; P9BE-NEXT:    vmrghb v2, v3, v2
-; P9BE-NEXT:    vspltb v3, v3, 0
-; P9BE-NEXT:    vmrghh v4, v4, v3
-; P9BE-NEXT:    xxspltw v3, v3, 0
-; P9BE-NEXT:    vmrghw v2, v4, v2
-; P9BE-NEXT:    lxvx v4, 0, r3
+; P9BE-NEXT:    mtvsrwz v4, r6
+; P9BE-NEXT:    vperm v2, v4, v2, v3
+; P9BE-NEXT:    vperm v3, v4, v5, v3
+; P9BE-NEXT:    vspltb v4, v4, 7
+; P9BE-NEXT:    vmrghh v3, v3, v4
+; P9BE-NEXT:    xxspltw v4, v4, 0
+; P9BE-NEXT:    vmrghw v2, v3, v2
+; P9BE-NEXT:    lxvx v3, 0, r3
 ; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    vperm v2, v3, v2, v4
+; P9BE-NEXT:    vperm v2, v4, v2, v3
 ; P9BE-NEXT:    xxspltw v3, v2, 1
 ; P9BE-NEXT:    vadduwm v2, v2, v3
 ; P9BE-NEXT:    vextuwlx r3, r3, v2
 ; P9BE-NEXT:    cmpw r3, r5
 ; P9BE-NEXT:    bgelr+ cr0
 ; P9BE-NEXT:  # %bb.1: # %if.then
 entry:
   %idxprom = sext i32 %delta to i64

llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll

 ; P8LE-NEXT:    lxsiwzx v4, 0, r3
 ; P8LE-NEXT:    addi r4, r4, .LCPI0_0@toc@l
 ; P8LE-NEXT:    lvx v3, 0, r4
 ; P8LE-NEXT:    vperm v2, v2, v4, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test1:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    lfiwzx f0, 0, r3
-; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
-; P8BE-NEXT:    xxsldwi vs0, v2, vs0, 1
-; P8BE-NEXT:    xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT:    lxsiwzx v3, 0, r3
+; P8BE-NEXT:    vmrghw v4, v2, v3
+; P8BE-NEXT:    xxsldwi vs0, v2, v3, 1
+; P8BE-NEXT:    xxsldwi v2, v4, vs0, 3
 ; P8BE-NEXT:    blr
 entry:
   %0 = load i32, i32* %int32, align 4
   %vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
   ret <4 x i32> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly

 ; P8LE-NEXT:    lxsiwzx v4, 0, r3
 ; P8LE-NEXT:    lvx v3, 0, r4
 ; P8LE-NEXT:    vperm v2, v2, v4, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test2:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4
-; P8BE-NEXT:    lfiwzx f0, 0, r3
-; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
-; P8BE-NEXT:    xxsldwi vs0, v2, vs0, 1
-; P8BE-NEXT:    xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT:    lxsiwzx v3, 0, r3
+; P8BE-NEXT:    vmrghw v4, v2, v3
+; P8BE-NEXT:    xxsldwi vs0, v2, v3, 1
+; P8BE-NEXT:    xxsldwi v2, v4, vs0, 3
 ; P8BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
   %0 = load i32, i32* %arrayidx, align 4
   %vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
   ret <4 x i32> %vecins
 }
 

 ; P8LE-NEXT:    lxsiwzx v3, r3, r5
 ; P8LE-NEXT:    lvx v4, 0, r4
 ; P8LE-NEXT:    vperm v2, v2, v3, v4
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test3:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r7, 2
-; P8BE-NEXT:    lfiwzx f0, r3, r4
-; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
-; P8BE-NEXT:    xxsldwi vs0, v2, vs0, 1
-; P8BE-NEXT:    xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT:    lxsiwzx v3, r3, r4
+; P8BE-NEXT:    vmrghw v4, v2, v3
+; P8BE-NEXT:    xxsldwi vs0, v2, v3, 1
+; P8BE-NEXT:    xxsldwi v2, v4, vs0, 3
 ; P8BE-NEXT:    blr
 entry:
   %idxprom = sext i32 %Idx to i64
   %arrayidx = getelementptr inbounds i32, i32* %int32, i64 %idxprom
   %0 = load i32, i32* %arrayidx, align 4
   %vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
   ret <4 x i32> %vecins
 }

 ; P8LE-NEXT:    lxsiwzx v4, 0, r3
 ; P8LE-NEXT:    lvx v3, 0, r4
 ; P8LE-NEXT:    vperm v2, v2, v4, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test4:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4
-; P8BE-NEXT:    lfiwzx f0, 0, r3
-; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
-; P8BE-NEXT:    xxsldwi vs0, v2, vs0, 1
-; P8BE-NEXT:    xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT:    lxsiwzx v3, 0, r3
+; P8BE-NEXT:    vmrghw v4, v2, v3
+; P8BE-NEXT:    xxsldwi vs0, v2, v3, 1
+; P8BE-NEXT:    xxsldwi v2, v4, vs0, 3
 ; P8BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds i32, i32* %int32, i64 1
   %0 = load i32, i32* %arrayidx, align 4
   %vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
   ret <4 x i32> %vecins
 }
 

 ; P8LE-NEXT:    lxsiwzx v4, 0, r5
 ; P8LE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
 ; P8LE-NEXT:    lvx v3, 0, r3
 ; P8LE-NEXT:    vperm v2, v2, v4, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test5:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    lfiwzx f0, 0, r5
-; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
-; P8BE-NEXT:    xxsldwi vs0, v2, vs0, 1
-; P8BE-NEXT:    xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT:    lxsiwzx v3, 0, r5
+; P8BE-NEXT:    vmrghw v4, v2, v3
+; P8BE-NEXT:    xxsldwi vs0, v2, v3, 1
+; P8BE-NEXT:    xxsldwi v2, v4, vs0, 3
 ; P8BE-NEXT:    blr
 entry:
   %0 = load i32, i32* %ptr1, align 4
   %vecins = insertelement <4 x i32> %vec, i32 %0, i32 0
   ret <4 x i32> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly

 ; P8LE-NEXT:    lxsiwzx v4, 0, r3
 ; P8LE-NEXT:    addi r4, r4, .LCPI5_0@toc@l
 ; P8LE-NEXT:    lvx v3, 0, r4
 ; P8LE-NEXT:    vperm v2, v2, v4, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test_f1:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    lfiwzx f0, 0, r3
-; P8BE-NEXT:    xxsldwi vs0, f0, f0, 1
-; P8BE-NEXT:    xxsldwi vs0, v2, vs0, 1
-; P8BE-NEXT:    xxsldwi v2, vs0, vs0, 3
+; P8BE-NEXT:    lxsiwzx v3, 0, r3
+; P8BE-NEXT:    vmrghw v4, v2, v3
+; P8BE-NEXT:    xxsldwi vs0, v2, v3, 1
+; P8BE-NEXT:    xxsldwi v2, v4, vs0, 3
 ; P8BE-NEXT:    blr
 entry:
   %0 = load float, float* %f64, align 4
   %vecins = insertelement <4 x float> %vec, float %0, i32 0
   ret <4 x float> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x float> @s2v_test_f2(float* nocapture readonly %f64, <2 x float> %vec)  {
 ; P9LE-LABEL: s2v_test_f2:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    addi r3, r3, 4
 ; P9LE-NEXT:    vmrglw v2, v2, v2
 ; P9LE-NEXT:    lxsiwzx v3, 0, r3
 ; P9LE-NEXT:    vmrghw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: s2v_test_f2:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    addi r3, r3, 4
-; P9BE-NEXT:    xxspltw v2, v2, 1
-; P9BE-NEXT:    lfiwzx f0, 0, r3
-; P9BE-NEXT:    xxsldwi v3, f0, f0, 1
-; P9BE-NEXT:    vmrghw v2, v3, v2
+; P9BE-NEXT:    lxsiwzx v3, 0, r3
+; P9BE-NEXT:    vmrgow v2, v3, v2
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test_f2:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    vmrglw v2, v2, v2
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    lxsiwzx v3, 0, r3
 ; P8LE-NEXT:    vmrghw v2, v2, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test_f2:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4
-; P8BE-NEXT:    xxspltw v2, v2, 1
-; P8BE-NEXT:    lfiwzx f0, 0, r3
-; P8BE-NEXT:    xxsldwi v3, f0, f0, 1
-; P8BE-NEXT:    vmrghw v2, v3, v2
+; P8BE-NEXT:    lxsiwzx v3, 0, r3
+; P8BE-NEXT:    vmrgow v2, v3, v2
 ; P8BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %f64, i64 1
   %0 = load float, float* %arrayidx, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x float> @s2v_test_f3(float* nocapture readonly %f64, <2 x float> %vec, i32 signext %Idx)  {
 ; P9LE-LABEL: s2v_test_f3:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r7, 2
 ; P9LE-NEXT:    vmrglw v2, v2, v2
 ; P9LE-NEXT:    lxsiwzx v3, r3, r4
 ; P9LE-NEXT:    vmrghw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: s2v_test_f3:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r7, 2
-; P9BE-NEXT:    xxspltw v2, v2, 1
-; P9BE-NEXT:    lfiwzx f0, r3, r4
-; P9BE-NEXT:    xxsldwi v3, f0, f0, 1
-; P9BE-NEXT:    vmrghw v2, v3, v2
+; P9BE-NEXT:    lxsiwzx v3, r3, r4
+; P9BE-NEXT:    vmrgow v2, v3, v2
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test_f3:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    vmrglw v2, v2, v2
 ; P8LE-NEXT:    sldi r4, r7, 2
 ; P8LE-NEXT:    lxsiwzx v3, r3, r4
 ; P8LE-NEXT:    vmrghw v2, v2, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test_f3:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r7, 2
-; P8BE-NEXT:    xxspltw v2, v2, 1
-; P8BE-NEXT:    lfiwzx f0, r3, r4
-; P8BE-NEXT:    xxsldwi v3, f0, f0, 1
-; P8BE-NEXT:    vmrghw v2, v3, v2
+; P8BE-NEXT:    lxsiwzx v3, r3, r4
+; P8BE-NEXT:    vmrgow v2, v3, v2
 ; P8BE-NEXT:    blr
 entry:
   %idxprom = sext i32 %Idx to i64
   %arrayidx = getelementptr inbounds float, float* %f64, i64 %idxprom
   %0 = load float, float* %arrayidx, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x float> @s2v_test_f4(float* nocapture readonly %f64, <2 x float> %vec)  {
 ; P9LE-LABEL: s2v_test_f4:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    addi r3, r3, 4
 ; P9LE-NEXT:    vmrglw v2, v2, v2
 ; P9LE-NEXT:    lxsiwzx v3, 0, r3
 ; P9LE-NEXT:    vmrghw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: s2v_test_f4:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    addi r3, r3, 4
-; P9BE-NEXT:    xxspltw v2, v2, 1
-; P9BE-NEXT:    lfiwzx f0, 0, r3
-; P9BE-NEXT:    xxsldwi v3, f0, f0, 1
-; P9BE-NEXT:    vmrghw v2, v3, v2
+; P9BE-NEXT:    lxsiwzx v3, 0, r3
+; P9BE-NEXT:    vmrgow v2, v3, v2
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test_f4:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    vmrglw v2, v2, v2
 ; P8LE-NEXT:    addi r3, r3, 4
 ; P8LE-NEXT:    lxsiwzx v3, 0, r3
 ; P8LE-NEXT:    vmrghw v2, v2, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test_f4:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addi r3, r3, 4
-; P8BE-NEXT:    xxspltw v2, v2, 1
-; P8BE-NEXT:    lfiwzx f0, 0, r3
-; P8BE-NEXT:    xxsldwi v3, f0, f0, 1
-; P8BE-NEXT:    vmrghw v2, v3, v2
+; P8BE-NEXT:    lxsiwzx v3, 0, r3
+; P8BE-NEXT:    vmrgow v2, v3, v2
 ; P8BE-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds float, float* %f64, i64 1
   %0 = load float, float* %arrayidx, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define <2 x float> @s2v_test_f5(<2 x float> %vec, float* nocapture readonly %ptr1)  {
 ; P9LE-LABEL: s2v_test_f5:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxsiwzx v3, 0, r5
 ; P9LE-NEXT:    vmrglw v2, v2, v2
 ; P9LE-NEXT:    vmrghw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: s2v_test_f5:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    lfiwzx f0, 0, r5
-; P9BE-NEXT:    xxspltw v2, v2, 1
-; P9BE-NEXT:    xxsldwi v3, f0, f0, 1
-; P9BE-NEXT:    vmrghw v2, v3, v2
+; P9BE-NEXT:    lxsiwzx v3, 0, r5
+; P9BE-NEXT:    vmrgow v2, v3, v2
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: s2v_test_f5:
 ; P8LE:       # %bb.0: # %entry
 ; P8LE-NEXT:    vmrglw v2, v2, v2
 ; P8LE-NEXT:    lxsiwzx v3, 0, r5
 ; P8LE-NEXT:    vmrghw v2, v2, v3
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: s2v_test_f5:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    lfiwzx f0, 0, r5
-; P8BE-NEXT:    xxspltw v2, v2, 1
-; P8BE-NEXT:    xxsldwi v3, f0, f0, 1
-; P8BE-NEXT:    vmrghw v2, v3, v2
+; P8BE-NEXT:    lxsiwzx v3, 0, r5
+; P8BE-NEXT:    vmrgow v2, v3, v2
 ; P8BE-NEXT:    blr
 entry:
   %0 = load float, float* %ptr1, align 8
   %vecins = insertelement <2 x float> %vec, float %0, i32 0
   ret <2 x float> %vecins
 }
 

llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll

 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    sub r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, -124
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -21386
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    ori r4, r4, 37253
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 0
+; P9BE-NEXT:    ori r4, r4, 37253
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -16728
-; P9BE-NEXT:    sldi r3, r3, 48
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; P9BE-NEXT:    ori r4, r4, 63249
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    extsh r3, r3
+; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 8
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, -1003
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 21399
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    ori r4, r4, 33437
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 4
+; P9BE-NEXT:    ori r4, r4, 33437
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 5
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 98
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
-; P9BE-NEXT:    vmrghh v2, v2, v4
+; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    vperm v2, v2, v4, v5
 ; P9BE-NEXT:    vmrghw v2, v3, v2
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_srem_vec_1:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 21399
 ; P8LE-NEXT:    lis r8, -16728

 ; P8BE-NEXT:    add r9, r9, r11
 ; P8BE-NEXT:    srwi r11, r10, 31
 ; P8BE-NEXT:    srawi r10, r10, 6
 ; P8BE-NEXT:    mulli r8, r8, 98
 ; P8BE-NEXT:    add r10, r10, r11
 ; P8BE-NEXT:    mulli r9, r9, -124
 ; P8BE-NEXT:    mulli r10, r10, 95
 ; P8BE-NEXT:    sub r3, r5, r3
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    sub r5, r6, r8
-; P8BE-NEXT:    mtvsrd v2, r3
-; P8BE-NEXT:    sub r6, r7, r9
-; P8BE-NEXT:    sldi r3, r5, 48
+; P8BE-NEXT:    addis r5, r2, .LCPI0_0@toc@ha
+; P8BE-NEXT:    mtvsrwz v2, r3
+; P8BE-NEXT:    addi r3, r5, .LCPI0_0@toc@l
+; P8BE-NEXT:    sub r6, r6, r8
+; P8BE-NEXT:    lxvw4x v3, 0, r3
+; P8BE-NEXT:    sub r3, r7, r9
+; P8BE-NEXT:    mtvsrwz v4, r6
 ; P8BE-NEXT:    sub r4, r4, r10
-; P8BE-NEXT:    mtvsrd v3, r3
-; P8BE-NEXT:    sldi r3, r6, 48
-; P8BE-NEXT:    sldi r4, r4, 48
-; P8BE-NEXT:    mtvsrd v4, r3
-; P8BE-NEXT:    mtvsrd v5, r4
-; P8BE-NEXT:    vmrghh v2, v3, v2
-; P8BE-NEXT:    vmrghh v3, v5, v4
+; P8BE-NEXT:    mtvsrwz v5, r3
+; P8BE-NEXT:    mtvsrwz v0, r4
+; P8BE-NEXT:    vperm v2, v4, v2, v3
+; P8BE-NEXT:    vperm v3, v0, v5, v3
 ; P8BE-NEXT:    vmrghw v2, v3, v2
 ; P8BE-NEXT:    blr
   %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
   ret <4 x i16> %1
 }
 
 define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P9LE-LABEL: fold_srem_vec_2:

 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    extsh r3, r3
+; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
-; P9BE-NEXT:    vmrghh v2, v2, v4
+; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    vperm v2, v2, v4, v5
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_srem_vec_2:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -21386
 ; P8LE-NEXT:    ori r3, r3, 37253

 ; P8BE-NEXT:    srwi r11, r10, 31
 ; P8BE-NEXT:    srawi r10, r10, 6
 ; P8BE-NEXT:    mulli r9, r9, 95
 ; P8BE-NEXT:    add r10, r10, r11
 ; P8BE-NEXT:    srwi r11, r3, 31
 ; P8BE-NEXT:    srawi r3, r3, 6
 ; P8BE-NEXT:    mulli r10, r10, 95
 ; P8BE-NEXT:    sub r5, r5, r8
+; P8BE-NEXT:    addis r8, r2, .LCPI1_0@toc@ha
 ; P8BE-NEXT:    add r3, r3, r11
-; P8BE-NEXT:    sldi r5, r5, 48
+; P8BE-NEXT:    mtvsrwz v2, r5
+; P8BE-NEXT:    addi r5, r8, .LCPI1_0@toc@l
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    sub r6, r6, r9
-; P8BE-NEXT:    mtvsrd v2, r5
-; P8BE-NEXT:    sldi r6, r6, 48
-; P8BE-NEXT:    sub r7, r7, r10
-; P8BE-NEXT:    mtvsrd v3, r6
+; P8BE-NEXT:    lxvw4x v3, 0, r5
+; P8BE-NEXT:    mtvsrwz v4, r6
+; P8BE-NEXT:    sub r5, r7, r10
+; P8BE-NEXT:    mtvsrwz v5, r5
 ; P8BE-NEXT:    sub r3, r4, r3
-; P8BE-NEXT:    sldi r4, r7, 48
-; P8BE-NEXT:    vmrghh v2, v3, v2
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    mtvsrd v4, r4
-; P8BE-NEXT:    mtvsrd v5, r3
-; P8BE-NEXT:    vmrghh v3, v5, v4
+; P8BE-NEXT:    vperm v2, v4, v2, v3
+; P8BE-NEXT:    mtvsrwz v0, r3
+; P8BE-NEXT:    vperm v3, v0, v5, v3
 ; P8BE-NEXT:    vmrghw v2, v3, v2
 ; P8BE-NEXT:    blr
   %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   ret <4 x i16> %1
 }
 
 
 ; Don't fold if we can combine srem with sdiv.

 ; P9BE-NEXT:    extsh r4, r3
 ; P9BE-NEXT:    mulhw r6, r4, r5
 ; P9BE-NEXT:    add r4, r6, r4
 ; P9BE-NEXT:    srwi r6, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r6
 ; P9BE-NEXT:    mulli r6, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r6
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r6, r3
 ; P9BE-NEXT:    mulhw r7, r6, r5
 ; P9BE-NEXT:    add r6, r7, r6
 ; P9BE-NEXT:    srwi r7, r6, 31
 ; P9BE-NEXT:    srawi r6, r6, 6
 ; P9BE-NEXT:    add r6, r6, r7
 ; P9BE-NEXT:    mulli r7, r6, 95
 ; P9BE-NEXT:    sub r3, r3, r7
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    extsh r7, r3
+; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mulhw r8, r7, r5
 ; P9BE-NEXT:    add r7, r8, r7
 ; P9BE-NEXT:    srwi r8, r7, 31
 ; P9BE-NEXT:    srawi r7, r7, 6
 ; P9BE-NEXT:    add r7, r7, r8
 ; P9BE-NEXT:    mulli r8, r7, 95
 ; P9BE-NEXT:    sub r3, r3, r8
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r5
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r8, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r8
 ; P9BE-NEXT:    mulli r8, r5, 95
+; P9BE-NEXT:    mtvsrwz v0, r5
 ; P9BE-NEXT:    sub r3, r3, r8
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
-; P9BE-NEXT:    sldi r3, r4, 48
-; P9BE-NEXT:    vmrghh v2, v2, v4
+; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    vperm v2, v2, v4, v5
+; P9BE-NEXT:    mtvsrwz v4, r6
 ; P9BE-NEXT:    vmrghw v2, v2, v3
-; P9BE-NEXT:    mtvsrd v3, r3
-; P9BE-NEXT:    sldi r3, r6, 48
-; P9BE-NEXT:    mtvsrd v4, r3
-; P9BE-NEXT:    sldi r3, r7, 48
-; P9BE-NEXT:    vmrghh v3, v4, v3
-; P9BE-NEXT:    mtvsrd v4, r3
-; P9BE-NEXT:    sldi r3, r5, 48
-; P9BE-NEXT:    mtvsrd v5, r3
-; P9BE-NEXT:    vmrghh v4, v5, v4
+; P9BE-NEXT:    mtvsrwz v3, r4
+; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    mtvsrwz v4, r7
+; P9BE-NEXT:    vperm v4, v0, v4, v5
 ; P9BE-NEXT:    vmrghw v3, v4, v3
 ; P9BE-NEXT:    vadduhm v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: combine_srem_sdiv:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -21386

 ; P8LE-NEXT:    vmrghh v4, v5, v4
 ; P8LE-NEXT:    vmrglw v3, v0, v3
 ; P8LE-NEXT:    vmrglw v2, v4, v2
 ; P8LE-NEXT:    vadduhm v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: combine_srem_sdiv:
 ; P8BE:       # %bb.0:
-; P8BE-NEXT:    mfvsrd r5, v2
-; P8BE-NEXT:    lis r4, -21386
-; P8BE-NEXT:    ori r4, r4, 37253
-; P8BE-NEXT:    clrldi r3, r5, 48
-; P8BE-NEXT:    rldicl r6, r5, 48, 48
-; P8BE-NEXT:    extsh r8, r3
-; P8BE-NEXT:    rldicl r7, r5, 32, 48
+; P8BE-NEXT:    mfvsrd r4, v2
+; P8BE-NEXT:    lis r3, -21386
+; P8BE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; P8BE-NEXT:    addis r30, r2, .LCPI2_0@toc@ha
+; P8BE-NEXT:    ori r3, r3, 37253
+; P8BE-NEXT:    clrldi r5, r4, 48
+; P8BE-NEXT:    rldicl r6, r4, 48, 48
+; P8BE-NEXT:    rldicl r7, r4, 32, 48
+; P8BE-NEXT:    extsh r8, r5
 ; P8BE-NEXT:    extsh r9, r6
-; P8BE-NEXT:    rldicl r5, r5, 16, 48
-; P8BE-NEXT:    mulhw r11, r8, r4
 ; P8BE-NEXT:    extsh r10, r7
-; P8BE-NEXT:    extsh r5, r5
-; P8BE-NEXT:    mulhw r12, r9, r4
-; P8BE-NEXT:    mulhw r0, r10, r4
-; P8BE-NEXT:    mulhw r4, r5, r4
+; P8BE-NEXT:    mulhw r11, r8, r3
+; P8BE-NEXT:    mulhw r12, r9, r3
+; P8BE-NEXT:    rldicl r4, r4, 16, 48
+; P8BE-NEXT:    mulhw r0, r10, r3
+; P8BE-NEXT:    extsh r4, r4
+; P8BE-NEXT:    mulhw r3, r4, r3
 ; P8BE-NEXT:    add r8, r11, r8
 ; P8BE-NEXT:    add r9, r12, r9
-; P8BE-NEXT:    srawi r11, r8, 6
-; P8BE-NEXT:    srwi r8, r8, 31
+; P8BE-NEXT:    srwi r11, r8, 31
 ; P8BE-NEXT:    add r10, r0, r10
-; P8BE-NEXT:    add r4, r4, r5
-; P8BE-NEXT:    add r8, r11, r8
+; P8BE-NEXT:    srawi r8, r8, 6
+; P8BE-NEXT:    addi r0, r30, .LCPI2_0@toc@l
+; P8BE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8BE-NEXT:    srawi r12, r9, 6
 ; P8BE-NEXT:    srwi r9, r9, 31
-; P8BE-NEXT:    srawi r0, r10, 6
-; P8BE-NEXT:    srawi r11, r4, 6
+; P8BE-NEXT:    add r8, r8, r11
+; P8BE-NEXT:    add r3, r3, r4
+; P8BE-NEXT:    lxvw4x v2, 0, r0
+; P8BE-NEXT:    srawi r11, r10, 6
 ; P8BE-NEXT:    srwi r10, r10, 31
 ; P8BE-NEXT:    add r9, r12, r9
-; P8BE-NEXT:    srwi r4, r4, 31
+; P8BE-NEXT:    mtvsrwz v3, r8
 ; P8BE-NEXT:    mulli r12, r8, 95
-; P8BE-NEXT:    add r10, r0, r10
-; P8BE-NEXT:    add r4, r11, r4
-; P8BE-NEXT:    mulli r0, r9, 95
-; P8BE-NEXT:    sldi r9, r9, 48
-; P8BE-NEXT:    sldi r8, r8, 48
-; P8BE-NEXT:    mtvsrd v3, r9
-; P8BE-NEXT:    mulli r9, r4, 95
-; P8BE-NEXT:    mtvsrd v2, r8
-; P8BE-NEXT:    mulli r8, r10, 95
-; P8BE-NEXT:    sldi r10, r10, 48
-; P8BE-NEXT:    sub r3, r3, r12
-; P8BE-NEXT:    mtvsrd v4, r10
-; P8BE-NEXT:    sub r6, r6, r0
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    vmrghh v2, v3, v2
-; P8BE-NEXT:    sldi r6, r6, 48
-; P8BE-NEXT:    mtvsrd v3, r3
-; P8BE-NEXT:    sub r3, r5, r9
-; P8BE-NEXT:    sub r7, r7, r8
-; P8BE-NEXT:    mtvsrd v5, r6
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    sldi r5, r7, 48
-; P8BE-NEXT:    mtvsrd v1, r3
-; P8BE-NEXT:    sldi r3, r4, 48
-; P8BE-NEXT:    mtvsrd v0, r5
-; P8BE-NEXT:    vmrghh v3, v5, v3
-; P8BE-NEXT:    mtvsrd v5, r3
-; P8BE-NEXT:    vmrghh v0, v1, v0
-; P8BE-NEXT:    vmrghh v4, v5, v4
-; P8BE-NEXT:    vmrghw v3, v0, v3
-; P8BE-NEXT:    vmrghw v2, v4, v2
-; P8BE-NEXT:    vadduhm v2, v3, v2
+; P8BE-NEXT:    add r10, r11, r10
+; P8BE-NEXT:    srwi r11, r3, 31
+; P8BE-NEXT:    mtvsrwz v4, r9
+; P8BE-NEXT:    srawi r3, r3, 6
+; P8BE-NEXT:    mulli r8, r9, 95
+; P8BE-NEXT:    mtvsrwz v5, r10
+; P8BE-NEXT:    add r3, r3, r11
+; P8BE-NEXT:    mulli r9, r10, 95
+; P8BE-NEXT:    vperm v3, v4, v3, v2
+; P8BE-NEXT:    mulli r10, r3, 95
+; P8BE-NEXT:    sub r5, r5, r12
+; P8BE-NEXT:    sub r6, r6, r8
+; P8BE-NEXT:    mtvsrwz v4, r5
+; P8BE-NEXT:    mtvsrwz v0, r6
+; P8BE-NEXT:    sub r5, r7, r9
+; P8BE-NEXT:    sub r4, r4, r10
+; P8BE-NEXT:    mtvsrwz v1, r5
+; P8BE-NEXT:    mtvsrwz v6, r4
+; P8BE-NEXT:    vperm v4, v0, v4, v2
+; P8BE-NEXT:    mtvsrwz v0, r3
+; P8BE-NEXT:    vperm v1, v6, v1, v2
+; P8BE-NEXT:    vperm v2, v0, v5, v2
+; P8BE-NEXT:    vmrghw v4, v1, v4
+; P8BE-NEXT:    vmrghw v2, v2, v3
+; P8BE-NEXT:    vadduhm v2, v4, v2
 ; P8BE-NEXT:    blr
   %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %3 = add <4 x i16> %1, %2
   ret <4 x i16> %3
 }
 
 ; Don't fold for divisors that are a power of two.

 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 5
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 5
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 6
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 6
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -21386
-; P9BE-NEXT:    sldi r3, r3, 48
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; P9BE-NEXT:    ori r4, r4, 37253
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    extsh r3, r3
+; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 3
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 3
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
-; P9BE-NEXT:    vmrghh v2, v2, v4
+; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    vperm v2, v2, v4, v5
 ; P9BE-NEXT:    vmrghw v2, v3, v2
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_srem_power_of_two:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -21386
 ; P8LE-NEXT:    ori r3, r3, 37253

 ; P8BE-NEXT:    extsh r4, r4
 ; P8BE-NEXT:    slwi r8, r8, 5
 ; P8BE-NEXT:    add r3, r3, r5
 ; P8BE-NEXT:    addze r9, r9
 ; P8BE-NEXT:    sub r6, r6, r8
 ; P8BE-NEXT:    srwi r10, r3, 31
 ; P8BE-NEXT:    srawi r3, r3, 6
 ; P8BE-NEXT:    slwi r8, r9, 6
+; P8BE-NEXT:    mtvsrwz v2, r6
 ; P8BE-NEXT:    add r3, r3, r10
 ; P8BE-NEXT:    srawi r9, r4, 3
-; P8BE-NEXT:    sub r7, r7, r8
+; P8BE-NEXT:    addis r10, r2, .LCPI3_0@toc@ha
+; P8BE-NEXT:    sub r6, r7, r8
 ; P8BE-NEXT:    mulli r3, r3, 95
-; P8BE-NEXT:    sldi r6, r6, 48
 ; P8BE-NEXT:    addze r8, r9
-; P8BE-NEXT:    mtvsrd v2, r6
-; P8BE-NEXT:    slwi r6, r8, 3
-; P8BE-NEXT:    sub r4, r4, r6
-; P8BE-NEXT:    sldi r4, r4, 48
+; P8BE-NEXT:    addi r7, r10, .LCPI3_0@toc@l
+; P8BE-NEXT:    mtvsrwz v4, r6
+; P8BE-NEXT:    lxvw4x v3, 0, r7
 ; P8BE-NEXT:    sub r3, r5, r3
-; P8BE-NEXT:    sldi r5, r7, 48
-; P8BE-NEXT:    mtvsrd v5, r4
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    mtvsrd v3, r5
-; P8BE-NEXT:    mtvsrd v4, r3
-; P8BE-NEXT:    vmrghh v2, v3, v2
-; P8BE-NEXT:    vmrghh v3, v5, v4
+; P8BE-NEXT:    slwi r5, r8, 3
+; P8BE-NEXT:    vperm v2, v4, v2, v3
+; P8BE-NEXT:    sub r4, r4, r5
+; P8BE-NEXT:    mtvsrwz v5, r3
+; P8BE-NEXT:    mtvsrwz v0, r4
+; P8BE-NEXT:    vperm v3, v0, v5, v3
 ; P8BE-NEXT:    vmrghw v2, v2, v3
 ; P8BE-NEXT:    blr
   %1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is one.
 define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {

 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 4
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 23
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 24749
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    ori r4, r4, 47143
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 6
+; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 5423
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -14230
-; P9BE-NEXT:    sldi r3, r3, 48
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; P9BE-NEXT:    ori r4, r4, 30865
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v3, v4
 ; P9BE-NEXT:    extsh r3, r3
+; P9BE-NEXT:    vperm v3, v3, v4, v5
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 9
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 654
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
+; P9BE-NEXT:    mtvsrwz v2, r3
 ; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
-; P9BE-NEXT:    vmrghh v2, v4, v2
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    vperm v2, v4, v2, v5
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_srem_one:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r5, 24749
 ; P8LE-NEXT:    lis r6, -19946

 ; P8LE-NEXT:    mtvsrd v5, r3
 ; P8LE-NEXT:    vmrghh v3, v3, v4
 ; P8LE-NEXT:    vmrghh v2, v5, v2
 ; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: dont_fold_srem_one:
 ; P8BE:       # %bb.0:
-; P8BE-NEXT:    mfvsrd r3, v2
-; P8BE-NEXT:    lis r5, 24749
-; P8BE-NEXT:    lis r6, -19946
+; P8BE-NEXT:    mfvsrd r4, v2
+; P8BE-NEXT:    lis r3, 24749
+; P8BE-NEXT:    lis r7, -19946
 ; P8BE-NEXT:    lis r8, -14230
-; P8BE-NEXT:    ori r5, r5, 47143
-; P8BE-NEXT:    ori r6, r6, 17097
+; P8BE-NEXT:    ori r3, r3, 47143
+; P8BE-NEXT:    ori r7, r7, 17097
 ; P8BE-NEXT:    ori r8, r8, 30865
-; P8BE-NEXT:    clrldi r4, r3, 48
-; P8BE-NEXT:    rldicl r7, r3, 48, 48
-; P8BE-NEXT:    rldicl r3, r3, 32, 48
+; P8BE-NEXT:    clrldi r5, r4, 48
+; P8BE-NEXT:    rldicl r6, r4, 48, 48
+; P8BE-NEXT:    rldicl r4, r4, 32, 48
+; P8BE-NEXT:    extsh r5, r5
+; P8BE-NEXT:    extsh r6, r6
 ; P8BE-NEXT:    extsh r4, r4
-; P8BE-NEXT:    extsh r7, r7
-; P8BE-NEXT:    extsh r3, r3
-; P8BE-NEXT:    mulhw r5, r4, r5
-; P8BE-NEXT:    mulhw r6, r7, r6
-; P8BE-NEXT:    mulhw r8, r3, r8
-; P8BE-NEXT:    srwi r9, r5, 31
-; P8BE-NEXT:    srawi r5, r5, 11
-; P8BE-NEXT:    add r6, r6, r7
-; P8BE-NEXT:    add r8, r8, r3
-; P8BE-NEXT:    add r5, r5, r9
-; P8BE-NEXT:    srwi r9, r6, 31
-; P8BE-NEXT:    srawi r6, r6, 4
-; P8BE-NEXT:    add r6, r6, r9
-; P8BE-NEXT:    srwi r9, r8, 31
-; P8BE-NEXT:    srawi r8, r8, 9
-; P8BE-NEXT:    mulli r5, r5, 5423
-; P8BE-NEXT:    add r8, r8, r9
-; P8BE-NEXT:    mulli r6, r6, 23
-; P8BE-NEXT:    li r9, 0
+; P8BE-NEXT:    mulhw r3, r5, r3
+; P8BE-NEXT:    mulhw r7, r6, r7
+; P8BE-NEXT:    mulhw r8, r4, r8
+; P8BE-NEXT:    srawi r9, r3, 11
+; P8BE-NEXT:    srwi r3, r3, 31
+; P8BE-NEXT:    add r7, r7, r6
+; P8BE-NEXT:    add r8, r8, r4
+; P8BE-NEXT:    add r3, r9, r3
+; P8BE-NEXT:    srwi r9, r7, 31
+; P8BE-NEXT:    srawi r7, r7, 4
+; P8BE-NEXT:    srawi r10, r8, 9
+; P8BE-NEXT:    srwi r8, r8, 31
+; P8BE-NEXT:    add r7, r7, r9
+; P8BE-NEXT:    addis r9, r2, .LCPI4_0@toc@ha
+; P8BE-NEXT:    mulli r3, r3, 5423
+; P8BE-NEXT:    add r8, r10, r8
+; P8BE-NEXT:    li r10, 0
+; P8BE-NEXT:    mulli r7, r7, 23
 ; P8BE-NEXT:    mulli r8, r8, 654
-; P8BE-NEXT:    sub r4, r4, r5
-; P8BE-NEXT:    sldi r5, r9, 48
-; P8BE-NEXT:    mtvsrd v2, r5
-; P8BE-NEXT:    sub r5, r7, r6
-; P8BE-NEXT:    sldi r4, r4, 48
-; P8BE-NEXT:    sub r3, r3, r8
-; P8BE-NEXT:    mtvsrd v3, r4
-; P8BE-NEXT:    sldi r4, r5, 48
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    mtvsrd v4, r4
-; P8BE-NEXT:    mtvsrd v5, r3
-; P8BE-NEXT:    vmrghh v3, v4, v3
-; P8BE-NEXT:    vmrghh v2, v2, v5
-; P8BE-NEXT:    vmrghw v2, v2, v3
+; P8BE-NEXT:    mtvsrwz v2, r10
+; P8BE-NEXT:    sub r3, r5, r3
+; P8BE-NEXT:    addi r5, r9, .LCPI4_0@toc@l
+; P8BE-NEXT:    lxvw4x v3, 0, r5
+; P8BE-NEXT:    sub r5, r6, r7
+; P8BE-NEXT:    mtvsrwz v4, r3
+; P8BE-NEXT:    sub r3, r4, r8
+; P8BE-NEXT:    mtvsrwz v5, r5
+; P8BE-NEXT:    mtvsrwz v0, r3
+; P8BE-NEXT:    vperm v4, v5, v4, v3
+; P8BE-NEXT:    vperm v2, v2, v0, v3
+; P8BE-NEXT:    vmrghw v2, v2, v4
 ; P8BE-NEXT:    blr
   %1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is 2^15.
 define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; P9LE-LABEL: dont_fold_urem_i16_smax:

 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 4
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 23
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 24749
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    ori r4, r4, 47143
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 6
+; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 5423
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v3, v4
 ; P9BE-NEXT:    extsh r3, r3
+; P9BE-NEXT:    vperm v3, v3, v4, v5
 ; P9BE-NEXT:    srawi r4, r3, 15
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 15
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
+; P9BE-NEXT:    mtvsrwz v2, r3
 ; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
-; P9BE-NEXT:    vmrghh v2, v4, v2
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    vperm v2, v4, v2, v5
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_i16_smax:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r4, 24749
 ; P8LE-NEXT:    lis r5, -19946

 ; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: dont_fold_urem_i16_smax:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r3, v2
 ; P8BE-NEXT:    lis r4, 24749
 ; P8BE-NEXT:    lis r5, -19946
+; P8BE-NEXT:    li r9, 0
 ; P8BE-NEXT:    ori r4, r4, 47143
 ; P8BE-NEXT:    ori r5, r5, 17097
+; P8BE-NEXT:    mtvsrwz v2, r9
 ; P8BE-NEXT:    clrldi r6, r3, 48
 ; P8BE-NEXT:    rldicl r7, r3, 48, 48
 ; P8BE-NEXT:    extsh r6, r6
 ; P8BE-NEXT:    extsh r7, r7
 ; P8BE-NEXT:    mulhw r4, r6, r4
 ; P8BE-NEXT:    mulhw r5, r7, r5
 ; P8BE-NEXT:    rldicl r3, r3, 32, 48
 ; P8BE-NEXT:    extsh r3, r3
 ; P8BE-NEXT:    srwi r8, r4, 31
 ; P8BE-NEXT:    srawi r4, r4, 11
 ; P8BE-NEXT:    add r5, r5, r7
 ; P8BE-NEXT:    add r4, r4, r8
 ; P8BE-NEXT:    srwi r8, r5, 31
 ; P8BE-NEXT:    srawi r5, r5, 4
 ; P8BE-NEXT:    mulli r4, r4, 5423
 ; P8BE-NEXT:    add r5, r5, r8
-; P8BE-NEXT:    li r8, 0
+; P8BE-NEXT:    addis r8, r2, .LCPI5_0@toc@ha
+; P8BE-NEXT:    srawi r10, r3, 15
 ; P8BE-NEXT:    mulli r5, r5, 23
-; P8BE-NEXT:    srawi r9, r3, 15
 ; P8BE-NEXT:    sub r4, r6, r4
-; P8BE-NEXT:    sldi r6, r8, 48
-; P8BE-NEXT:    addze r8, r9
-; P8BE-NEXT:    mtvsrd v2, r6
+; P8BE-NEXT:    addi r6, r8, .LCPI5_0@toc@l
+; P8BE-NEXT:    addze r8, r10
+; P8BE-NEXT:    lxvw4x v3, 0, r6
 ; P8BE-NEXT:    slwi r6, r8, 15
-; P8BE-NEXT:    sldi r4, r4, 48
+; P8BE-NEXT:    mtvsrwz v4, r4
 ; P8BE-NEXT:    sub r5, r7, r5
 ; P8BE-NEXT:    sub r3, r3, r6
-; P8BE-NEXT:    mtvsrd v3, r4
-; P8BE-NEXT:    sldi r4, r5, 48
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    mtvsrd v4, r4
-; P8BE-NEXT:    mtvsrd v5, r3
-; P8BE-NEXT:    vmrghh v3, v4, v3
-; P8BE-NEXT:    vmrghh v2, v2, v5
-; P8BE-NEXT:    vmrghw v2, v2, v3
+; P8BE-NEXT:    mtvsrwz v5, r5
+; P8BE-NEXT:    mtvsrwz v0, r3
+; P8BE-NEXT:    vperm v4, v5, v4, v3
+; P8BE-NEXT:    vperm v2, v2, v0, v3
+; P8BE-NEXT:    vmrghw v2, v2, v4
 ; P8BE-NEXT:    blr
   %1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423>
   ret <4 x i16> %1
 }
 
 ; Don't fold i64 srem.
 define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {
 ; P9LE-LABEL: dont_fold_srem_i64:

llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll

 ; P9BE-NEXT:    ori r4, r4, 2287
 ; P9BE-NEXT:    ori r5, r5, 16913
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 8
 ; P9BE-NEXT:    mulli r4, r4, 1003
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 21399
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    ori r4, r4, 33437
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 4
+; P9BE-NEXT:    ori r4, r4, 33437
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 5
 ; P9BE-NEXT:    mulli r4, r4, 98
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    rlwinm r3, r3, 30, 18, 31
+; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 2
 ; P9BE-NEXT:    mulli r3, r3, 124
 ; P9BE-NEXT:    sub r3, r4, r3
 ; P9BE-NEXT:    lis r4, 22765
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    ori r4, r4, 8969
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 0
+; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
-; P9BE-NEXT:    vmrghh v2, v2, v4
+; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    vperm v2, v2, v4, v5
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_urem_vec_1:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    lis r7, 21399

 ; P8BE-NEXT:    lis r10, 8456
 ; P8BE-NEXT:    ori r3, r3, 8969
 ; P8BE-NEXT:    ori r7, r7, 2287
 ; P8BE-NEXT:    ori r9, r9, 33437
 ; P8BE-NEXT:    ori r10, r10, 16913
 ; P8BE-NEXT:    rldicl r6, r4, 16, 48
 ; P8BE-NEXT:    clrldi r5, r4, 48
 ; P8BE-NEXT:    clrlwi r6, r6, 16
-; P8BE-NEXT:    rldicl r8, r4, 48, 48
 ; P8BE-NEXT:    clrlwi r5, r5, 16
 ; P8BE-NEXT:    mulhwu r3, r6, r3
+; P8BE-NEXT:    rldicl r8, r4, 48, 48
+; P8BE-NEXT:    mulhwu r7, r5, r7
 ; P8BE-NEXT:    rldicl r4, r4, 32, 48
 ; P8BE-NEXT:    clrlwi r8, r8, 16
-; P8BE-NEXT:    mulhwu r7, r5, r7
 ; P8BE-NEXT:    rlwinm r11, r4, 30, 18, 31
-; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulhwu r9, r8, r9
+; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulhwu r10, r11, r10
 ; P8BE-NEXT:    sub r11, r6, r3
-; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    srwi r7, r7, 8
+; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    add r3, r11, r3
-; P8BE-NEXT:    srwi r9, r9, 5
-; P8BE-NEXT:    srwi r10, r10, 2
 ; P8BE-NEXT:    mulli r7, r7, 1003
+; P8BE-NEXT:    srwi r9, r9, 5
 ; P8BE-NEXT:    srwi r3, r3, 6
+; P8BE-NEXT:    srwi r10, r10, 2
 ; P8BE-NEXT:    mulli r9, r9, 98
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    mulli r10, r10, 124
 ; P8BE-NEXT:    sub r5, r5, r7
-; P8BE-NEXT:    sub r7, r8, r9
-; P8BE-NEXT:    sldi r5, r5, 48
+; P8BE-NEXT:    addis r7, r2, .LCPI0_0@toc@ha
+; P8BE-NEXT:    mtvsrwz v2, r5
+; P8BE-NEXT:    addi r5, r7, .LCPI0_0@toc@l
+; P8BE-NEXT:    sub r8, r8, r9
+; P8BE-NEXT:    lxvw4x v3, 0, r5
 ; P8BE-NEXT:    sub r3, r6, r3
 ; P8BE-NEXT:    sub r4, r4, r10
-; P8BE-NEXT:    mtvsrd v2, r5
-; P8BE-NEXT:    sldi r5, r7, 48
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    sldi r4, r4, 48
-; P8BE-NEXT:    mtvsrd v3, r5
-; P8BE-NEXT:    mtvsrd v4, r3
-; P8BE-NEXT:    mtvsrd v5, r4
-; P8BE-NEXT:    vmrghh v2, v3, v2
-; P8BE-NEXT:    vmrghh v3, v4, v5
+; P8BE-NEXT:    mtvsrwz v4, r8
+; P8BE-NEXT:    mtvsrwz v5, r3
+; P8BE-NEXT:    mtvsrwz v0, r4
+; P8BE-NEXT:    vperm v2, v4, v2, v3
+; P8BE-NEXT:    vperm v3, v5, v0, v3
 ; P8BE-NEXT:    vmrghw v2, v3, v2
 ; P8BE-NEXT:    blr
   %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
   ret <4 x i16> %1
 }
 
 define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
 ; P9LE-LABEL: fold_urem_vec_2:

 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
 ; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
 ; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r3, r3, 16
+; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mulhwu r5, r3, r4
 ; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
-; P9BE-NEXT:    vmrghh v2, v2, v4
+; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    vperm v2, v2, v4, v5
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_urem_vec_2:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    ori r3, r3, 8969

 ; P8BE-NEXT:    srwi r12, r12, 1
 ; P8BE-NEXT:    add r9, r12, r9
 ; P8BE-NEXT:    sub r12, r4, r3
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    srwi r8, r8, 6
 ; P8BE-NEXT:    add r10, r11, r10
 ; P8BE-NEXT:    srwi r11, r12, 1
 ; P8BE-NEXT:    srwi r9, r9, 6
+; P8BE-NEXT:    mulli r8, r8, 95
 ; P8BE-NEXT:    add r3, r11, r3
 ; P8BE-NEXT:    srwi r10, r10, 6
 ; P8BE-NEXT:    srwi r3, r3, 6
-; P8BE-NEXT:    mulli r8, r8, 95
 ; P8BE-NEXT:    mulli r9, r9, 95
 ; P8BE-NEXT:    mulli r10, r10, 95
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    sub r5, r5, r8
+; P8BE-NEXT:    addis r8, r2, .LCPI1_0@toc@ha
+; P8BE-NEXT:    mtvsrwz v2, r5
+; P8BE-NEXT:    addi r5, r8, .LCPI1_0@toc@l
 ; P8BE-NEXT:    sub r6, r6, r9
-; P8BE-NEXT:    sub r7, r7, r10
+; P8BE-NEXT:    lxvw4x v3, 0, r5
+; P8BE-NEXT:    sub r5, r7, r10
 ; P8BE-NEXT:    sub r3, r4, r3
-; P8BE-NEXT:    sldi r5, r5, 48
-; P8BE-NEXT:    sldi r6, r6, 48
-; P8BE-NEXT:    sldi r4, r7, 48
-; P8BE-NEXT:    mtvsrd v2, r5
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    mtvsrd v3, r6
-; P8BE-NEXT:    mtvsrd v4, r4
-; P8BE-NEXT:    mtvsrd v5, r3
-; P8BE-NEXT:    vmrghh v2, v3, v2
-; P8BE-NEXT:    vmrghh v3, v5, v4
+; P8BE-NEXT:    mtvsrwz v4, r6
+; P8BE-NEXT:    mtvsrwz v5, r5
+; P8BE-NEXT:    mtvsrwz v0, r3
+; P8BE-NEXT:    vperm v2, v4, v2, v3
+; P8BE-NEXT:    vperm v3, v0, v5, v3
 ; P8BE-NEXT:    vmrghw v2, v3, v2
 ; P8BE-NEXT:    blr
   %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   ret <4 x i16> %1
 }
 
 
 ; Don't fold if we can combine urem with udiv.

 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    mulhwu r6, r4, r5
 ; P9BE-NEXT:    sub r4, r4, r6
 ; P9BE-NEXT:    srwi r4, r4, 1
 ; P9BE-NEXT:    add r4, r4, r6
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r6, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r6
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r6, r3, 16
 ; P9BE-NEXT:    mulhwu r7, r6, r5
 ; P9BE-NEXT:    sub r6, r6, r7
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r6, r6, r7
 ; P9BE-NEXT:    srwi r6, r6, 6
 ; P9BE-NEXT:    mulli r7, r6, 95
 ; P9BE-NEXT:    sub r3, r3, r7
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r7, r3, 16
+; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mulhwu r8, r7, r5
 ; P9BE-NEXT:    sub r7, r7, r8
 ; P9BE-NEXT:    srwi r7, r7, 1
 ; P9BE-NEXT:    add r7, r7, r8
 ; P9BE-NEXT:    srwi r7, r7, 6
 ; P9BE-NEXT:    mulli r8, r7, 95
 ; P9BE-NEXT:    sub r3, r3, r8
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r5
 ; P9BE-NEXT:    sub r8, r3, r5
 ; P9BE-NEXT:    srwi r8, r8, 1
 ; P9BE-NEXT:    add r5, r8, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r8, r5, 95
+; P9BE-NEXT:    mtvsrwz v0, r5
 ; P9BE-NEXT:    sub r3, r3, r8
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
-; P9BE-NEXT:    sldi r3, r4, 48
-; P9BE-NEXT:    vmrghh v2, v2, v4
+; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    vperm v2, v2, v4, v5
+; P9BE-NEXT:    mtvsrwz v4, r6
 ; P9BE-NEXT:    vmrghw v2, v2, v3
-; P9BE-NEXT:    mtvsrd v3, r3
-; P9BE-NEXT:    sldi r3, r6, 48
-; P9BE-NEXT:    mtvsrd v4, r3
-; P9BE-NEXT:    sldi r3, r7, 48
-; P9BE-NEXT:    vmrghh v3, v4, v3
-; P9BE-NEXT:    mtvsrd v4, r3
-; P9BE-NEXT:    sldi r3, r5, 48
-; P9BE-NEXT:    mtvsrd v5, r3
-; P9BE-NEXT:    vmrghh v4, v5, v4
+; P9BE-NEXT:    mtvsrwz v3, r4
+; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    mtvsrwz v4, r7
+; P9BE-NEXT:    vperm v4, v0, v4, v5
 ; P9BE-NEXT:    vmrghw v3, v4, v3
 ; P9BE-NEXT:    vadduhm v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: combine_urem_udiv:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765

 ; P8LE-NEXT:    vmrghh v4, v5, v4
 ; P8LE-NEXT:    vmrglw v3, v0, v3
 ; P8LE-NEXT:    vmrglw v2, v4, v2
 ; P8LE-NEXT:    vadduhm v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: combine_urem_udiv:
 ; P8BE:       # %bb.0:
-; P8BE-NEXT:    mfvsrd r5, v2
-; P8BE-NEXT:    lis r4, 22765
-; P8BE-NEXT:    ori r4, r4, 8969
-; P8BE-NEXT:    clrldi r3, r5, 48
-; P8BE-NEXT:    rldicl r6, r5, 48, 48
-; P8BE-NEXT:    clrlwi r8, r3, 16
-; P8BE-NEXT:    rldicl r7, r5, 32, 48
+; P8BE-NEXT:    mfvsrd r4, v2
+; P8BE-NEXT:    lis r3, 22765
+; P8BE-NEXT:    ori r3, r3, 8969
+; P8BE-NEXT:    clrldi r5, r4, 48
+; P8BE-NEXT:    rldicl r6, r4, 48, 48
+; P8BE-NEXT:    clrlwi r8, r5, 16
 ; P8BE-NEXT:    clrlwi r9, r6, 16
-; P8BE-NEXT:    rldicl r5, r5, 16, 48
-; P8BE-NEXT:    mulhwu r10, r8, r4
+; P8BE-NEXT:    rldicl r7, r4, 32, 48
+; P8BE-NEXT:    rldicl r4, r4, 16, 48
+; P8BE-NEXT:    mulhwu r10, r8, r3
+; P8BE-NEXT:    mulhwu r12, r9, r3
 ; P8BE-NEXT:    clrlwi r11, r7, 16
-; P8BE-NEXT:    mulhwu r12, r9, r4
-; P8BE-NEXT:    clrlwi r5, r5, 16
-; P8BE-NEXT:    mulhwu r0, r11, r4
-; P8BE-NEXT:    mulhwu r4, r5, r4
+; P8BE-NEXT:    clrlwi r4, r4, 16
+; P8BE-NEXT:    mulhwu r0, r11, r3
+; P8BE-NEXT:    mulhwu r3, r4, r3
 ; P8BE-NEXT:    sub r8, r8, r10
 ; P8BE-NEXT:    sub r9, r9, r12
 ; P8BE-NEXT:    srwi r8, r8, 1
-; P8BE-NEXT:    add r8, r8, r10
-; P8BE-NEXT:    sub r10, r11, r0
 ; P8BE-NEXT:    srwi r9, r9, 1
-; P8BE-NEXT:    sub r11, r5, r4
+; P8BE-NEXT:    sub r11, r11, r0
+; P8BE-NEXT:    add r8, r8, r10
 ; P8BE-NEXT:    add r9, r9, r12
-; P8BE-NEXT:    srwi r8, r8, 6
+; P8BE-NEXT:    sub r12, r4, r3
+; P8BE-NEXT:    addis r10, r2, .LCPI2_0@toc@ha
 ; P8BE-NEXT:    srwi r11, r11, 1
-; P8BE-NEXT:    srwi r10, r10, 1
+; P8BE-NEXT:    srwi r8, r8, 6
+; P8BE-NEXT:    srwi r12, r12, 1
 ; P8BE-NEXT:    srwi r9, r9, 6
-; P8BE-NEXT:    mulli r12, r8, 95
-; P8BE-NEXT:    add r4, r11, r4
-; P8BE-NEXT:    add r10, r10, r0
-; P8BE-NEXT:    mulli r11, r9, 95
-; P8BE-NEXT:    srwi r4, r4, 6
-; P8BE-NEXT:    srwi r10, r10, 6
-; P8BE-NEXT:    sldi r9, r9, 48
-; P8BE-NEXT:    sldi r8, r8, 48
-; P8BE-NEXT:    mtvsrd v3, r9
-; P8BE-NEXT:    mulli r9, r4, 95
-; P8BE-NEXT:    mtvsrd v2, r8
-; P8BE-NEXT:    mulli r8, r10, 95
-; P8BE-NEXT:    sub r3, r3, r12
-; P8BE-NEXT:    sub r6, r6, r11
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    vmrghh v2, v3, v2
-; P8BE-NEXT:    sldi r6, r6, 48
-; P8BE-NEXT:    sldi r10, r10, 48
-; P8BE-NEXT:    mtvsrd v3, r3
-; P8BE-NEXT:    sub r3, r5, r9
-; P8BE-NEXT:    sub r7, r7, r8
-; P8BE-NEXT:    mtvsrd v5, r6
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    sldi r5, r7, 48
-; P8BE-NEXT:    mtvsrd v1, r3
-; P8BE-NEXT:    sldi r3, r4, 48
-; P8BE-NEXT:    mtvsrd v4, r10
-; P8BE-NEXT:    mtvsrd v0, r5
-; P8BE-NEXT:    vmrghh v3, v5, v3
-; P8BE-NEXT:    mtvsrd v5, r3
-; P8BE-NEXT:    vmrghh v0, v1, v0
-; P8BE-NEXT:    vmrghh v4, v5, v4
-; P8BE-NEXT:    vmrghw v3, v0, v3
-; P8BE-NEXT:    vmrghw v2, v4, v2
-; P8BE-NEXT:    vadduhm v2, v3, v2
+; P8BE-NEXT:    addi r10, r10, .LCPI2_0@toc@l
+; P8BE-NEXT:    add r11, r11, r0
+; P8BE-NEXT:    mulli r0, r8, 95
+; P8BE-NEXT:    add r3, r12, r3
+; P8BE-NEXT:    mtvsrwz v3, r8
+; P8BE-NEXT:    lxvw4x v2, 0, r10
+; P8BE-NEXT:    srwi r10, r11, 6
+; P8BE-NEXT:    mulli r8, r9, 95
+; P8BE-NEXT:    srwi r3, r3, 6
+; P8BE-NEXT:    mtvsrwz v4, r9
+; P8BE-NEXT:    mulli r9, r10, 95
+; P8BE-NEXT:    mtvsrwz v5, r10
+; P8BE-NEXT:    mulli r10, r3, 95
+; P8BE-NEXT:    vperm v3, v4, v3, v2
+; P8BE-NEXT:    sub r5, r5, r0
+; P8BE-NEXT:    sub r6, r6, r8
+; P8BE-NEXT:    mtvsrwz v4, r5
+; P8BE-NEXT:    mtvsrwz v0, r6
+; P8BE-NEXT:    sub r5, r7, r9
+; P8BE-NEXT:    sub r4, r4, r10
+; P8BE-NEXT:    mtvsrwz v1, r5
+; P8BE-NEXT:    mtvsrwz v6, r4
+; P8BE-NEXT:    vperm v4, v0, v4, v2
+; P8BE-NEXT:    mtvsrwz v0, r3
+; P8BE-NEXT:    vperm v1, v6, v1, v2
+; P8BE-NEXT:    vperm v2, v0, v5, v2
+; P8BE-NEXT:    vmrghw v4, v1, v4
+; P8BE-NEXT:    vmrghw v2, v2, v3
+; P8BE-NEXT:    vadduhm v2, v4, v2
 ; P8BE-NEXT:    blr
   %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
   %3 = add <4 x i16> %1, %2
   ret <4 x i16> %3
 }
 
 ; Don't fold for divisors that are a power of two.

 ;
 ; P9BE-LABEL: dont_fold_urem_power_of_two:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    lis r4, 22765
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    clrlwi r3, r3, 27
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 26
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r3, r3, 16
+; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 29
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
-; P9BE-NEXT:    vmrghh v2, v2, v4
+; P9BE-NEXT:    mtvsrwz v2, r3
+; P9BE-NEXT:    vperm v2, v2, v4, v5
 ; P9BE-NEXT:    vmrghw v2, v3, v2
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_power_of_two:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    ori r3, r3, 8969

 ; P8LE-NEXT:    vmrghh v3, v4, v5
 ; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: dont_fold_urem_power_of_two:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, 22765
+; P8BE-NEXT:    addis r7, r2, .LCPI3_0@toc@ha
 ; P8BE-NEXT:    ori r3, r3, 8969
 ; P8BE-NEXT:    clrldi r5, r4, 48
-; P8BE-NEXT:    rldicl r7, r4, 16, 48
+; P8BE-NEXT:    rldicl r8, r4, 16, 48
 ; P8BE-NEXT:    clrlwi r5, r5, 16
-; P8BE-NEXT:    clrlwi r7, r7, 26
 ; P8BE-NEXT:    mulhwu r3, r5, r3
 ; P8BE-NEXT:    sub r6, r5, r3
 ; P8BE-NEXT:    srwi r6, r6, 1
 ; P8BE-NEXT:    add r3, r6, r3
 ; P8BE-NEXT:    rldicl r6, r4, 32, 48
 ; P8BE-NEXT:    srwi r3, r3, 6
-; P8BE-NEXT:    rldicl r4, r4, 48, 48
 ; P8BE-NEXT:    clrlwi r6, r6, 27
 ; P8BE-NEXT:    mulli r3, r3, 95
-; P8BE-NEXT:    sldi r6, r6, 48
+; P8BE-NEXT:    mtvsrwz v2, r6
+; P8BE-NEXT:    addi r6, r7, .LCPI3_0@toc@l
+; P8BE-NEXT:    rldicl r4, r4, 48, 48
+; P8BE-NEXT:    clrlwi r7, r8, 26
+; P8BE-NEXT:    lxvw4x v3, 0, r6
 ; P8BE-NEXT:    clrlwi r4, r4, 29
-; P8BE-NEXT:    mtvsrd v2, r6
-; P8BE-NEXT:    sldi r6, r7, 48
-; P8BE-NEXT:    sldi r4, r4, 48
-; P8BE-NEXT:    mtvsrd v3, r6
-; P8BE-NEXT:    mtvsrd v5, r4
+; P8BE-NEXT:    mtvsrwz v4, r7
+; P8BE-NEXT:    mtvsrwz v0, r4
 ; P8BE-NEXT:    sub r3, r5, r3
-; P8BE-NEXT:    vmrghh v2, v3, v2
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    mtvsrd v4, r3
-; P8BE-NEXT:    vmrghh v3, v5, v4
+; P8BE-NEXT:    vperm v2, v4, v2, v3
+; P8BE-NEXT:    mtvsrwz v5, r3
+; P8BE-NEXT:    vperm v3, v0, v5, v3
 ; P8BE-NEXT:    vmrghw v2, v2, v3
 ; P8BE-NEXT:    blr
   %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is one.
 define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {

 ; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    ori r5, r5, 30865
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 11
 ; P9BE-NEXT:    mulli r4, r4, 5423
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -19946
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    ori r4, r4, 17097
-; P9BE-NEXT:    mtvsrd v3, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 4
+; P9BE-NEXT:    ori r4, r4, 17097
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 4
 ; P9BE-NEXT:    mulli r4, r4, 23
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; P9BE-NEXT:    lxvx v5, 0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
-; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    rlwinm r3, r3, 31, 17, 31
+; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 8
 ; P9BE-NEXT:    mulli r3, r3, 654
 ; P9BE-NEXT:    sub r3, r4, r3
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v2, r3
+; P9BE-NEXT:    mtvsrwz v2, r3
 ; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    sldi r3, r3, 48
-; P9BE-NEXT:    mtvsrd v4, r3
-; P9BE-NEXT:    vmrghh v2, v4, v2
+; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    vperm v2, v4, v2, v5
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_one:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -14230
 ; P8LE-NEXT:    lis r7, -19946

 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: dont_fold_urem_one:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, 24749
 ; P8BE-NEXT:    lis r7, -19946
 ; P8BE-NEXT:    lis r8, -14230
+; P8BE-NEXT:    li r10, 0
 ; P8BE-NEXT:    ori r3, r3, 47143
 ; P8BE-NEXT:    ori r7, r7, 17097
 ; P8BE-NEXT:    ori r8, r8, 30865
+; P8BE-NEXT:    mtvsrwz v2, r10
 ; P8BE-NEXT:    clrldi r5, r4, 48
 ; P8BE-NEXT:    rldicl r6, r4, 48, 48
-; P8BE-NEXT:    rldicl r4, r4, 32, 48
 ; P8BE-NEXT:    clrlwi r5, r5, 16
+; P8BE-NEXT:    rldicl r4, r4, 32, 48
 ; P8BE-NEXT:    clrlwi r6, r6, 16
 ; P8BE-NEXT:    mulhwu r3, r5, r3
 ; P8BE-NEXT:    rlwinm r9, r4, 31, 17, 31
-; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulhwu r7, r6, r7
 ; P8BE-NEXT:    mulhwu r8, r9, r8
-; P8BE-NEXT:    li r9, 0
+; P8BE-NEXT:    addis r9, r2, .LCPI4_0@toc@ha
 ; P8BE-NEXT:    srwi r3, r3, 11
-; P8BE-NEXT:    srwi r7, r7, 4
 ; P8BE-NEXT:    mulli r3, r3, 5423
+; P8BE-NEXT:    srwi r7, r7, 4
 ; P8BE-NEXT:    srwi r8, r8, 8
 ; P8BE-NEXT:    mulli r7, r7, 23
 ; P8BE-NEXT:    mulli r8, r8, 654
 ; P8BE-NEXT:    sub r3, r5, r3
-; P8BE-NEXT:    sldi r5, r9, 48
-; P8BE-NEXT:    mtvsrd v2, r5
+; P8BE-NEXT:    addi r5, r9, .LCPI4_0@toc@l
+; P8BE-NEXT:    mtvsrwz v4, r3
+; P8BE-NEXT:    clrlwi r3, r4, 16
+; P8BE-NEXT:    lxvw4x v3, 0, r5
 ; P8BE-NEXT:    sub r5, r6, r7
-; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    sub r4, r4, r8
-; P8BE-NEXT:    sldi r5, r5, 48
-; P8BE-NEXT:    mtvsrd v3, r3
-; P8BE-NEXT:    sldi r3, r4, 48
-; P8BE-NEXT:    mtvsrd v4, r5
-; P8BE-NEXT:    mtvsrd v5, r3
-; P8BE-NEXT:    vmrghh v3, v4, v3
-; P8BE-NEXT:    vmrghh v2, v2, v5
-; P8BE-NEXT:    vmrghw v2, v2, v3
+; P8BE-NEXT:    sub r3, r3, r8
+; P8BE-NEXT:    mtvsrwz v5, r5
+; P8BE-NEXT:    mtvsrwz v0, r3
+; P8BE-NEXT:    vperm v4, v5, v4, v3
+; P8BE-NEXT:    vperm v2, v2, v0, v3
+; P8BE-NEXT:    vmrghw v2, v2, v4
 ; P8BE-NEXT:    blr
   %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is 2^16.
 define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; CHECK-LABEL: dont_fold_urem_i16_smax:

llvm/test/CodeGen/PowerPC/vec-itofp.ll

 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI0_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI0_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI0_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI0_2@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI0_2@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4

 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:

 ;
 ; CHECK-BE-LABEL: test2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v2
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
   %1 = uitofp <2 x i16> %0 to <2 x double>
   store <2 x double> %1, <2 x double>* %Sink, align 16
   ret void

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll

 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptoui <2 x float> %0 to <2 x i16>
   %2 = bitcast <2 x i16> %1 to i32
   ret i32 %2
 }

 ; CHECK-P9-NEXT:    vmrghh v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    vmrghh v2, v4, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <4 x float> %a to <4 x i16>
   %1 = bitcast <4 x i16> %0 to i64
   ret i64 %1
 }
 

 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghh v4, v4, v5
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptoui <8 x float> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 {

 ; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r4)
-; CHECK-BE-NEXT:    lxv vs0, 0(r4)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    xscvspdpn f4, vs1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    lxv vs2, 16(r4)
+; CHECK-BE-NEXT:    addis r5, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
+; CHECK-BE-NEXT:    lxv vs0, 48(r4)
+; CHECK-BE-NEXT:    addi r5, r5, .LCPI3_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r5
+; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
+; CHECK-BE-NEXT:    xxswapd vs4, vs2
+; CHECK-BE-NEXT:    xscvspdpn f5, vs2
+; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
+; CHECK-BE-NEXT:    xxsldwi vs6, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r5, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs1
+; CHECK-BE-NEXT:    mtvsrwz v3, r5
+; CHECK-BE-NEXT:    mffprwz r5, f4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f5
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    mtvsrwz v4, r5
+; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r5, f4
+; CHECK-BE-NEXT:    xscvspdpn f4, vs6
+; CHECK-BE-NEXT:    mtvsrwz v4, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    xxsldwi vs2, vs0, vs0, 3
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v2, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f4
-; CHECK-BE-NEXT:    sldi r5, r5, 48
+; CHECK-BE-NEXT:    xscvspdpn f2, vs1
+; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mtvsrwz v5, r5
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    mffprwz r5, f4
+; CHECK-BE-NEXT:    mtvsrwz v5, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r5
+; CHECK-BE-NEXT:    xxsldwi vs3, vs0, vs0, 3
+; CHECK-BE-NEXT:    mtvsrwz v0, r5
+; CHECK-BE-NEXT:    mffprwz r5, f2
+; CHECK-BE-NEXT:    xscvspdpn f2, vs3
+; CHECK-BE-NEXT:    vperm v5, v0, v5, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    sldi r5, r5, 48
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
+; CHECK-BE-NEXT:    vperm v0, v0, v1, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
+; CHECK-BE-NEXT:    vmrghw v4, v0, v5
+; CHECK-BE-NEXT:    mffprwz r5, f2
+; CHECK-BE-NEXT:    xscvspdpn f2, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v5, r5
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    lxv vs1, 48(r4)
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r5
-; CHECK-BE-NEXT:    mffprwz r5, f0
-; CHECK-BE-NEXT:    lxv vs0, 32(r4)
-; CHECK-BE-NEXT:    xscvspdpn f5, vs1
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    xscvdpsxws f5, f5
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v0, r5
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vmrghh v5, v5, v0
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghw v3, v5, v4
-; CHECK-BE-NEXT:    mffprwz r4, f5
-; CHECK-BE-NEXT:    xxmrghd vs4, v3, v2
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r4
+; CHECK-BE-NEXT:    mffprwz r5, f1
+; CHECK-BE-NEXT:    lxv vs1, 32(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f0, f0
+; CHECK-BE-NEXT:    mtvsrwz v6, r5
+; CHECK-BE-NEXT:    vperm v1, v6, v1, v2
 ; CHECK-BE-NEXT:    mffprwz r4, f2
-; CHECK-BE-NEXT:    stxv vs4, 0(r3)
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xxmrghd vs2, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    mffprwz r4, f0
+; CHECK-BE-NEXT:    xxsldwi vs0, vs1, vs1, 3
+; CHECK-BE-NEXT:    stxv vs2, 0(r3)
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v4, r4
+; CHECK-BE-NEXT:    vperm v3, v5, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r4
+; CHECK-BE-NEXT:    vmrghw v3, v3, v1
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r4
-; CHECK-BE-NEXT:    vmrghh v4, v4, v5
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd vs0, v3, v2
+; CHECK-BE-NEXT:    xxswapd vs0, vs1
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    xscvdpsxws f0, f0
+; CHECK-BE-NEXT:    mffprwz r4, f0
+; CHECK-BE-NEXT:    xscvspdpn f0, vs1
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    xscvdpsxws f0, f0
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
+; CHECK-BE-NEXT:    mffprwz r4, f0
+; CHECK-BE-NEXT:    xxsldwi vs0, vs1, vs1, 1
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    xscvdpsxws f0, f0
+; CHECK-BE-NEXT:    mffprwz r4, f0
+; CHECK-BE-NEXT:    mtvsrwz v0, r4
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd vs0, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptoui <16 x float> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptosi <2 x float> %0 to <2 x i16>
   %2 = bitcast <2 x i16> %1 to i32
   ret i32 %2
 }

 ; CHECK-P9-NEXT:    vmrghh v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r3
-; CHECK-BE-NEXT:    vmrghh v2, v4, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <4 x float> %a to <4 x i16>
   %1 = bitcast <4 x i16> %0 to i64
   ret i64 %1
 }
 

 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghh v4, v4, v5
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptosi <8 x float> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt_signed(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 {

 ; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs1, 16(r4)
-; CHECK-BE-NEXT:    lxv vs0, 0(r4)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    xscvspdpn f4, vs1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    lxv vs2, 16(r4)
+; CHECK-BE-NEXT:    addis r5, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
+; CHECK-BE-NEXT:    lxv vs0, 48(r4)
+; CHECK-BE-NEXT:    addi r5, r5, .LCPI7_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r5
+; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
+; CHECK-BE-NEXT:    xxswapd vs4, vs2
+; CHECK-BE-NEXT:    xscvspdpn f5, vs2
+; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
+; CHECK-BE-NEXT:    xxsldwi vs6, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r5, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs1
+; CHECK-BE-NEXT:    mtvsrwz v3, r5
+; CHECK-BE-NEXT:    mffprwz r5, f4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f5
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    mtvsrwz v4, r5
+; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r5, f4
+; CHECK-BE-NEXT:    xscvspdpn f4, vs6
+; CHECK-BE-NEXT:    mtvsrwz v4, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    xxsldwi vs2, vs0, vs0, 3
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v2, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f4
-; CHECK-BE-NEXT:    sldi r5, r5, 48
+; CHECK-BE-NEXT:    xscvspdpn f2, vs1
+; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mtvsrwz v5, r5
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    mffprwz r5, f4
+; CHECK-BE-NEXT:    mtvsrwz v5, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r5
+; CHECK-BE-NEXT:    xxsldwi vs3, vs0, vs0, 3
+; CHECK-BE-NEXT:    mtvsrwz v0, r5
+; CHECK-BE-NEXT:    mffprwz r5, f2
+; CHECK-BE-NEXT:    xscvspdpn f2, vs3
+; CHECK-BE-NEXT:    vperm v5, v0, v5, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    sldi r5, r5, 48
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
+; CHECK-BE-NEXT:    vperm v0, v0, v1, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
+; CHECK-BE-NEXT:    vmrghw v4, v0, v5
+; CHECK-BE-NEXT:    mffprwz r5, f2
+; CHECK-BE-NEXT:    xscvspdpn f2, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v5, r5
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    lxv vs1, 48(r4)
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r5
-; CHECK-BE-NEXT:    mffprwz r5, f0
-; CHECK-BE-NEXT:    lxv vs0, 32(r4)
-; CHECK-BE-NEXT:    xscvspdpn f5, vs1
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    xscvdpsxws f5, f5
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v0, r5
-; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vmrghh v5, v5, v0
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghw v3, v5, v4
-; CHECK-BE-NEXT:    mffprwz r4, f5
-; CHECK-BE-NEXT:    xxmrghd vs4, v3, v2
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r4
+; CHECK-BE-NEXT:    mffprwz r5, f1
+; CHECK-BE-NEXT:    lxv vs1, 32(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f0, f0
+; CHECK-BE-NEXT:    mtvsrwz v6, r5
+; CHECK-BE-NEXT:    vperm v1, v6, v1, v2
 ; CHECK-BE-NEXT:    mffprwz r4, f2
-; CHECK-BE-NEXT:    stxv vs4, 0(r3)
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xxmrghd vs2, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    mffprwz r4, f0
+; CHECK-BE-NEXT:    xxsldwi vs0, vs1, vs1, 3
+; CHECK-BE-NEXT:    stxv vs2, 0(r3)
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v4, r4
+; CHECK-BE-NEXT:    vperm v3, v5, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r4
+; CHECK-BE-NEXT:    vmrghw v3, v3, v1
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r4
-; CHECK-BE-NEXT:    vmrghh v4, v4, v5
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd vs0, v3, v2
+; CHECK-BE-NEXT:    xxswapd vs0, vs1
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    xscvdpsxws f0, f0
+; CHECK-BE-NEXT:    mffprwz r4, f0
+; CHECK-BE-NEXT:    xscvspdpn f0, vs1
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    xscvdpsxws f0, f0
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
+; CHECK-BE-NEXT:    mffprwz r4, f0
+; CHECK-BE-NEXT:    xxsldwi vs0, vs1, vs1, 1
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    xscvdpsxws f0, f0
+; CHECK-BE-NEXT:    mffprwz r4, f0
+; CHECK-BE-NEXT:    mtvsrwz v0, r4
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd vs0, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptosi <16 x float> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll

 ; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vmrghb v2, v2, v3
+; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptoui <2 x float> %0 to <2 x i8>
   %2 = bitcast <2 x i8> %1 to i16

 ; CHECK-P9-NEXT:    vmrghb v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v4, v3
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vmrghb v2, v4, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
+; CHECK-BE-NEXT:    vmrghh v2, v2, v4
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <4 x float> %a to <4 x i8>
   %1 = bitcast <4 x i8> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghb v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghb v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghh v2, v2, v4
+; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptoui <8 x float> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xxsldwi vs4, vs3, vs3, 3
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs4
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs4
-; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs3, vs3, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vmrghb v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vmrghb v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v5, r3
+; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghb v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v5, r3
+; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v5, r3
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    vperm v5, v0, v5, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghb v4, v5, v4
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v0, r3
-; CHECK-BE-NEXT:    vmrghb v5, v5, v0
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v1, r3
+; CHECK-BE-NEXT:    vperm v2, v0, v1, v2
+; CHECK-BE-NEXT:    vmrghh v2, v2, v5
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptoui <16 x float> %a to <16 x i8>
   ret <16 x i8> %1
 }
 
 define i16 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {

 ; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vmrghb v2, v2, v3
+; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptosi <2 x float> %0 to <2 x i8>
   %2 = bitcast <2 x i8> %1 to i16

 ; CHECK-P9-NEXT:    vmrghb v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
+; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v4, v3
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vmrghb v2, v4, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
+; CHECK-BE-NEXT:    vmrghh v2, v2, v4
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <4 x float> %a to <4 x i8>
   %1 = bitcast <4 x i8> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghb v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghb v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghh v2, v2, v4
+; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptosi <8 x float> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xxsldwi vs4, vs3, vs3, 3
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs4
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs4
-; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
 ; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvspdpn f4, vs3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs3, vs3, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vmrghb v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vmrghb v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v5, r3
+; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghb v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v5, r3
+; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    mtvsrd v5, r3
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    vperm v5, v0, v5, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghb v4, v5, v4
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v0, r3
-; CHECK-BE-NEXT:    vmrghb v5, v5, v0
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v1, r3
+; CHECK-BE-NEXT:    vperm v2, v0, v1, v2
+; CHECK-BE-NEXT:    vmrghh v2, v2, v5
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptosi <16 x float> %a to <16 x i8>
   ret <16 x i8> %1
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll

 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <2 x double> %a to <2 x i16>
   %1 = bitcast <2 x i16> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
+; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptoui <4 x double> %a to <4 x i16>
   %2 = bitcast <4 x i16> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
-; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghh v4, v4, v5
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptoui <8 x double> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 {

 ; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs4, 48(r4)
-; CHECK-BE-NEXT:    lxv vs3, 32(r4)
-; CHECK-BE-NEXT:    lxv vs2, 16(r4)
-; CHECK-BE-NEXT:    lxv vs1, 0(r4)
-; CHECK-BE-NEXT:    xscvdpsxws f5, f4
-; CHECK-BE-NEXT:    xxswapd vs4, vs4
-; CHECK-BE-NEXT:    xscvdpsxws f6, f3
+; CHECK-BE-NEXT:    lxv vs3, 48(r4)
+; CHECK-BE-NEXT:    lxv vs2, 32(r4)
+; CHECK-BE-NEXT:    lxv vs1, 16(r4)
+; CHECK-BE-NEXT:    lxv vs0, 0(r4)
+; CHECK-BE-NEXT:    addis r5, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    addi r5, r5, .LCPI3_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r5
+; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    xscvdpsxws f5, f2
+; CHECK-BE-NEXT:    xscvdpsxws f6, f1
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f7, f2
-; CHECK-BE-NEXT:    lxv vs0, 112(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f7, f0
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xxswapd vs1, vs1
+; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r5, f5
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r5
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    xscvdpsxws f4, f1
-; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f6
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
-; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f7
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    mtvsrd v4, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r5
+; CHECK-BE-NEXT:    mtvsrwz v3, r5
+; CHECK-BE-NEXT:    mffprwz r5, f5
+; CHECK-BE-NEXT:    mtvsrwz v4, r5
+; CHECK-BE-NEXT:    mffprwz r5, f6
+; CHECK-BE-NEXT:    mtvsrwz v5, r5
+; CHECK-BE-NEXT:    mffprwz r5, f7
+; CHECK-BE-NEXT:    mtvsrwz v0, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v0, r5
+; CHECK-BE-NEXT:    lxv vs3, 112(r4)
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f2
 ; CHECK-BE-NEXT:    lxv vs2, 96(r4)
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v1, r5
+; CHECK-BE-NEXT:    vperm v3, v3, v1, v2
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    lxv vs1, 80(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs3
+; CHECK-BE-NEXT:    vperm v4, v4, v1, v2
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
+; CHECK-BE-NEXT:    mffprwz r5, f0
+; CHECK-BE-NEXT:    lxv vs0, 64(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    vperm v5, v5, v1, v2
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    vperm v0, v0, v1, v2
+; CHECK-BE-NEXT:    mffprwz r4, f4
+; CHECK-BE-NEXT:    vmrghw v5, v0, v5
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    vmrghh v4, v4, v1
-; CHECK-BE-NEXT:    mtvsrd v1, r5
+; CHECK-BE-NEXT:    xxmrghd vs4, v5, v3
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r5, f0
-; CHECK-BE-NEXT:    lxv vs0, 64(r4)
-; CHECK-BE-NEXT:    vmrghh v5, v5, v1
-; CHECK-BE-NEXT:    sldi r5, r5, 48
+; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    stxv vs4, 0(r3)
 ; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    mtvsrd v1, r5
-; CHECK-BE-NEXT:    vmrghw v3, v5, v4
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    vmrghh v0, v0, v1
-; CHECK-BE-NEXT:    xxmrghd vs3, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v2, r4
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    sldi r4, r4, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    stxv vs3, 0(r3)
-; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r4, f2
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    vmrghw v2, v2, v0
-; CHECK-BE-NEXT:    mtvsrd v3, r4
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r4, r4, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r4
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r4
-; CHECK-BE-NEXT:    vmrghh v4, v4, v5
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd vs0, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r4
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd vs0, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptoui <16 x double> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <2 x double> %a to <2 x i16>
   %1 = bitcast <2 x i16> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
+; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptosi <4 x double> %a to <4 x i16>
   %2 = bitcast <4 x i16> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
-; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghh v4, v4, v5
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptosi <8 x double> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt_signed(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 {

 ; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs4, 48(r4)
-; CHECK-BE-NEXT:    lxv vs3, 32(r4)
-; CHECK-BE-NEXT:    lxv vs2, 16(r4)
-; CHECK-BE-NEXT:    lxv vs1, 0(r4)
-; CHECK-BE-NEXT:    xscvdpsxws f5, f4
-; CHECK-BE-NEXT:    xxswapd vs4, vs4
-; CHECK-BE-NEXT:    xscvdpsxws f6, f3
+; CHECK-BE-NEXT:    lxv vs3, 48(r4)
+; CHECK-BE-NEXT:    lxv vs2, 32(r4)
+; CHECK-BE-NEXT:    lxv vs1, 16(r4)
+; CHECK-BE-NEXT:    lxv vs0, 0(r4)
+; CHECK-BE-NEXT:    addis r5, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    addi r5, r5, .LCPI7_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r5
+; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    xscvdpsxws f5, f2
+; CHECK-BE-NEXT:    xscvdpsxws f6, f1
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f7, f2
-; CHECK-BE-NEXT:    lxv vs0, 112(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f7, f0
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xxswapd vs1, vs1
+; CHECK-BE-NEXT:    xxswapd vs0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r5, f5
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v2, r5
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    xscvdpsxws f4, f1
-; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f6
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
-; CHECK-BE-NEXT:    mtvsrd v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xscvdpsxws f3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r5, r5, 48
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f7
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
-; CHECK-BE-NEXT:    mtvsrd v4, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r5
+; CHECK-BE-NEXT:    mtvsrwz v3, r5
+; CHECK-BE-NEXT:    mffprwz r5, f5
+; CHECK-BE-NEXT:    mtvsrwz v4, r5
+; CHECK-BE-NEXT:    mffprwz r5, f6
+; CHECK-BE-NEXT:    mtvsrwz v5, r5
+; CHECK-BE-NEXT:    mffprwz r5, f7
+; CHECK-BE-NEXT:    mtvsrwz v0, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v0, r5
+; CHECK-BE-NEXT:    lxv vs3, 112(r4)
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f2
 ; CHECK-BE-NEXT:    lxv vs2, 96(r4)
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    mtvsrd v1, r5
+; CHECK-BE-NEXT:    vperm v3, v3, v1, v2
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
 ; CHECK-BE-NEXT:    mffprwz r5, f1
 ; CHECK-BE-NEXT:    lxv vs1, 80(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs3
+; CHECK-BE-NEXT:    vperm v4, v4, v1, v2
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
+; CHECK-BE-NEXT:    mffprwz r5, f0
+; CHECK-BE-NEXT:    lxv vs0, 64(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    vperm v5, v5, v1, v2
+; CHECK-BE-NEXT:    mtvsrwz v1, r5
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    vperm v0, v0, v1, v2
+; CHECK-BE-NEXT:    mffprwz r4, f4
+; CHECK-BE-NEXT:    vmrghw v5, v0, v5
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    sldi r5, r5, 48
-; CHECK-BE-NEXT:    vmrghh v4, v4, v1
-; CHECK-BE-NEXT:    mtvsrd v1, r5
+; CHECK-BE-NEXT:    xxmrghd vs4, v5, v3
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r5, f0
-; CHECK-BE-NEXT:    lxv vs0, 64(r4)
-; CHECK-BE-NEXT:    vmrghh v5, v5, v1
-; CHECK-BE-NEXT:    sldi r5, r5, 48
+; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    stxv vs4, 0(r3)
 ; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    mtvsrd v1, r5
-; CHECK-BE-NEXT:    vmrghw v3, v5, v4
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    vmrghh v0, v0, v1
-; CHECK-BE-NEXT:    xxmrghd vs3, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v2, r4
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    sldi r4, r4, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    stxv vs3, 0(r3)
-; CHECK-BE-NEXT:    mtvsrd v3, r4
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r4, f2
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    vmrghw v2, v2, v0
-; CHECK-BE-NEXT:    mtvsrd v3, r4
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r4, r4, 48
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r4
-; CHECK-BE-NEXT:    vmrghh v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v4, r4
+; CHECK-BE-NEXT:    mtvsrwz v5, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    sldi r4, r4, 48
-; CHECK-BE-NEXT:    mtvsrd v5, r4
-; CHECK-BE-NEXT:    vmrghh v4, v4, v5
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd vs0, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r4
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd vs0, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptosi <16 x double> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpuxws f0, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    mtvsrws v3, r3
 ; CHECK-BE-NEXT:    xscvdpuxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <2 x double> %a to <2 x i32>
   %1 = bitcast <2 x i32> %0 to i64
   ret i64 %1
 }
 

 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    mtvsrws v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <2 x double> %a to <2 x i32>
   %1 = bitcast <2 x i32> %0 to i64
   ret i64 %1
 }
 

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll

 ; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vmrghb v2, v3, v2
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <2 x double> %a to <2 x i8>
   %1 = bitcast <2 x i8> %0 to i16
   ret i16 %1

 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    vmrghb v2, v2, v3
+; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
+; CHECK-BE-NEXT:    vmrghh v2, v2, v3
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptoui <4 x double> %a to <4 x i8>
   %2 = bitcast <4 x i8> %1 to i32
   ret i32 %2
 }

 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
-; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    vmrghb v2, v2, v3
+; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghh v2, v2, v4
+; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptoui <8 x double> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs7, 112(r3)
-; CHECK-BE-NEXT:    lxv vs6, 96(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f8, f7
 ; CHECK-BE-NEXT:    xxswapd vs7, vs7
-; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs4, 64(r3)
 ; CHECK-BE-NEXT:    lxv vs5, 80(r3)
+; CHECK-BE-NEXT:    lxv vs6, 96(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f7
 ; CHECK-BE-NEXT:    mffprwz r3, f8
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f7
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f6
 ; CHECK-BE-NEXT:    xxswapd vs6, vs6
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f6
-; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    vmrghb v2, v2, v3
+; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f7
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f6
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f5
 ; CHECK-BE-NEXT:    xxswapd vs5, vs5
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f5
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f6
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs4
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f5
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
+; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
+; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
+; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v0, r3
-; CHECK-BE-NEXT:    vmrghb v5, v5, v0
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v1, r3
+; CHECK-BE-NEXT:    vperm v2, v0, v1, v2
+; CHECK-BE-NEXT:    vmrghh v2, v2, v5
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptoui <16 x double> %a to <16 x i8>
   ret <16 x i8> %1
 }
 
 define i16 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {

 ; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-BE-NEXT:    lxvx v3, 0, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vmrghb v2, v3, v2
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <2 x double> %a to <2 x i8>
   %1 = bitcast <2 x i8> %0 to i16
   ret i16 %1

 ; CHECK-P9-NEXT:    vmrglh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    vmrghb v2, v2, v3
+; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
+; CHECK-BE-NEXT:    vmrghh v2, v2, v3
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptosi <4 x double> %a to <4 x i8>
   %2 = bitcast <4 x i8> %1 to i32
   ret i32 %2
 }

 ; CHECK-P9-NEXT:    vmrglh v3, v4, v3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
-; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs2, 32(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    vmrghb v2, v2, v3
+; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghh v2, v2, v4
+; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptosi <8 x double> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    vmrglh v4, v5, v4
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs7, 112(r3)
-; CHECK-BE-NEXT:    lxv vs6, 96(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
+; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f8, f7
 ; CHECK-BE-NEXT:    xxswapd vs7, vs7
-; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs4, 64(r3)
 ; CHECK-BE-NEXT:    lxv vs5, 80(r3)
+; CHECK-BE-NEXT:    lxv vs6, 96(r3)
+; CHECK-BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
+; CHECK-BE-NEXT:    lxvx v2, 0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f7
 ; CHECK-BE-NEXT:    mffprwz r3, f8
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f7
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f6
 ; CHECK-BE-NEXT:    xxswapd vs6, vs6
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f6
-; CHECK-BE-NEXT:    mtvsrd v3, r3
-; CHECK-BE-NEXT:    vmrghb v2, v2, v3
+; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f7
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f6
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f5
 ; CHECK-BE-NEXT:    xxswapd vs5, vs5
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f5
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f6
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    vmrghh v2, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs4
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f5
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
+; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    vmrghw v2, v3, v2
-; CHECK-BE-NEXT:    mtvsrd v3, r3
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mtvsrd v4, r3
-; CHECK-BE-NEXT:    vmrghb v3, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
+; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrd v4, r3
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrd v5, r3
-; CHECK-BE-NEXT:    vmrghb v4, v4, v5
+; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    sldi r3, r3, 56
-; CHECK-BE-NEXT:    mtvsrd v0, r3
-; CHECK-BE-NEXT:    vmrghb v5, v5, v0
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v1, r3
+; CHECK-BE-NEXT:    vperm v2, v0, v1, v2
+; CHECK-BE-NEXT:    vmrghh v2, v2, v5
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptosi <16 x double> %a to <16 x i8>
   ret <16 x i8> %1
 }

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
 ; CHECK-BE-NEXT:    clrlwi r3, r3, 16
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
 ; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    vmrgow v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = uitofp <2 x i16> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64
   ret i64 %2
 }

 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
-; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <4 x i16>
   %1 = uitofp <4 x i16> %0 to <4 x float>
   ret <4 x float> %1
 }
 

 ; CHECK-P9-NEXT:    xvcvuxwsp vs0, v4
 ; CHECK-P9-NEXT:    xvcvuxwsp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
-; CHECK-BE-NEXT:    xvcvuxwsp vs0, v3
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-NEXT:    stxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-NEXT:    vmrghh v4, v3, v2
+; CHECK-BE-NEXT:    vmrglh v2, v3, v2
+; CHECK-BE-NEXT:    xvcvuxwsp vs0, v4
 ; CHECK-BE-NEXT:    xvcvuxwsp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
+; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = uitofp <8 x i16> %a to <8 x float>
   store <8 x float> %0, <8 x float>* %agg.result, align 32
   ret void
 }
 
 define void @test16elt(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {

 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 16(r4)
 ; CHECK-BE-NEXT:    lxv v3, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v5, v5, v5
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_1@toc@l
-; CHECK-BE-NEXT:    vperm v0, v3, v5, v4
+; CHECK-BE-NEXT:    vperm v0, v5, v3, v4
+; CHECK-BE-NEXT:    vperm v4, v5, v2, v4
+; CHECK-BE-NEXT:    vmrglh v3, v5, v3
+; CHECK-BE-NEXT:    vmrglh v2, v5, v2
 ; CHECK-BE-NEXT:    xvcvuxwsp vs0, v0
-; CHECK-BE-NEXT:    lxvx v0, 0, r4
-; CHECK-BE-NEXT:    vperm v3, v5, v3, v0
-; CHECK-BE-NEXT:    stxv vs0, 0(r3)
-; CHECK-BE-NEXT:    xvcvuxwsp vs1, v3
-; CHECK-BE-NEXT:    vperm v3, v2, v5, v4
-; CHECK-BE-NEXT:    vperm v2, v5, v2, v0
+; CHECK-BE-NEXT:    xvcvuxwsp vs1, v4
+; CHECK-BE-NEXT:    stxv vs1, 32(r3)
 ; CHECK-BE-NEXT:    xvcvuxwsp vs2, v3
 ; CHECK-BE-NEXT:    xvcvuxwsp vs3, v2
-; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
-; CHECK-BE-NEXT:    stxv vs2, 32(r3)
+; CHECK-BE-NEXT:    stxv vs2, 16(r3)
+; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x i16>, <16 x i16>* %0, align 32
   %1 = uitofp <16 x i16> %a to <16 x float>
   store <16 x float> %1, <16 x float>* %agg.result, align 64
   ret void
 }
 

 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
 ; CHECK-BE-NEXT:    extsh r3, r3
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
 ; CHECK-BE-NEXT:    mtfprwa f0, r3
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    vmrgow v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = sitofp <2 x i16> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    xvcvsxwsp vs0, v3
 ; CHECK-P9-NEXT:    xvcvsxwsp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxvx v3, 0, r4
-; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
+; CHECK-BE-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-NEXT:    vmrglh v3, v3, v2
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v2
 ; CHECK-BE-NEXT:    vextsh2w v3, v3
 ; CHECK-BE-NEXT:    vextsh2w v2, v2
 ; CHECK-BE-NEXT:    xvcvsxwsp vs0, v3
 ; CHECK-BE-NEXT:    xvcvsxwsp vs1, v2
-; CHECK-BE-NEXT:    stxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
+; CHECK-BE-NEXT:    stxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = sitofp <8 x i16> %a to <8 x float>
   store <8 x float> %0, <8 x float>* %agg.result, align 32
   ret void
 }
 
 define void @test16elt_signed(<16 x float>* noalias nocapture sret(<16 x float>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {

 ; CHECK-P9-NEXT:    stxv vs3, 48(r3)
 ; CHECK-P9-NEXT:    stxv vs2, 32(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 16(r4)
 ; CHECK-BE-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v5, v5, v5
-; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxvx v4, 0, r4
-; CHECK-BE-NEXT:    vperm v0, v5, v3, v4
-; CHECK-BE-NEXT:    vperm v4, v5, v2, v4
+; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    vmrglh v5, v4, v3
+; CHECK-BE-NEXT:    vmrglh v4, v4, v2
 ; CHECK-BE-NEXT:    vmrghh v3, v3, v3
 ; CHECK-BE-NEXT:    vmrghh v2, v2, v2
-; CHECK-BE-NEXT:    vextsh2w v0, v0
+; CHECK-BE-NEXT:    vextsh2w v5, v5
 ; CHECK-BE-NEXT:    vextsh2w v4, v4
 ; CHECK-BE-NEXT:    vextsh2w v3, v3
 ; CHECK-BE-NEXT:    vextsh2w v2, v2
-; CHECK-BE-NEXT:    xvcvsxwsp vs0, v0
+; CHECK-BE-NEXT:    xvcvsxwsp vs0, v5
 ; CHECK-BE-NEXT:    xvcvsxwsp vs1, v4
 ; CHECK-BE-NEXT:    xvcvsxwsp vs2, v3
 ; CHECK-BE-NEXT:    xvcvsxwsp vs3, v2
-; CHECK-BE-NEXT:    stxv vs3, 32(r3)
-; CHECK-BE-NEXT:    stxv vs2, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs1, 48(r3)
+; CHECK-BE-NEXT:    stxv vs3, 32(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
+; CHECK-BE-NEXT:    stxv vs2, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x i16>, <16 x i16>* %0, align 32
   %1 = sitofp <16 x i16> %a to <16 x float>
   store <16 x float> %1, <16 x float>* %agg.result, align 64
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
-; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxddp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = uitofp <2 x i16> %0 to <2 x double>
   ret <2 x double> %1
 }
 

 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:

 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_2@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_2@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4

 ; CHECK-BE-NEXT:    lxv v2, 16(r4)
 ; CHECK-BE-NEXT:    lxv v3, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v5, v5, v5
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v4, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_1@toc@l
-; CHECK-BE-NEXT:    vperm v0, v3, v5, v4
+; CHECK-BE-NEXT:    vperm v0, v5, v3, v4
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v0
 ; CHECK-BE-NEXT:    lxvx v0, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_2@toc@l
 ; CHECK-BE-NEXT:    vperm v1, v5, v3, v0
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v1
 ; CHECK-BE-NEXT:    lxvx v1, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_3@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_3@toc@l
 ; CHECK-BE-NEXT:    vperm v6, v5, v3, v1
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs2, v6
 ; CHECK-BE-NEXT:    lxvx v6, 0, r4
 ; CHECK-BE-NEXT:    vperm v3, v5, v3, v6
 ; CHECK-BE-NEXT:    stxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs3, v3
-; CHECK-BE-NEXT:    vperm v3, v2, v5, v4
+; CHECK-BE-NEXT:    vperm v3, v5, v2, v4
 ; CHECK-BE-NEXT:    xvcvuxddp vs4, v3
 ; CHECK-BE-NEXT:    vperm v3, v5, v2, v0
 ; CHECK-BE-NEXT:    xvcvuxddp vs5, v3
 ; CHECK-BE-NEXT:    vperm v3, v5, v2, v1
 ; CHECK-BE-NEXT:    vperm v2, v5, v2, v6
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs6, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs7, v2

llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll

 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    xxlor vs1, v2, v2
 ; CHECK-BE-NEXT:    xscvuxdsp f1, f1
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f1
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    vmrgow v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = uitofp <2 x i64> %a to <2 x float>
   %1 = bitcast <2 x float> %0 to i64
   ret i64 %1
 }
 

 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    xxlor vs1, v2, v2
 ; CHECK-BE-NEXT:    xscvsxdsp f1, f1
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f1
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    vmrgow v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = sitofp <2 x i64> %a to <2 x float>
   %1 = bitcast <2 x float> %0 to i64
   ret i64 %1
 }
 

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
 ; CHECK-BE-NEXT:    clrlwi r3, r3, 24
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
 ; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    vmrgow v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = uitofp <2 x i8> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64
   ret i64 %2
 }

 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
-; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = uitofp <4 x i8> %0 to <4 x float>
   ret <4 x float> %1
 }
 

 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxwsp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxwsp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:

 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxwsp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_2@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxwsp vs1, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4

 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
 ; CHECK-BE-NEXT:    extsb r3, r3
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
 ; CHECK-BE-NEXT:    mtfprwa f0, r3
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    vmrgow v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = sitofp <2 x i8> %0 to <2 x float>
   %2 = bitcast <2 x float> %1 to i64
   ret i64 %2
 }

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r3
-; CHECK-BE-NEXT:    vperm v2, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxddp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = uitofp <2 x i8> %0 to <2 x double>
   ret <2 x double> %1
 }
 

 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrws v2, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI1_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:

 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_2@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI2_2@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4

 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v2, v4, v3
+; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    xvcvuxddp vs0, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_2@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_2@toc@l
 ; CHECK-BE-NEXT:    vperm v3, v4, v2, v3
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    xvcvuxddp vs1, v3
 ; CHECK-BE-NEXT:    lxvx v3, 0, r4

llvm/test/CodeGen/PowerPC/vec_insert_elt.ll

 ; CHECK-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; CHECK-NEXT:    xxinsertw v2, vs0, 12
 ; CHECK-NEXT:    xxinsertw v2, vs0, 4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: testFloatImm1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpspn vs0, f1
-; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 3
 ; CHECK-BE-NEXT:    xxinsertw v2, vs0, 0
 ; CHECK-BE-NEXT:    xxinsertw v2, vs0, 8
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: testFloatImm1:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f1
 ; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 3

llvm/test/CodeGen/PowerPC/vec_int_ext.ll

 ; CHECK-BE-NEXT:    vextublx 7, 7, 2
 ; CHECK-BE-NEXT:    vextublx 8, 8, 2
 ; CHECK-BE-NEXT:    li 3, 0
 ; CHECK-BE-NEXT:    li 4, 2
 ; CHECK-BE-NEXT:    li 5, 4
 ; CHECK-BE-NEXT:    li 6, 6
 ; CHECK-BE-NEXT:    extsb 9, 9
 ; CHECK-BE-NEXT:    extsb 10, 10
-; CHECK-BE-NEXT:    extsb 7, 7
-; CHECK-BE-NEXT:    extsb 8, 8
 ; CHECK-BE-NEXT:    vextublx 3, 3, 2
 ; CHECK-BE-NEXT:    vextublx 4, 4, 2
+; CHECK-BE-NEXT:    vextublx 5, 5, 2
+; CHECK-BE-NEXT:    extsb 7, 7
+; CHECK-BE-NEXT:    extsb 8, 8
+; CHECK-BE-NEXT:    extsb 5, 5
 ; CHECK-BE-NEXT:    extsb 3, 3
 ; CHECK-BE-NEXT:    extsb 4, 4
-; CHECK-BE-NEXT:    sldi 10, 10, 48
-; CHECK-BE-NEXT:    sldi 9, 9, 48
-; CHECK-BE-NEXT:    vextublx 5, 5, 2
+; CHECK-BE-NEXT:    mtvsrwz 35, 9
+; CHECK-BE-NEXT:    addis 9, 2, .LCPI11_0@toc@ha
 ; CHECK-BE-NEXT:    vextublx 6, 6, 2
-; CHECK-BE-NEXT:    sldi 8, 8, 48
-; CHECK-BE-NEXT:    sldi 7, 7, 48
-; CHECK-BE-NEXT:    extsb 5, 5
+; CHECK-BE-NEXT:    mtvsrwz 34, 10
+; CHECK-BE-NEXT:    mtvsrwz 37, 7
 ; CHECK-BE-NEXT:    extsb 6, 6
-; CHECK-BE-NEXT:    sldi 6, 6, 48
-; CHECK-BE-NEXT:    sldi 5, 5, 48
-; CHECK-BE-NEXT:    sldi 4, 4, 48
-; CHECK-BE-NEXT:    sldi 3, 3, 48
-; CHECK-BE-NEXT:    mtvsrd 34, 10
-; CHECK-BE-NEXT:    mtvsrd 35, 9
-; CHECK-BE-NEXT:    mtvsrd 36, 7
-; CHECK-BE-NEXT:    mtvsrd 37, 3
-; CHECK-BE-NEXT:    vmrghh 2, 3, 2
-; CHECK-BE-NEXT:    mtvsrd 35, 8
-; CHECK-BE-NEXT:    vmrghh 3, 4, 3
-; CHECK-BE-NEXT:    mtvsrd 36, 5
+; CHECK-BE-NEXT:    mtvsrwz 32, 3
+; CHECK-BE-NEXT:    addi 9, 9, .LCPI11_0@toc@l
+; CHECK-BE-NEXT:    lxvx 36, 0, 9
+; CHECK-BE-NEXT:    vperm 2, 3, 2, 4
+; CHECK-BE-NEXT:    mtvsrwz 35, 8
+; CHECK-BE-NEXT:    vperm 3, 5, 3, 4
+; CHECK-BE-NEXT:    mtvsrwz 37, 5
 ; CHECK-BE-NEXT:    vmrghw 2, 3, 2
-; CHECK-BE-NEXT:    mtvsrd 35, 6
-; CHECK-BE-NEXT:    vmrghh 3, 4, 3
-; CHECK-BE-NEXT:    mtvsrd 36, 4
-; CHECK-BE-NEXT:    vmrghh 4, 5, 4
+; CHECK-BE-NEXT:    mtvsrwz 35, 6
+; CHECK-BE-NEXT:    vperm 3, 5, 3, 4
+; CHECK-BE-NEXT:    mtvsrwz 37, 4
+; CHECK-BE-NEXT:    vperm 4, 0, 5, 4
 ; CHECK-BE-NEXT:    vmrghw 3, 4, 3
 ; CHECK-BE-NEXT:    xxmrghd 34, 35, 34
 ; CHECK-BE-NEXT:    blr
 entry:
 
 
   %vecext = extractelement <16 x i8> %a, i32 0
   %conv = sext i8 %vecext to i16