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Differential D107609

[PowerPC] Fix copy/paste error in scalar_to_vector patterns
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Authored by jsji on Aug 5 2021, 3:47 PM.

Details

Reviewers
shchenz
nemanjai
Group Reviewers
Restricted Project
Commits
rG6f84d94b9c56: [PowerPC] Fix copy/paste error in scalar_to_vector patterns
Summary

https://reviews.llvm.org/D100478 refactoring added a copy/paste error
for v8i16 patterns.

Diff Detail

Event Timeline

jsji created this revision.Aug 5 2021, 3:47 PM
Herald added subscribers: kbarton, hiraditya. · View Herald TranscriptAug 5 2021, 3:47 PM
jsji requested review of this revision.Aug 5 2021, 3:47 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 5 2021, 3:47 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B118284: Diff 364642.Aug 5 2021, 4:15 PM
shchenz accepted this revision.Aug 5 2021, 7:10 PM

LGTM. Thanks for catching this issue.

This revision is now accepted and ready to land.Aug 5 2021, 7:10 PM
This revision was landed with ongoing or failed builds.Aug 5 2021, 8:14 PM
Closed by commit rG6f84d94b9c56: [PowerPC] Fix copy/paste error in scalar_to_vector patterns (authored by jsji). · Explain Why
This revision was automatically updated to reflect the committed changes.
jsji added a commit: rG6f84d94b9c56: [PowerPC] Fix copy/paste error in scalar_to_vector patterns.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
2 lines
test/
CodeGen/
PowerPC/
2 lines

Diff 364684

llvm/lib/Target/PowerPC/PPCInstrVSX.td

Show First 20 Lines • Show All 3,541 Lines • ▼ Show 20 Lines
let Predicates = [HasVSX, HasDirectMove, IsBigEndian] in { let Predicates = [HasVSX, HasDirectMove, IsBigEndian] in {
// v16i8 scalar <-> vector conversions (BE) // v16i8 scalar <-> vector conversions (BE)
defm : ScalToVecWPermute< defm : ScalToVecWPermute<
v16i8, (i32 i32:$A), v16i8, (i32 i32:$A),
(SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64), (SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64),
(SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
defm : ScalToVecWPermute< defm : ScalToVecWPermute<
v8i16, (i32 i32:$A), v8i16, (i32 i32:$A),
(SUBREG_TO_REG (i64 1), MovesToVSR.BE_BYTE_0, sub_64), (SUBREG_TO_REG (i64 1), MovesToVSR.BE_HALF_0, sub_64),
(SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
defm : ScalToVecWPermute< defm : ScalToVecWPermute<
v4i32, (i32 i32:$A), v4i32, (i32 i32:$A),
(SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64), (SUBREG_TO_REG (i64 1), MovesToVSR.BE_WORD_0, sub_64),
(SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>; (SUBREG_TO_REG (i64 1), (MTVSRWZ $A), sub_64)>;
def : Pat<(v2i64 (scalar_to_vector i64:$A)), def : Pat<(v2i64 (scalar_to_vector i64:$A)),
(v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>; (v2i64 (SUBREG_TO_REG (i64 1), MovesToVSR.BE_DWORD_0, sub_64))>;
▲ Show 20 Lines • Show All 1,459 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll

Show All 24 Lines
; P8LE-LABEL: scalar_to_vector_half: ; P8LE-LABEL: scalar_to_vector_half:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lhz r3, 0(r3) ; P8LE-NEXT: lhz r3, 0(r3)
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: scalar_to_vector_half: ; P8BE-LABEL: scalar_to_vector_half:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lhz r3, 0(r3) ; P8BE-NEXT: lhz r3, 0(r3)
; P8BE-NEXT: sldi r3, r3, 56 ; P8BE-NEXT: sldi r3, r3, 48
; P8BE-NEXT: mtfprd f0, r3 ; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: mffprd r3, f0 ; P8BE-NEXT: mffprd r3, f0
; P8BE-NEXT: rldicl r3, r3, 8, 56 ; P8BE-NEXT: rldicl r3, r3, 8, 56
; P8BE-NEXT: blr ; P8BE-NEXT: blr
entry: entry:
%0 = bitcast i16* %ad to <2 x i8>* %0 = bitcast i16* %ad to <2 x i8>*
%1 = load <2 x i8>, <2 x i8>* %0, align 1 %1 = load <2 x i8>, <2 x i8>* %0, align 1
%2 = extractelement <2 x i8> %1, i32 0 %2 = extractelement <2 x i8> %1, i32 0
ret i8 %2 ret i8 %2
} }