Refactor: Simplify boolean conditional return statements in lib/Target/X86

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify boolean conditional return statements

[craig.topper]

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

228–229

Indent to start after the opening parenthese on the previous line.

lib/Target/X86/X86ISelLowering.cpp

2231

Push the negate through

3825

Push the negate through

lib/Target/X86/X86InstrInfo.cpp

2500–2501

Push negate through and fix indentation on second line.

4142–4143

Fix indentation

[LegalizeAdulthood]

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

228–229

Fixed.

lib/Target/X86/X86ISelLowering.cpp

2231

Fixed.

3825

Fixed.

lib/Target/X86/X86InstrInfo.cpp

2500–2501

Fixed.

4142–4143

Fixed.

[LegalizeAdulthood]

Update from comments, clang-format

[LegalizeAdulthood]

Update from latest.
I do not have commit access.

[bruno]

lib/Target/X86/X86ISelLowering.cpp

3358

The curly braces are useless now, you should also remove them.

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

bool Is16BitMemOperand(const MCInst &MI, unsigned Op,
                          const MCSubtargetInfo &STI) const {
     const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
     const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
     const MCOperand &Disp     = MI.getOperand(Op+X86::AddrDisp);
 
     if (is16BitMode(STI) && BaseReg.getReg() == 0 &&
         Disp.isImm() && Disp.getImm() < 0x10000)
       return true;
-    if ((BaseReg.getReg() != 0 &&
-         X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
+    return (BaseReg.getReg() != 0 &&
+            X86MCRegisterClasses[X86::GR16RegClassID].contains(
+                BaseReg.getReg())) ||
            (IndexReg.getReg() != 0 &&
-         X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
-      return true;
-    return false;
+            X86MCRegisterClasses[X86::GR16RegClassID].contains(
+                IndexReg.getReg()));
   }
 
   unsigned GetX86RegNum(const MCOperand &MO) const {
     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
   }
 
   // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
   // 0-7 and the difference between the 2 groups is given by the REX prefix.
static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
   return MCFixup::getKindForSize(Size, isPCRel);
 }
 
 /// Is32BitMemOperand - Return true if the specified instruction has
 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
   const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
   const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
 
-  if ((BaseReg.getReg() != 0 &&
-       X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
+  return (BaseReg.getReg() != 0 &&
+          X86MCRegisterClasses[X86::GR32RegClassID].contains(
+              BaseReg.getReg())) ||
          (IndexReg.getReg() != 0 &&
-       X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
-    return true;
-  return false;
+          X86MCRegisterClasses[X86::GR32RegClassID].contains(
+              IndexReg.getReg()));
 }
 
 /// Is64BitMemOperand - Return true if the specified instruction has
 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
 #ifndef NDEBUG
 static bool Is64BitMemOperand(const MCInst &MI, unsigned Op) {
   const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
   const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);

lib/Target/X86/X86FastISel.cpp

if (X86FastEmitCMoveSelect(RetVT, I))
     return true;
 
   // Try to use a sequence of SSE instructions to simulate a conditional move.
   if (X86FastEmitSSESelect(RetVT, I))
     return true;
 
   // Fall-back to pseudo conditional move instructions, which will be later
   // converted to control-flow.
-  if (X86FastEmitPseudoSelect(RetVT, I))
-    return true;
-
-  return false;
+  return X86FastEmitPseudoSelect(RetVT, I);
 }
 
 bool X86FastISel::X86SelectSIToFP(const Instruction *I) {
   // The target-independent selection algorithm in FastISel already knows how
   // to select a SINT_TO_FP if the target is SSE but not AVX.
   // Early exit if the subtarget doesn't have AVX.
   if (!Subtarget->hasAVX())
     return false;
case Intrinsic::stackprotector: {
     const Value *Op1 = II->getArgOperand(0); // The guard's value.
     const AllocaInst *Slot = cast<AllocaInst>(II->getArgOperand(1));
 
     MFI.setStackProtectorIndex(FuncInfo.StaticAllocaMap[Slot]);
 
     // Grab the frame index.
     X86AddressMode AM;
     if (!X86SelectAddress(Slot, AM)) return false;
-    if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
-    return true;
+    return X86FastEmitStore(PtrTy, Op1, AM);
   }
   case Intrinsic::dbg_declare: {
     const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
     X86AddressMode AM;
     assert(DI->getAddress() && "Null address should be checked earlier!");
     if (!X86SelectAddress(DI->getAddress(), AM))
       return false;
     const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);

lib/Target/X86/X86ISelDAGToDAG.cpp

if (!Chain.getNumOperands())
     return false;
   // Since we are not checking for AA here, conservatively abort if the chain
   // writes to memory. It's not safe to move the callee (a load) across a store.
   if (isa<MemSDNode>(Chain.getNode()) &&
       cast<MemSDNode>(Chain.getNode())->writeMem())
     return false;
   if (Chain.getOperand(0).getNode() == Callee.getNode())
     return true;
-  if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
+  return Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
          Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
-      Callee.getValue(1).hasOneUse())
-    return true;
-  return false;
+         Callee.getValue(1).hasOneUse();
 }
 
 void X86DAGToDAGISel::PreprocessISelDAG() {
   // OptForSize is used in pattern predicates that isel is matching.
   OptForSize = MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
 
   for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
        E = CurDAG->allnodes_end(); I != E; ) {
bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
                                           SDValue &PatternNodeWithChain) {
   if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
     PatternNodeWithChain = N.getOperand(0);
     if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
         PatternNodeWithChain.hasOneUse() &&
         IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
         IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
       LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
-      if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
-        return false;
-      return true;
+      return SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment);
     }
   }
 
   // Also handle the case where we explicitly require zeros in the top
   // elements.  This is a vector shuffle from the zero vector.
   if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
       // Check to see if the top elements are all zeros (or bitcast of zeros).
       N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
if (Chain == Load.getValue(1)) {
     }
 
     if (ChainCheck)
       // Make a new TokenFactor with all the other input chains except
       // for the load.
       InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
                                    MVT::Other, ChainOps);
   }
-  if (!ChainCheck)
-    return false;
-
-  return true;
+  return ChainCheck;
 }
 
 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
   if (Opc == X86ISD::DEC) {
     if (LdVT == MVT::i64) return X86::DEC64m;
     if (LdVT == MVT::i32) return X86::DEC32m;

lib/Target/X86/X86ISelLowering.cpp

 }
 
 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
   if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
     return false;
 
   CallSite CS(CI);
   CallingConv::ID CalleeCC = CS.getCallingConv();
-  if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
-    return false;
-
-  return true;
+  return IsTailCallConvention(CalleeCC) || IsCCallConvention(CalleeCC);
 }
 
 /// Return true if the function is being made into
 /// a tailcall target by changing its ABI.
 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
                                    bool GuaranteedTailCallOpt) {
   return GuaranteedTailCallOpt && IsTailCallConvention(CC);
 }
X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
 
   // Win64 functions have extra shadow space for argument homing. Don't do the
   // sibcall if the caller and callee have mismatched expectations for this
   // space.
   if (IsCalleeWin64 != IsCallerWin64)
     return false;
 
   if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
-    if (IsTailCallConvention(CalleeCC) && CCMatch)
-      return true;
-    return false;
+    return IsTailCallConvention(CalleeCC) && CCMatch;
   }
 
   // Look for obvious safe cases to perform tail call optimization that do not
   // require ABI changes. This is what gcc calls sibcall.
 
   // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
   // emit a special epilogue.
   const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
   if (RegInfo->needsStackRealignment(MF))
bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
   // bits boundary. We may also accept pretty large negative constants knowing
   // that all objects are in the positive half of address space.
   if (M == CodeModel::Small && Offset < 16*1024*1024)
     return true;
 
   // For kernel code model we know that all object resist in the negative half
   // of 32bits address space. We may not accept negative offsets, since they may
   // be just off and we may accept pretty large positive ones.
-  if (M == CodeModel::Kernel && Offset >= 0)
-    return true;
-
-  return false;
+  return M == CodeModel::Kernel && Offset >= 0;
 }
 
 /// isCalleePop - Determines whether the callee is required to pop its
 /// own arguments. Callee pop is necessary to support tail calls.
 bool X86::isCalleePop(CallingConv::ID CallingConv,
                       bool is64Bit, bool IsVarArg, bool TailCallOpt) {
   switch (CallingConv) {
   default:

 
 /// \brief Returns true if it is beneficial to convert a load of a constant
 /// to just the constant itself.
 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                           Type *Ty) const {
   assert(Ty->isIntegerTy());
 
   unsigned BitSize = Ty->getPrimitiveSizeInBits();
-  if (BitSize == 0 || BitSize > 64)
-    return false;
-  return true;
+  return BitSize != 0 && BitSize <= 64;
 }
 
 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
                                                 unsigned Index) const {
   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
     return false;
 
   return (Index == 0 || Index == ResVT.getVectorNumElements());

 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
   // This routine only handles 128-bit shufps.
   assert(Mask.size() == 4 && "Unsupported mask size!");
 
   // To lower with a single SHUFPS we need to have the low half and high half
   // each requiring a single input.
   if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
     return false;
-  if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
-    return false;
-
-  return true;
+  return Mask[2] == -1 || Mask[3] == -1 || (Mask[2] < 4) == (Mask[3] < 4);
 }
 
 /// \brief Lower a vector shuffle using the SHUFPS instruction.
 ///
 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
 /// It makes no assumptions about whether this is the *best* lowering, it simply
 /// uses it.
 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
if (Op.getResNo() == 1 &&
        Opc == X86ISD::UMUL ||
        Opc == X86ISD::INC ||
        Opc == X86ISD::DEC ||
        Opc == X86ISD::OR ||
        Opc == X86ISD::XOR ||
        Opc == X86ISD::AND))
     return true;
 
-  if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
-    return true;
-
-  return false;
+  return Op.getResNo() == 2 && Opc == X86ISD::UMUL;
 }
 
 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
   if (V.getOpcode() != ISD::TRUNCATE)
     return false;
 
   SDValue VOp0 = V.getOperand(0);
   unsigned InBits = VOp0.getValueSizeInBits();

lib/Target/X86/X86InstrInfo.cpp

bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
 
   // For both LEA64 and LEA32 the register already has essentially the right
   // type (32-bit or 64-bit) we may just need to forbid SP.
   if (Opc != X86::LEA64_32r) {
     NewSrc = SrcReg;
     isKill = Src.isKill();
     isUndef = Src.isUndef();
 
-    if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
-        !MF.getRegInfo().constrainRegClass(NewSrc, RC))
-      return false;
-
-    return true;
+    return !TargetRegisterInfo::isVirtualRegister(NewSrc) ||
+           MF.getRegInfo().constrainRegClass(NewSrc, RC);
   }
 
   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
   // another we need to add 64-bit registers to the final MI.
   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
     ImplicitOp = Src;
     ImplicitOp.setImplicit();
 
if (((FlagI->getOpcode() == X86::CMP64rr &&
         OI->getOpcode() == X86::SUB16rr)||
        (FlagI->getOpcode() == X86::CMP8rr &&
         OI->getOpcode() == X86::SUB8rr)) &&
       ((OI->getOperand(1).getReg() == SrcReg &&
         OI->getOperand(2).getReg() == SrcReg2) ||
        (OI->getOperand(1).getReg() == SrcReg2 &&
         OI->getOperand(2).getReg() == SrcReg)))
     return true;
 
-  if (((FlagI->getOpcode() == X86::CMP64ri32 &&
+  return ((FlagI->getOpcode() == X86::CMP64ri32 &&
            OI->getOpcode() == X86::SUB64ri32) ||
           (FlagI->getOpcode() == X86::CMP64ri8 &&
            OI->getOpcode() == X86::SUB64ri8) ||
           (FlagI->getOpcode() == X86::CMP32ri &&
            OI->getOpcode() == X86::SUB32ri) ||
           (FlagI->getOpcode() == X86::CMP32ri8 &&
            OI->getOpcode() == X86::SUB32ri8) ||
           (FlagI->getOpcode() == X86::CMP16ri &&
            OI->getOpcode() == X86::SUB16ri) ||
           (FlagI->getOpcode() == X86::CMP16ri8 &&
            OI->getOpcode() == X86::SUB16ri8) ||
           (FlagI->getOpcode() == X86::CMP8ri &&
            OI->getOpcode() == X86::SUB8ri)) &&
          OI->getOperand(1).getReg() == SrcReg &&
-      OI->getOperand(2).getImm() == ImmValue)
-    return true;
-  return false;
+         OI->getOperand(2).getImm() == ImmValue;
 }
 
 /// Check whether the definition can be converted
 /// to remove a comparison against zero.
 inline static bool isDefConvertible(MachineInstr *MI) {
   switch (MI->getOpcode()) {
   default: return false;
 

lib/Target/X86/X86TargetTransformInfo.cpp

 }
 
 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, int Consecutive) {
   int DataWidth = DataTy->getPrimitiveSizeInBits();
   
   // Todo: AVX512 allows gather/scatter, works with strided and random as well
   if ((DataWidth < 32) || (Consecutive == 0))
     return false;
-  if (ST->hasAVX512() || ST->hasAVX2()) 
-    return true;
-  return false;
+  return ST->hasAVX512() || ST->hasAVX2();
 }
 
 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, int Consecutive) {
   return isLegalMaskedLoad(DataType, Consecutive);
 }