Refactor: Simplify boolean conditional return statements in lib/Target/SystemZ

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify conditonal return statements

[craig.topper]

lib/Target/SystemZ/SystemZInstrInfo.cpp

506

Can this just be on the previous line and still fit 80 columns?

[LegalizeAdulthood]

lib/Target/SystemZ/SystemZInstrInfo.cpp

506

Fixed.

[LegalizeAdulthood]

clang-format

[uweigand]

Some of these changes make sense to me, but a number of others don't appear to make the code more readable.

The latter are typically of the form:

if (cond1)
  return false;
if (cond2)
  return false;
...
if (condN)
  return false;

return true;

In a sequence like this (which is written this way to be able to easily add/remove further conditions as appropriate, it doesn't really improve maintainability to just transform the *last* condition.

[LegalizeAdulthood]

Update from latest.
Update from comments.
I do not have commit access.

[LegalizeAdulthood]

In D9986#201999, @uweigand wrote:

Some of these changes make sense to me, but a number of others don't appear to make the code more readable.

The latter are typically of the form:

if (cond1)
  return false;
if (cond2)
  return false;
...
if (condN)
  return false;

return true;

In a sequence like this (which is written this way to be able to easily add/remove further conditions as appropriate, it doesn't really improve maintainability to just transform the *last* condition.

This should not be a problem anymore.

[uweigand]

LGTM.

lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

if (Disp) {
     unsigned IndexOpcode = Index->getOpcode();
     if (IndexOpcode == ISD::SIGN_EXTEND ||
         IndexOpcode == ISD::SIGN_EXTEND_INREG)
       return false;
   }
 
   // Don't use LA for two-operand addition if either operand is only
   // used once.  The addition instructions are better in that case.
-  if (Base->hasOneUse())
-    return false;
-
-  return true;
+  return !Base->hasOneUse();
 }
 
 // Return true if Addr is suitable for AM, updating AM if so.
 bool SystemZDAGToDAGISel::selectAddress(SDValue Addr,
                                         SystemZAddressingMode &AM) const {
   // Start out assuming that the address will need to be loaded separately,
   // then try to extend it as much as we can.
   AM.Base = Addr;

lib/Target/SystemZ/SystemZISelLowering.cpp

 #include "SystemZGenCallingConv.inc"
 
 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
                                                      Type *ToType) const {
   return isTruncateFree(FromType, ToType);
 }
 
 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
-  if (!CI->isTailCall())
-    return false;
-  return true;
+  return CI->isTailCall();
 }
 
 // We do not yet support 128-bit single-element vector types.  If the user
 // attempts to use such types as function argument or return type, prefer
 // to error out instead of emitting code violating the ABI.
 static void VerifyVectorType(MVT VT, EVT ArgVT) {
   if (ArgVT.isVector() && !VT.isVector())
     report_fatal_error("Unsupported vector argument or return type");
if (!ConstOp1)
       return true;
     // The unsigned memory-immediate instructions can handle 16-bit
     // unsigned integers.
     if (C.ICmpType != SystemZICMP::SignedOnly &&
         isUInt<16>(ConstOp1->getZExtValue()))
       return false;
     // The signed memory-immediate instructions can handle 16-bit
     // signed integers.
-    if (C.ICmpType != SystemZICMP::UnsignedOnly &&
-        isInt<16>(ConstOp1->getSExtValue()))
-      return false;
-    return true;
+    return !(C.ICmpType != SystemZICMP::UnsignedOnly &&
+             isInt<16>(ConstOp1->getSExtValue()));
   }
 
   // Try to promote the use of CGFR and CLGFR.
   unsigned Opcode0 = C.Op0.getOpcode();
   if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
     return true;
   if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
     return true;
-  if (C.ICmpType != SystemZICMP::SignedOnly &&
-      Opcode0 == ISD::AND &&
+  return C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::AND &&
          C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
-      cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
-    return true;
-
-  return false;
+         cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() ==
+             0xffffffff;
 }
 
 // Return a version of comparison CC mask CCMask in which the LT and GT
 // actions are swapped.
 static unsigned reverseCCMask(unsigned CCMask) {
   return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
           (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
           (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |

lib/Target/SystemZ/SystemZInstrInfo.cpp

 
 bool
 SystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare,
                                        unsigned SrcReg, unsigned SrcReg2,
                                        int Mask, int Value,
                                        const MachineRegisterInfo *MRI) const {
   assert(!SrcReg2 && "Only optimizing constant comparisons so far");
   bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
-  if (Value == 0 &&
-      !IsLogical &&
-      removeIPMBasedCompare(Compare, SrcReg, MRI, &RI))
-    return true;
-  return false;
+  return Value == 0 && !IsLogical &&
+         removeIPMBasedCompare(Compare, SrcReg, MRI, &RI);
 }
 
 // If Opcode is a move that has a conditional variant, return that variant,
 // otherwise return 0.
 static unsigned getConditionalMove(unsigned Opcode) {
   switch (Opcode) {
   case SystemZ::LR:  return SystemZ::LOCR;
   case SystemZ::LGR: return SystemZ::LOCGR;
   default:           return 0;
   }
 }
 
 bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
   unsigned Opcode = MI->getOpcode();
-  if (STI.hasLoadStoreOnCond() &&
-      getConditionalMove(Opcode))
-    return true;
-  return false;
+  return STI.hasLoadStoreOnCond() && getConditionalMove(Opcode);
 }
 
 bool SystemZInstrInfo::
 isProfitableToIfCvt(MachineBasicBlock &MBB,
                     unsigned NumCycles, unsigned ExtraPredCycles,
                     const BranchProbability &Probability) const {
   // For now only convert single instructions.
   return NumCycles == 1;
 }