Refactor: Simplify boolean conditional return statements in lib/Target/Arm

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify boolean conditional return statements.

[craig.topper]

lib/Target/ARM/ARMFrameLowering.cpp

113

This should really be aligned right after the opening parenthese on the previous line. That's really probably true of many of these patches, but it looks particularly bad here.

lib/Target/ARM/ARMISelLowering.cpp

4942

Push negate through

4966

Push negate through

10055

Push negate through and use != and &&. Align second line after the return.

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1263

Push the negate through this expression and all the similar ones below.

[LegalizeAdulthood]

lib/Target/ARM/ARMFrameLowering.cpp

113

Fixed.

I forgot to run clang-format on these before posting them; I'm doing that now.

lib/Target/ARM/ARMISelLowering.cpp

4942

Fixed.

4966

Fixed.

10055

Fixed.

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1263

Fixed.

[LegalizeAdulthood]

Update from comments, clang-format

[LegalizeAdulthood]

Update to latest

lib/Target/ARM/A15SDOptimizer.cpp

bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
   // INSERT_SUBREG or REG_SEQUENCE.
   if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
     return true;
 
   if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
                                            &ARM::SPRRegClass))
     return true;
 
-  if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
-    return true;
-
-  return false;
+  return MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass);
 }
 
 // Looks through full copies to get the instruction that defines the input
 // operand for MI.
 MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
   if (!MI->isFullCopy())
     return MI;
   if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))

lib/Target/ARM/ARMBaseInstrInfo.cpp

bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
   if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
       !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
          Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
         (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
          Load2->getMachineOpcode() == ARM::t2LDRBi8)))
     return false;  // FIXME: overly conservative?
 
   // Four loads in a row should be sufficient.
-  if (NumLoads >= 3)
-    return false;
-
-  return true;
+  return NumLoads < 3;
 }
 
 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
                                             const MachineBasicBlock *MBB,
                                             const MachineFunction &MF) const {
   // Debug info is never a scheduling boundary. It's necessary to be explicit
   // due to the special treatment of IT instructions below, otherwise a
   // dbg_value followed by an IT will result in the IT instruction being
bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
   // Don't attempt to schedule around any instruction that defines
   // a stack-oriented pointer, as it's unlikely to be profitable. This
   // saves compile time, because it doesn't require every single
   // stack slot reference to depend on the instruction that does the
   // modification.
   // Calls don't actually change the stack pointer, even if they have imp-defs.
   // No ARM calling conventions change the stack pointer. (X86 calling
   // conventions sometimes do).
-  if (!MI->isCall() && MI->definesRegister(ARM::SP))
-    return true;
-
-  return false;
+  return !MI->isCall() && MI->definesRegister(ARM::SP);
 }
 
 bool ARMBaseInstrInfo::
 isProfitableToIfCvt(MachineBasicBlock &MBB,
                     unsigned NumCycles, unsigned ExtraPredCycles,
                     const BranchProbability &Probability) const {
   if (!NumCycles)
     return false;
if ((CmpI->getOpcode() == ARM::CMPrr ||
       (OI->getOpcode() == ARM::SUBrr ||
        OI->getOpcode() == ARM::t2SUBrr) &&
       ((OI->getOperand(1).getReg() == SrcReg &&
         OI->getOperand(2).getReg() == SrcReg2) ||
        (OI->getOperand(1).getReg() == SrcReg2 &&
         OI->getOperand(2).getReg() == SrcReg)))
     return true;
 
-  if ((CmpI->getOpcode() == ARM::CMPri ||
+  return (CmpI->getOpcode() == ARM::CMPri ||
        CmpI->getOpcode() == ARM::t2CMPri) &&
       (OI->getOpcode() == ARM::SUBri ||
        OI->getOpcode() == ARM::t2SUBri) &&
       OI->getOperand(1).getReg() == SrcReg &&
-      OI->getOperand(2).getImm() == ImmValue)
-    return true;
-  return false;
+      OI->getOperand(2).getImm() == ImmValue;
 }
 
 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
 /// comparison into one that sets the zero bit in the flags register;
 /// Remove a redundant Compare instruction if an earlier instruction can set the
 /// flags in the same way as Compare.
 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the

 }
 
 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
   if (MI->getNumOperands() < 4)
     return true;
   unsigned ShOpVal = MI->getOperand(3).getImm();
   unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
   // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
-  if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
+  return (ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
       ((ShImm == 1 || ShImm == 2) &&
-       ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
-    return true;
-
-  return false;
+       ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl);
 }
 
 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
     const MachineInstr &MI, unsigned DefIdx,
     SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
   assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
 

lib/Target/ARM/ARMBaseRegisterInfo.cpp

bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
   // reserve a Base Pointer.
   if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
     // Conservatively estimate whether the negative offset from the frame
     // pointer will be sufficient to reach. If a function has a smallish
     // frame, it's less likely to have lots of spills and callee saved
     // space, so it's all more likely to be within range of the frame pointer.
     // If it's wrong, the scavenger will still enable access to work, it just
     // won't be optimal.
-    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
-      return false;
-    return true;
+    return !(AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128);
   }
 
   return false;
 }
 
 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
   const MachineRegisterInfo *MRI = &MF.getRegInfo();
   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
   // immediate.
   if ((Offset & (Scale-1)) != 0)
     return false;
 
   if (isSigned && Offset < 0)
     Offset = -Offset;
 
   unsigned Mask = (1 << NumBits) - 1;
-  if ((unsigned)Offset <= Mask * Scale)
-    return true;
-
-  return false;
+  return (unsigned)Offset <= Mask * Scale;
 }
 
 void
 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                          int SPAdj, unsigned FIOperandNum,
                                          RegScavenger *RS) const {
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();

lib/Target/ARM/ARMFastISel.cpp

bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
   return TLI.isTypeLegal(VT);
 }
 
 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
   if (isTypeLegal(Ty, VT)) return true;
 
   // If this is a type than can be sign or zero-extended to a basic operation
   // go ahead and accept it now.
-  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
-    return true;
-
-  return false;
+  return VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16;
 }
 
 // Computes the address to get to an object.
 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
   // Some boilerplate from the X86 FastISel.
   const User *U = nullptr;
   unsigned Opcode = Instruction::UserOp1;
   if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
bool ARMFastISel::SelectStore(const Instruction *I) {
   SrcReg = getRegForValue(Op0);
   if (SrcReg == 0) return false;
 
   // See if we can handle this address.
   Address Addr;
   if (!ARMComputeAddress(I->getOperand(1), Addr))
     return false;
 
-  if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
-    return false;
-  return true;
+  return ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment());
 }
 
 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
   switch (Pred) {
     // Needs two compares...
     case CmpInst::FCMP_ONE:
     case CmpInst::FCMP_UEQ:
     default:

lib/Target/ARM/ARMFrameLowering.cpp

static bool isCSRestore(MachineInstr *MI,
   if (isPopOpcode(MI->getOpcode())) {
     // The first two operands are predicates. The last two are
     // imp-def and imp-use of SP. Check everything in between.
     for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
       if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
         return false;
     return true;
   }
-  if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
+  return (MI->getOpcode() == ARM::LDR_POST_IMM ||
        MI->getOpcode() == ARM::LDR_POST_REG ||
        MI->getOpcode() == ARM::t2LDR_POST) &&
       isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
-      MI->getOperand(1).getReg() == ARM::SP)
-    return true;
-
-  return false;
+      MI->getOperand(1).getReg() == ARM::SP;
 }
 
 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator &MBBI, DebugLoc dl,
                                  const ARMBaseInstrInfo &TII, unsigned DestReg,
                                  unsigned SrcReg, int NumBytes,
                                  unsigned MIFlags = MachineInstr::NoFlags,
                                  ARMCC::CondCodes Pred = ARMCC::AL,

lib/Target/ARM/ARMISelLowering.cpp

static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
   WhichResult = (M[0] == 0 ? 0 : 1);
   for (unsigned i = 0; i != NumElts; ++i) {
     if (M[i] < 0) continue; // ignore UNDEF indices
     if ((unsigned) M[i] != 2 * i + WhichResult)
       return false;
   }
 
   // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
-  if (VT.is64BitVector() && EltSz == 32)
-    return false;
-
-  return true;
+  return !(VT.is64BitVector() && EltSz == 32);
 }
 
 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
   unsigned EltSz = VT.getVectorElementType().getSizeInBits();
   if (EltSz == 64)
     return false;
 
   unsigned Half = VT.getVectorNumElements() / 2;
   WhichResult = (M[0] == 0 ? 0 : 1);
   for (unsigned j = 0; j != 2; ++j) {
     unsigned Idx = WhichResult;
     for (unsigned i = 0; i != Half; ++i) {
       int MIdx = M[i + j * Half];
       if (MIdx >= 0 && (unsigned) MIdx != Idx)
         return false;
       Idx += 2;
     }
   }
 
   // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
-  if (VT.is64BitVector() && EltSz == 32)
-    return false;
-
-  return true;
+  return !(VT.is64BitVector() && EltSz == 32);
 }
 
 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
   unsigned EltSz = VT.getVectorElementType().getSizeInBits();
   if (EltSz == 64)
     return false;
 
   unsigned NumElts = VT.getVectorNumElements();
   WhichResult = (M[0] == 0 ? 0 : 1);
   unsigned Idx = WhichResult * NumElts / 2;
   for (unsigned i = 0; i != NumElts; i += 2) {
     if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
         (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
       return false;
     Idx += 1;
   }
 
   // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
-  if (VT.is64BitVector() && EltSz == 32)
-    return false;
-
-  return true;
+  return !(VT.is64BitVector() && EltSz == 32);
 }
 
 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
   unsigned EltSz = VT.getVectorElementType().getSizeInBits();
   if (EltSz == 64)
     return false;
 
   unsigned NumElts = VT.getVectorNumElements();
   WhichResult = (M[0] == 0 ? 0 : 1);
   unsigned Idx = WhichResult * NumElts / 2;
   for (unsigned i = 0; i != NumElts; i += 2) {
     if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
         (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
       return false;
     Idx += 1;
   }
 
   // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
-  if (VT.is64BitVector() && EltSz == 32)
-    return false;
-
-  return true;
+  return !(VT.is64BitVector() && EltSz == 32);
 }
 
 /// \return true if this is a reverse operation on an vector.
 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
   unsigned NumElts = VT.getVectorNumElements();
   // Make sure the mask has the right size.
   if (NumElts != M.size())
       return false;
static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
   return true;
 }
 
 /// isSignExtended - Check if a node is a vector value that is sign-extended
 /// or a constant BUILD_VECTOR with sign-extended elements.
 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
   if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
     return true;
-  if (isExtendedBUILD_VECTOR(N, DAG, true))
-    return true;
-  return false;
+  return isExtendedBUILD_VECTOR(N, DAG, true);
 }
 
 /// isZeroExtended - Check if a node is a vector value that is zero-extended
 /// or a constant BUILD_VECTOR with zero-extended elements.
 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
   if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
     return true;
-  if (isExtendedBUILD_VECTOR(N, DAG, false))
-    return true;
-  return false;
+  return isExtendedBUILD_VECTOR(N, DAG, false);
 }
 
 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
   if (OrigVT.getSizeInBits() >= 64)
     return OrigVT;
 
   assert(OrigVT.isSimple() && "Expecting a simple value type");
 
bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
   // instruction.
   // If there's more than one user instruction, the loadext is desirable no
   // matter what.  There can be two uses by the same instruction.
   if (ExtVal->use_empty() ||
       !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
     return true;
 
   SDNode *U = *ExtVal->use_begin();
-  if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
-       U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
-    return false;
-
-  return true;
+  return !(U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
+       U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL);
 }
 
 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
   if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
     return false;
 
   if (!isTypeLegal(EVT::getEVT(Ty1)))
     return false;

 
 /// \brief Returns true if it is beneficial to convert a load of a constant
 /// to just the constant itself.
 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                           Type *Ty) const {
   assert(Ty->isIntegerTy());
 
   unsigned Bits = Ty->getPrimitiveSizeInBits();
-  if (Bits == 0 || Bits > 32)
-    return false;
-  return true;
+  return !(Bits == 0 || Bits > 32);
 }
 
 bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; }
 
 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
                                         ARM_MB::MemBOpt Domain) const {
   Module *M = Builder.GetInsertBlock()->getParent()->getParent();
 

lib/Target/ARM/ARMSubtarget.cpp

ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
                                  Reloc::Model RelocM) const {
   if (RelocM == Reloc::Static)
     return false;
 
   bool isDecl = GV->isDeclarationForLinker();
 
   if (!isTargetMachO()) {
     // Extra load is needed for all externally visible.
-    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
-      return false;
-    return true;
+    return !(GV->hasLocalLinkage() || GV->hasHiddenVisibility());
   } else {
     if (RelocM == Reloc::PIC_) {
       // If this is a strong reference to a definition, it is definitely not
       // through a stub.
       if (!isDecl && !GV->isWeakForLinker())
         return false;
 
       // Unless we have a symbol with hidden visibility, we have to go through a
       // normal $non_lazy_ptr stub because this symbol might be resolved late.
       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
         return true;
 
       // If symbol visibility is hidden, we have a stub for common symbol
       // references and external declarations.
-      if (isDecl || GV->hasCommonLinkage())
-        // Hidden $non_lazy_ptr reference.
-        return true;
-
-      return false;
+      return isDecl || GV->hasCommonLinkage();
     } else {
       // If this is a strong reference to a definition, it is definitely not
       // through a stub.
       if (!isDecl && !GV->isWeakForLinker())
         return false;
 
       // Unless we have a symbol with hidden visibility, we have to go through a
       // normal $non_lazy_ptr stub because this symbol might be resolved late.

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

bool isAddrMode5() const {
     if (Memory.OffsetRegNum) return false;
     // Immediate offset in range [-1020, 1020] and a multiple of 4.
     if (!Memory.OffsetImm) return true;
     int64_t Val = Memory.OffsetImm->getValue();
     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
       Val == INT32_MIN;
   }
   bool isMemTBB() const {
-    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
-        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
-      return false;
-    return true;
+    return !(!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
+        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0);
   }
   bool isMemTBH() const {
-    if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
+    return !(!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
-        Memory.Alignment != 0 )
-      return false;
-    return true;
+        Memory.Alignment != 0);
   }
   bool isMemRegOffset() const {
-    if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
-      return false;
-    return true;
+    return !(!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0);
   }
   bool isT2MemRegOffset() const {
     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
         Memory.Alignment != 0)
       return false;
     // Only lsl #{0, 1, 2, 3} allowed.
     if (Memory.ShiftType == ARM_AM::no_shift)
       return true;
-    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
-      return false;
-    return true;
+    return !(Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3);
   }
   bool isMemThumbRR() const {
     // Thumb reg+reg addressing is simple. Just two registers, a base and
     // an offset. No shifts, negations or any other complicating factors.
     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
       return false;
     return isARMLowRegister(Memory.BaseRegNum) &&
bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
 
 
 
   // Register-register 'add/sub' for thumb does not have a cc_out operand
   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
   // right, this will result in better diagnostics (which operand is off)
   // anyway.
-  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
+  return isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
       (Operands.size() == 5 || Operands.size() == 6) &&
       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
        (Operands.size() == 6 &&
-        static_cast<ARMOperand &>(*Operands[5]).isImm())))
-    return true;
-
-  return false;
+        static_cast<ARMOperand &>(*Operands[5]).isImm()));
 }
 
 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
                                               OperandVector &Operands) {
   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
   unsigned RegIdx = 3;
   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
       static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const {
   case ARM::tCBZ:
     return ARM::tHINT;
   case ARM::tCBNZ:
     return ARM::tHINT;
   }
 }
 
 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
-  if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
-    return true;
-  return false;
+  return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
 }
 
 bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                                          const MCRelaxableFragment *DF,
                                          const MCAsmLayout &Layout) const {
   switch ((unsigned)Fixup.getKind()) {
   case ARM::fixup_arm_thumb_br: {
     // Relaxing tB to t2B. tB has a signed 12-bit displacement with the

lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp

bool ARMMachObjectWriter::requiresExternRelocation(MachObjectWriter *Writer,
   // BL/BLX also use external relocations when an internal relocation
   // would result in the target being out of range. This gives the linker
   // enough information to generate a branch island.
   const MCSectionData &SymSD = Asm.getSectionData(S.getSection());
   Value += Writer->getSectionAddress(&SymSD);
   Value -= Writer->getSectionAddress(Fragment.getParent());
   // If the resultant value would be out of range for an internal relocation,
   // use an external instead.
-  if (Value > Range || Value < -(Range + 1))
-    return true;
-  return false;
+  return Value > Range || Value < -(Range + 1);
 }
 
 void ARMMachObjectWriter::RecordRelocation(MachObjectWriter *Writer,
                                            MCAssembler &Asm,
                                            const MCAsmLayout &Layout,
                                            const MCFragment *Fragment,
                                            const MCFixup &Fixup, MCValue Target,
                                            uint64_t &FixedValue) {

lib/Target/ARM/Thumb2SizeReduction.cpp

if (Entry.Special)
     return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
 
   // Try to transform to a 16-bit two-address instruction.
   if (Entry.NarrowOpc2 &&
       ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
     return true;
 
   // Try to transform to a 16-bit non-two-address instruction.
-  if (Entry.NarrowOpc1 &&
-      ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
-    return true;
-
-  return false;
+  return Entry.NarrowOpc1 &&
+      ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
 }
 
 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
   bool Modified = false;
 
   // Yes, CPSR could be livein.
   bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
   MachineInstr *BundleMI = nullptr;