GlobalISel: Check for powers of 2 for inverse funnel shift lowering

[arsenm]

Summary

This doesn't make a practical difference since it would only be broken
if a target actually had a legal non-power-of-2 inverse shift.

[foad]

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

5354

No, it's the "WithInverse" lowering that might fail.

[arsenm]

Fix being totally wrong

[foad]

LGTM, thanks!

[arsenm]

14b03b4aadee8e6adcbb8c674c8d8f770b1bc4d6

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

LegalizerHelper::lowerFunnelShiftWithInverse(MachineInstr &MI) {
   Register Dst = MI.getOperand(0).getReg();
   Register X = MI.getOperand(1).getReg();
   Register Y = MI.getOperand(2).getReg();
   Register Z = MI.getOperand(3).getReg();
   LLT Ty = MRI.getType(Dst);
   LLT ShTy = MRI.getType(Z);
 
   unsigned BW = Ty.getScalarSizeInBits();
+
+  if (!isPowerOf2_32(BW))
+    return UnableToLegalize;
+
   const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL;
   unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL;
 
   if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) {
     // fshl X, Y, Z -> fshr X, Y, -Z
     // fshr X, Y, Z -> fshl X, Y, -Z
     auto Zero = MIRBuilder.buildConstant(ShTy, 0);
     Z = MIRBuilder.buildSub(Ty, Zero, Z).getReg(0);
LegalizerHelper::lowerFunnelShift(MachineInstr &MI) {
   // G_FSHL: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
   // G_FSHR: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
   Register Dst = MI.getOperand(0).getReg();
   LLT Ty = MRI.getType(Dst);
   LLT ShTy = MRI.getType(MI.getOperand(3).getReg());
 
   bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL;
   unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL;
-  if (LI.getAction({RevOpcode, {Ty, ShTy}}).Action == Lower)
-    return lowerFunnelShiftAsShifts(MI);
+  if (LI.getAction({RevOpcode, {Ty, ShTy}}).Action == Lower) {
+    // This only works for powers of 2, fallback to shifts if it fails.
+    LegalizerHelper::LegalizeResult Result = lowerFunnelShiftAsShifts(MI);
+    if (Result != UnableToLegalize)
+      return Result;
+  }
+
   return lowerFunnelShiftWithInverse(MI);
 }
 
 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
 // representation.
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
   Register Dst = MI.getOperand(0).getReg();