[MC][ARM] add .w suffixes for ORN/ORNS T1

[nickdesaulniers]

Summary

See also:
F5.1.128 ORN, ORNS (register) T1 shift or rotate by value variant
of the Arm ARM.

Link: https://github.com/ClangBuiltLinux/linux/issues/1309

[DavidSpickett]

llvm/test/MC/ARM/basic-thumb2-instructions.s

1884

Initially I thought that we shouldn't be allowing the flag setting S variant for v7 since it's not listed in the documentation. However that's just because on v7 they always set the flags so S or not it's the same thing.

1890

Add a .w check for one or more of the shift variants and the immediate.

[nickdesaulniers]

• add support and test coverage for immediates, and shifted register operands

llvm/lib/Target/ARM/ARMInstrThumb2.td

def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
     let msb{4-0} = imm{9-5};
     let lsb{4-0} = imm{4-0};
   }
 }
 
 defm t2ORN  : T2I_bin_irs<0b0011, "orn",
                           IIC_iBITi, IIC_iBITr, IIC_iBITsi,
                           BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">;
+def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $imm",
+   (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $Rm",
+   (t2ORNrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $ShiftedRm",
+   (t2ORNrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
 
 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
 /// unary operation that produces a value. These are predicable and can be
 /// changed to modify CPSR.
 multiclass T2I_un_irs<bits<4> opcod, string opc,
                      InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
                       PatFrag opnode,
                       bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> {

llvm/test/MC/ARM/basic-thumb2-instructions.s

 
 @ CHECK: nop.w                          @ encoding: [0xaf,0xf3,0x00,0x80]
 
 
 @------------------------------------------------------------------------------
 @ ORN
 @------------------------------------------------------------------------------
         orn r4, r5, #0xf000
+        orn.w r4, r5, #0xf000
         orn r4, r5, r6
+        orn.w r4, r5, r6
         orns r4, r5, r6
+        orns.w r4, r5, r6
         orn r4, r5, r6, lsl #5
+        orn.w r4, r5, r6, lsl #5
         orns r4, r5, r6, lsr #5
         orn r4, r5, r6, lsr #5
         orns r4, r5, r6, asr #5
         orn r4, r5, r6, ror #5
 
 @ CHECK: orn  r4, r5, #61440          @ encoding: [0x65,0xf4,0x70,0x44]
+@ CHECK: orn  r4, r5, #61440          @ encoding: [0x65,0xf4,0x70,0x44]
+@ CHECK: orn  r4, r5, r6              @ encoding: [0x65,0xea,0x06,0x04]
 @ CHECK: orn  r4, r5, r6              @ encoding: [0x65,0xea,0x06,0x04]
 @ CHECK: orns  r4, r5, r6              @ encoding: [0x75,0xea,0x06,0x04]
+@ CHECK: orns  r4, r5, r6              @ encoding: [0x75,0xea,0x06,0x04]
+@ CHECK: orn  r4, r5, r6, lsl #5      @ encoding: [0x65,0xea,0x46,0x14]
 @ CHECK: orn  r4, r5, r6, lsl #5      @ encoding: [0x65,0xea,0x46,0x14]
 @ CHECK: orns  r4, r5, r6, lsr #5      @ encoding: [0x75,0xea,0x56,0x14]
 @ CHECK: orn  r4, r5, r6, lsr #5      @ encoding: [0x65,0xea,0x56,0x14]
 @ CHECK: orns  r4, r5, r6, asr #5      @ encoding: [0x75,0xea,0x66,0x14]
 @ CHECK: orn  r4, r5, r6, ror #5      @ encoding: [0x65,0xea,0x76,0x14]
 
 
 @------------------------------------------------------------------------------