[GlobalISel] Fix crash in RBS with a non-generic IMPLICIT_DEF.

[aemerson]

Summary

This may occur when swifterror codegen in the translator generates these, but we shouldn't try to handle them since they should have regclasses anyway.

rdar://75784009

[aemerson]

Update x86 RBS test. For some reason it was using the non-generic IMPLICIT_DEF when it should be using the generic one.

[arsenm]

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

723

How did this get past the isPreIselOpcode check (same with asm)?

[aemerson]

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

723

Because the line above is short circuit AND, so it never calls isPreISelOpcode(). These opcodes are defined before the generic ones, so the isTargetSpecificOpcode(MI) call returns false.

[paquette]

LGTM. Kind of weird that we create normal IMPLICIT_DEFs in the IRTranslator though? I guess it's code shared with SDAG.

[arsenm]

In D99287#2648935, @paquette wrote:

LGTM. Kind of weird that we create normal IMPLICIT_DEFs in the IRTranslator though? I guess it's code shared with SDAG.

Definitely shouldn't be doing that. No optimizations are going to recognize it

[aemerson]

In D99287#2648977, @arsenm wrote:

In D99287#2648935, @paquette wrote:

LGTM. Kind of weird that we create normal IMPLICIT_DEFs in the IRTranslator though? I guess it's code shared with SDAG.

Definitely shouldn't be doing that. No optimizations are going to recognize it

This falls under “already selected” code, and should have regclasses. The intention AFAIK is for GISel to allow targets to preselect code at any point in the pipeline.

[arsenm]

In D99287#2649182, @aemerson wrote:

In D99287#2648977, @arsenm wrote:

In D99287#2648935, @paquette wrote:

LGTM. Kind of weird that we create normal IMPLICIT_DEFs in the IRTranslator though? I guess it's code shared with SDAG.

Definitely shouldn't be doing that. No optimizations are going to recognize it

This falls under “already selected” code, and should have regclasses. The intention AFAIK is for GISel to allow targets to preselect code at any point in the pipeline.

It should work, but it doesn't mean it's the best idea to use (especially for a "generic" instruction that has a direct "generic generic" instruction)

llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp

for (MachineBasicBlock::iterator MII = MBB->begin(), End = MBB->end();
       // registers/regclasses
       if (MI.isInlineAsm())
         continue;
 
       // Ignore debug info.
       if (MI.isDebugInstr())
         continue;
 
+      // Ignore IMPLICIT_DEF which must have a regclass.
+      if (MI.isImplicitDef())
+        continue;
+
       if (!assignInstr(MI)) {
         reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect",
                            "unable to map instruction", MI);
         return false;
       }
 
       // It's possible the mapping changed control flow, and moved the following
       // instruction to a new block, so figure out the new parent.

llvm/test/CodeGen/AArch64/GlobalISel/implicit_def_rbs_crash.mir

+# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+# Check we don't crash given an non-generic implicit_def. These may
+# come from swifterror handling in the translator.
+# CHECK: IMPLICIT_DEF
+---
+name:            implicit_def_crash
+alignment:       4
+legalized:       true
+regBankSelected: false
+selected:        false
+failedISel:      false
+registers:
+  - { id: 0, class: gpr64all, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+  - { id: 2, class: gpr64all, preferred-register: '' }
+  - { id: 3, class: gpr64all, preferred-register: '' }
+body:             |
+  bb.1:
+    %0:gpr64all = IMPLICIT_DEF
+
+...

llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir

registers:
   - { id: 4, class: _ }
   - { id: 5, class: _ }
   - { id: 6, class: _ }
   - { id: 7, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     ; FAST-LABEL: name: test_mul_gpr
-    ; FAST: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
-    ; FAST: [[DEF1:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
-    ; FAST: [[DEF2:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF
-    ; FAST: [[DEF3:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF
+    ; FAST: [[DEF:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
+    ; FAST: [[DEF1:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
+    ; FAST: [[DEF2:%[0-9]+]]:gpr(s16) = G_IMPLICIT_DEF
+    ; FAST: [[DEF3:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF
     ; FAST: [[MUL:%[0-9]+]]:gpr(s64) = G_MUL [[DEF]], [[DEF]]
     ; FAST: [[MUL1:%[0-9]+]]:gpr(s32) = G_MUL [[DEF1]], [[DEF1]]
     ; FAST: [[MUL2:%[0-9]+]]:gpr(s16) = G_MUL [[DEF2]], [[DEF2]]
     ; FAST: [[MUL3:%[0-9]+]]:gpr(s8) = G_MUL [[DEF3]], [[DEF3]]
     ; FAST: RET 0
     ; GREEDY-LABEL: name: test_mul_gpr
-    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
-    ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
-    ; GREEDY: [[DEF2:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF
-    ; GREEDY: [[DEF3:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF
+    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
+    ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
+    ; GREEDY: [[DEF2:%[0-9]+]]:gpr(s16) = G_IMPLICIT_DEF
+    ; GREEDY: [[DEF3:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF
     ; GREEDY: [[MUL:%[0-9]+]]:gpr(s64) = G_MUL [[DEF]], [[DEF]]
     ; GREEDY: [[MUL1:%[0-9]+]]:gpr(s32) = G_MUL [[DEF1]], [[DEF1]]
     ; GREEDY: [[MUL2:%[0-9]+]]:gpr(s16) = G_MUL [[DEF2]], [[DEF2]]
     ; GREEDY: [[MUL3:%[0-9]+]]:gpr(s8) = G_MUL [[DEF3]], [[DEF3]]
     ; GREEDY: RET 0
-    %0(s64) = IMPLICIT_DEF
-    %1(s32) = IMPLICIT_DEF
-    %2(s16) = IMPLICIT_DEF
-    %3(s8)  = IMPLICIT_DEF
+    %0(s64) = G_IMPLICIT_DEF
+    %1(s32) = G_IMPLICIT_DEF
+    %2(s16) = G_IMPLICIT_DEF
+    %3(s8)  = G_IMPLICIT_DEF
     %4(s64) = G_MUL %0, %0
     %5(s32) = G_MUL %1, %1
     %6(s16) = G_MUL %2, %2
     %7(s8)  = G_MUL %3, %3
     RET 0
 ...
 ---
 name:            test_add_float
registers:
   - { id: 3, class: _, preferred-register: '' }
 liveins:
 fixedStack:
 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     ; FAST-LABEL: name: test_fsub_float
-    ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
-    ; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
+    ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
+    ; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
     ; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; FAST: [[FSUB:%[0-9]+]]:vecr(s32) = G_FSUB [[COPY]], [[COPY1]]
     ; FAST: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; FAST: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; FAST: [[FSUB1:%[0-9]+]]:vecr(s64) = G_FSUB [[COPY2]], [[COPY3]]
     ; FAST: RET 0
     ; GREEDY-LABEL: name: test_fsub_float
-    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
-    ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
+    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
+    ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
     ; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; GREEDY: [[FSUB:%[0-9]+]]:vecr(s32) = G_FSUB [[COPY]], [[COPY1]]
     ; GREEDY: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; GREEDY: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; GREEDY: [[FSUB1:%[0-9]+]]:vecr(s64) = G_FSUB [[COPY2]], [[COPY3]]
     ; GREEDY: RET 0
-    %0(s32) = IMPLICIT_DEF
-    %2(s64) = IMPLICIT_DEF
+    %0(s32) = G_IMPLICIT_DEF
+    %2(s64) = G_IMPLICIT_DEF
     %1(s32) = G_FSUB %0, %0
     %3(s64) = G_FSUB %2, %2
     RET 0
 
 ...
 ---
 name:            test_fmul_float
 alignment:       16
 legalized:       true
 regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
   - { id: 2, class: _, preferred-register: '' }
   - { id: 3, class: _, preferred-register: '' }
 liveins:
 fixedStack:
 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     ; FAST-LABEL: name: test_fmul_float
-    ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
-    ; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
+    ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
+    ; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
     ; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; FAST: [[FMUL:%[0-9]+]]:vecr(s32) = G_FMUL [[COPY]], [[COPY1]]
     ; FAST: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; FAST: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; FAST: [[FMUL1:%[0-9]+]]:vecr(s64) = G_FMUL [[COPY2]], [[COPY3]]
     ; FAST: RET 0
     ; GREEDY-LABEL: name: test_fmul_float
-    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
-    ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
+    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
+    ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
     ; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; GREEDY: [[FMUL:%[0-9]+]]:vecr(s32) = G_FMUL [[COPY]], [[COPY1]]
     ; GREEDY: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; GREEDY: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; GREEDY: [[FMUL1:%[0-9]+]]:vecr(s64) = G_FMUL [[COPY2]], [[COPY3]]
     ; GREEDY: RET 0
-    %0(s32) = IMPLICIT_DEF
-    %2(s64) = IMPLICIT_DEF
+    %0(s32) = G_IMPLICIT_DEF
+    %2(s64) = G_IMPLICIT_DEF
     %1(s32) = G_FMUL %0, %0
     %3(s64) = G_FMUL %2, %2
     RET 0
 
 ...
 ---
 name:            test_fdiv_float
 alignment:       16
 legalized:       true
 regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
   - { id: 2, class: _, preferred-register: '' }
   - { id: 3, class: _, preferred-register: '' }
 liveins:
 fixedStack:
 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     ; FAST-LABEL: name: test_fdiv_float
-    ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
-    ; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
+    ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
+    ; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
     ; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; FAST: [[FDIV:%[0-9]+]]:vecr(s32) = G_FDIV [[COPY]], [[COPY1]]
     ; FAST: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; FAST: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; FAST: [[FDIV1:%[0-9]+]]:vecr(s64) = G_FDIV [[COPY2]], [[COPY3]]
     ; FAST: RET 0
     ; GREEDY-LABEL: name: test_fdiv_float
-    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
-    ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
+    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
+    ; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
     ; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
     ; GREEDY: [[FDIV:%[0-9]+]]:vecr(s32) = G_FDIV [[COPY]], [[COPY1]]
     ; GREEDY: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; GREEDY: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
     ; GREEDY: [[FDIV1:%[0-9]+]]:vecr(s64) = G_FDIV [[COPY2]], [[COPY3]]
     ; GREEDY: RET 0
-    %0(s32) = IMPLICIT_DEF
-    %2(s64) = IMPLICIT_DEF
+    %0(s32) = G_IMPLICIT_DEF
+    %2(s64) = G_IMPLICIT_DEF
     %1(s32) = G_FDIV %0, %0
     %3(s64) = G_FDIV %2, %2
     RET 0
 
 ...
 ---
 name:            test_add_v4i32
 alignment:       16

 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     ; FAST-LABEL: name: trunc_check
-    ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
+    ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
     ; FAST: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[DEF]](s32)
     ; FAST: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[DEF]](s32)
     ; FAST: [[TRUNC2:%[0-9]+]]:gpr(s16) = G_TRUNC [[DEF]](s32)
     ; FAST: RET 0
     ; GREEDY-LABEL: name: trunc_check
-    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
+    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
     ; GREEDY: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[DEF]](s32)
     ; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[DEF]](s32)
     ; GREEDY: [[TRUNC2:%[0-9]+]]:gpr(s16) = G_TRUNC [[DEF]](s32)
     ; GREEDY: RET 0
-    %0(s32) = IMPLICIT_DEF
+    %0(s32) = G_IMPLICIT_DEF
     %1(s1) = G_TRUNC %0(s32)
     %2(s8) = G_TRUNC %0(s32)
     %3(s16) = G_TRUNC %0(s32)
     RET 0
 
 ...
 ---
 name:            test_gep
 legalized:       true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     ; FAST-LABEL: name: test_gep
-    ; FAST: [[DEF:%[0-9]+]]:gpr(p0) = IMPLICIT_DEF
+    ; FAST: [[DEF:%[0-9]+]]:gpr(p0) = G_IMPLICIT_DEF
     ; FAST: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 20
     ; FAST: [[PTR_ADD:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
     ; FAST: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 20
     ; FAST: [[PTR_ADD1:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C1]](s64)
     ; FAST: RET 0
     ; GREEDY-LABEL: name: test_gep
-    ; GREEDY: [[DEF:%[0-9]+]]:gpr(p0) = IMPLICIT_DEF
+    ; GREEDY: [[DEF:%[0-9]+]]:gpr(p0) = G_IMPLICIT_DEF
     ; GREEDY: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 20
     ; GREEDY: [[PTR_ADD:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
     ; GREEDY: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 20
     ; GREEDY: [[PTR_ADD1:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C1]](s64)
     ; GREEDY: RET 0
-    %0(p0) = IMPLICIT_DEF
+    %0(p0) = G_IMPLICIT_DEF
     %1(s32) = G_CONSTANT i32 20
     %2(p0) = G_PTR_ADD %0, %1(s32)
     %3(s64) = G_CONSTANT i64 20
     %4(p0) = G_PTR_ADD %0, %3(s64)
     RET 0
 
 ...
 ---
registers:
   - { id: 1, class: _, preferred-register: '' }
 liveins:
 fixedStack:
 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     ; FAST-LABEL: name: test_xor_i8
-    ; FAST: [[DEF:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF
+    ; FAST: [[DEF:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF
     ; FAST: [[XOR:%[0-9]+]]:gpr(s8) = G_XOR [[DEF]], [[DEF]]
     ; FAST: $al = COPY [[XOR]](s8)
     ; FAST: RET 0, implicit $al
     ; GREEDY-LABEL: name: test_xor_i8
-    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF
+    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF
     ; GREEDY: [[XOR:%[0-9]+]]:gpr(s8) = G_XOR [[DEF]], [[DEF]]
     ; GREEDY: $al = COPY [[XOR]](s8)
     ; GREEDY: RET 0, implicit $al
-    %0(s8) = IMPLICIT_DEF
+    %0(s8) = G_IMPLICIT_DEF
     %1(s8) = G_XOR %0, %0
     $al = COPY %1(s8)
     RET 0, implicit $al
 
 ...
 ---
 name:            test_or_i16
 alignment:       16
 legalized:       true
 regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
 liveins:
 fixedStack:
 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     ; FAST-LABEL: name: test_or_i16
-    ; FAST: [[DEF:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF
+    ; FAST: [[DEF:%[0-9]+]]:gpr(s16) = G_IMPLICIT_DEF
     ; FAST: [[OR:%[0-9]+]]:gpr(s16) = G_OR [[DEF]], [[DEF]]
     ; FAST: $ax = COPY [[OR]](s16)
     ; FAST: RET 0, implicit $ax
     ; GREEDY-LABEL: name: test_or_i16
-    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF
+    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s16) = G_IMPLICIT_DEF
     ; GREEDY: [[OR:%[0-9]+]]:gpr(s16) = G_OR [[DEF]], [[DEF]]
     ; GREEDY: $ax = COPY [[OR]](s16)
     ; GREEDY: RET 0, implicit $ax
-    %0(s16) = IMPLICIT_DEF
+    %0(s16) = G_IMPLICIT_DEF
     %1(s16) = G_OR %0, %0
     $ax = COPY %1(s16)
     RET 0, implicit $ax
 
 ...
 ---
 name:            test_and_i32
 alignment:       16
 legalized:       true
 regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
 liveins:
 fixedStack:
 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     ; FAST-LABEL: name: test_and_i32
-    ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
+    ; FAST: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
     ; FAST: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[DEF]], [[DEF]]
     ; FAST: $eax = COPY [[AND]](s32)
     ; FAST: RET 0, implicit $eax
     ; GREEDY-LABEL: name: test_and_i32
-    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
+    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
     ; GREEDY: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[DEF]], [[DEF]]
     ; GREEDY: $eax = COPY [[AND]](s32)
     ; GREEDY: RET 0, implicit $eax
-    %0(s32) = IMPLICIT_DEF
+    %0(s32) = G_IMPLICIT_DEF
     %1(s32) = G_AND %0, %0
     $eax = COPY %1(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_and_i64
 alignment:       16
 legalized:       true
 regBankSelected: false
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
 liveins:
 fixedStack:
 stack:
 constants:
 body:             |
   bb.1 (%ir-block.0):
     ; FAST-LABEL: name: test_and_i64
-    ; FAST: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
+    ; FAST: [[DEF:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
     ; FAST: [[AND:%[0-9]+]]:gpr(s64) = G_AND [[DEF]], [[DEF]]
     ; FAST: $rax = COPY [[AND]](s64)
     ; FAST: RET 0, implicit $rax
     ; GREEDY-LABEL: name: test_and_i64
-    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
+    ; GREEDY: [[DEF:%[0-9]+]]:gpr(s64) = G_IMPLICIT_DEF
     ; GREEDY: [[AND:%[0-9]+]]:gpr(s64) = G_AND [[DEF]], [[DEF]]
     ; GREEDY: $rax = COPY [[AND]](s64)
     ; GREEDY: RET 0, implicit $rax
-    %0(s64) = IMPLICIT_DEF
+    %0(s64) = G_IMPLICIT_DEF
     %1(s64) = G_AND %0, %0
     $rax = COPY %1(s64)
     RET 0, implicit $rax
 
 ...
 ---
 name:            test_global_ptrv
 alignment:       16