[ARM] Enable UpperBound unrolling for all loops

[dmgreen]

Summary

This UpperBound unrolling was already enabled so long as a series of conditions in ARMTTIImpl::getUnrollingPreferences pass. This just always enables it as it can help fully unroll loops that would not otherwise pass those tests.

[SjoerdMeijer]

llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll

78

I find this test change a bit difficult to read. What exactly is changing here?
This first check here s just a check to see if the loop executes at all, but from the other changes below I find it difficult to see if this gets now unrolled or if there are other changes.

[dmgreen]

llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll

78

It is getting fully unrolled, which combined with the array values becoming constant and known, managed to simplify most of the unrolled code away. I was just using it as an example of something that will now be unrolled beneficially.

[SjoerdMeijer]

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

2121

Looking at this again, I am now confused why we always want to enable this while....

2130

... here we check of Oz and Os. So we could bail here, but still set UpperBound to true. Is that correct or what we want?

llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll

78

Ah, okay, got it, cheers.

[dmgreen]

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

2130

The loop unroller will already handle Oz and Os correctly, and I think these values are already the same as the defaults it has.

The loop unroller will only unroll loops if it thinks the size will be less after unrolling than the size of the loop. So very rarely, and usually only for loops with 1 or 2 iterations.

UpperBound should not change that and should be safe to always enable.

[SjoerdMeijer]

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

2130

Okidoki, thanks, LGTM.

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

bool ARMTTIImpl::emitGetActiveLaneMask() const {
   // Intrinsic @llvm.get.active.lane.mask is supported.
   // It is used in the MVETailPredication pass, which requires the number of
   // elements processed by this vector loop to setup the tail-predicated
   // loop.
   return true;
 }
 void ARMTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                          TTI::UnrollingPreferences &UP) {
+  // Enable Upper bound unrolling universally, not dependant upon the conditions
+  // below.
+  UP.UpperBound = true;
+
   // Only currently enable these preferences for M-Class cores.
   if (!ST->isMClass())
     return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP);
 
   // Disable loop unrolling for Oz and Os.
   UP.OptSizeThreshold = 0;
   UP.PartialOptSizeThreshold = 0;
   if (L->getHeader()->getParent()->hasOptSize())
     return;
 
   SmallVector<BasicBlock*, 4> ExitingBlocks;
   L->getExitingBlocks(ExitingBlocks);
   LLVM_DEBUG(dbgs() << "Loop has:\n"
                     << "Blocks: " << L->getNumBlocks() << "\n"
                     << "Exit blocks: " << ExitingBlocks.size() << "\n");
 
for (auto &I : *BB) {
         getUserCost(&I, Operands, TargetTransformInfo::TCK_SizeAndLatency);
     }
   }
 
   LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n");
 
   UP.Partial = true;
   UP.Runtime = true;
-  UP.UpperBound = true;
   UP.UnrollRemainder = true;
   UP.DefaultUnrollRuntimeCount = 4;
   UP.UnrollAndJam = true;
   UP.UnrollAndJamInnerLoopThreshold = 60;
 
   // Force unrolling small loops can be very useful because of the branch
   // taken cost of the backedge.
   if (Cost < 12)

llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll

while.end:                                        ; preds = %if.end, %entry
   ret void
 }
 
 ; Larger test that is still fully unrolled, thanks in part to the constant data.
 @data = internal constant [50 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50], align 4
 define i32 @test2(i32 %l86) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[FOR_BODY_I_I:%.*]]
-; CHECK:       for.body.i.i:
-; CHECK-NEXT:    [[I_0137_I_I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD_I_3_I:%.*]], [[FOR_BODY_I_3_I:%.*]] ]
-; CHECK-NEXT:    [[ADD_I_I:%.*]] = or i32 [[I_0137_I_I]], 1
-; CHECK-NEXT:    [[TMP0:%.*]] = zext i32 [[ADD_I_I]] to i64
-; CHECK-NEXT:    [[ARRAYIDX_I_I:%.*]] = getelementptr inbounds [50 x i32], [50 x i32]* @data, i64 0, i64 [[TMP0]]
-; CHECK-NEXT:    [[L93:%.*]] = load i32, i32* [[ARRAYIDX_I_I]], align 4
-; CHECK-NEXT:    [[CMP1_I_I:%.*]] = icmp sgt i32 [[L93]], [[L86:%.*]]
-; CHECK-NEXT:    br i1 [[CMP1_I_I]], label [[LAND_LHS_TRUE_I_I:%.*]], label [[FOR_INC_I_I:%.*]]
-; CHECK:       land.lhs.true.i.i:
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[I_0137_I_I]] to i64
-; CHECK-NEXT:    [[ARRAYIDX2_I_I:%.*]] = getelementptr inbounds [50 x i32], [50 x i32]* @data, i64 0, i64 [[TMP1]]
-; CHECK-NEXT:    [[L94:%.*]] = load i32, i32* [[ARRAYIDX2_I_I]], align 4
-; CHECK-NEXT:    [[CMP3_NOT_I_I:%.*]] = icmp sgt i32 [[L94]], [[L86]]
-; CHECK-NEXT:    br i1 [[CMP3_NOT_I_I]], label [[FOR_INC_I_I]], label [[FOR_END_I_IF_END8_I_CRIT_EDGE_I:%.*]]
-; CHECK:       for.inc.i.i:
-; CHECK-NEXT:    [[EXITCOND_NOT_I_I:%.*]] = icmp eq i32 [[ADD_I_I]], 25
-; CHECK-NEXT:    br i1 [[EXITCOND_NOT_I_I]], label [[FOR_END_I_IF_END8_I_CRIT_EDGE_I]], label [[FOR_BODY_I_1_I:%.*]]
-; CHECK:       for.body.i.1.i:
-; CHECK-NEXT:    [[ADD_I_1_I:%.*]] = or i32 [[I_0137_I_I]], 2
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[ADD_I_1_I]] to i64
-; CHECK-NEXT:    [[ARRAYIDX_I_1_I:%.*]] = getelementptr inbounds [50 x i32], [50 x i32]* @data, i64 0, i64 [[TMP2]]
-; CHECK-NEXT:    [[L345:%.*]] = load i32, i32* [[ARRAYIDX_I_1_I]], align 4
-; CHECK-NEXT:    [[CMP1_I_1_I:%.*]] = icmp sgt i32 [[L345]], [[L86]]
-; CHECK-NEXT:    [[CMP1_I_1_I_NOT:%.*]] = xor i1 [[CMP1_I_1_I]], true
-; CHECK-NEXT:    [[BRMERGE:%.*]] = or i1 [[CMP1_I_I]], [[CMP1_I_1_I_NOT]]
-; CHECK-NEXT:    br i1 [[BRMERGE]], label [[FOR_INC_I_1_I:%.*]], label [[FOR_END_I_I:%.*]]
-; CHECK:       for.inc.i.1.i:
-; CHECK-NEXT:    [[ADD_I_2_I:%.*]] = or i32 [[I_0137_I_I]], 3
-; CHECK-NEXT:    [[TMP3:%.*]] = zext i32 [[ADD_I_2_I]] to i64
-; CHECK-NEXT:    [[ARRAYIDX_I_2_I:%.*]] = getelementptr inbounds [50 x i32], [50 x i32]* @data, i64 0, i64 [[TMP3]]
-; CHECK-NEXT:    [[L346:%.*]] = load i32, i32* [[ARRAYIDX_I_2_I]], align 4
-; CHECK-NEXT:    [[CMP1_I_2_I:%.*]] = icmp sgt i32 [[L346]], [[L86]]
-; CHECK-NEXT:    [[CMP1_I_2_I_NOT:%.*]] = xor i1 [[CMP1_I_2_I]], true
-; CHECK-NEXT:    [[BRMERGE1:%.*]] = or i1 [[CMP1_I_1_I]], [[CMP1_I_2_I_NOT]]
-; CHECK-NEXT:    br i1 [[BRMERGE1]], label [[FOR_BODY_I_3_I]], label [[FOR_END_I_IF_END8_I_CRIT_EDGE_I]]
-; CHECK:       for.body.i.3.i:
-; CHECK-NEXT:    [[ADD_I_3_I]] = add nuw nsw i32 [[I_0137_I_I]], 4
-; CHECK-NEXT:    [[TMP4:%.*]] = zext i32 [[ADD_I_3_I]] to i64
-; CHECK-NEXT:    [[ARRAYIDX_I_3_I:%.*]] = getelementptr inbounds [50 x i32], [50 x i32]* @data, i64 0, i64 [[TMP4]]
-; CHECK-NEXT:    [[L347:%.*]] = load i32, i32* [[ARRAYIDX_I_3_I]], align 4
-; CHECK-NEXT:    [[CMP1_I_3_I:%.*]] = icmp sle i32 [[L347]], [[L86]]
-; CHECK-NEXT:    [[BRMERGE2:%.*]] = or i1 [[CMP1_I_3_I]], [[CMP1_I_2_I]]
-; CHECK-NEXT:    br i1 [[BRMERGE2]], label [[FOR_BODY_I_I]], label [[FOR_END_I_I]]
-; CHECK:       for.end.i.i:
-; CHECK-NEXT:    [[I_0_LCSSA_I_I:%.*]] = phi i32 [ [[ADD_I_I]], [[FOR_BODY_I_1_I]] ], [ [[ADD_I_2_I]], [[FOR_BODY_I_3_I]] ]
-; CHECK-NEXT:    [[CMP5_I_I:%.*]] = icmp eq i32 [[I_0_LCSSA_I_I]], 25
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[CMP5_I_I]], i32 2, i32 0
-; CHECK-NEXT:    br label [[FOR_END_I_IF_END8_I_CRIT_EDGE_I]]
+; CHECK-NEXT:    [[L86_OFF:%.*]] = add i32 [[L86:%.*]], -1
+; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[L86_OFF]], 24
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[FOR_END_I_IF_END8_I_CRIT_EDGE_I:%.*]], label [[FOR_INC_I_3_I_5:%.*]]
 ; CHECK:       for.end.i.if.end8.i_crit_edge.i:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 0, [[FOR_INC_I_1_I]] ], [ 0, [[LAND_LHS_TRUE_I_I]] ], [ 1, [[FOR_INC_I_I]] ], [ [[SPEC_SELECT]], [[FOR_END_I_I]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    ret i32 0
+; CHECK:       for.inc.i.3.i.5:
+; CHECK-NEXT:    [[DOTNOT30:%.*]] = icmp ne i32 [[L86]], 25
+; CHECK-NEXT:    [[SPEC_SELECT24:%.*]] = zext i1 [[DOTNOT30]] to i32
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT24]]
 ;
 entry:
   br label %for.body.i.i
 
 for.body.i.i:                                     ; preds = %for.body.i.i.preheader, %for.inc.i.3.i
   %i.0137.i.i = phi i32 [ %add.i.3.i, %for.inc.i.3.i ], [ 0, %entry ]
   %add.i.i = or i32 %i.0137.i.i, 1
   %arrayidx.i.i = getelementptr inbounds i32, i32* getelementptr inbounds ([50 x i32], [50 x i32]* @data, i32 0, i32 0), i32 %add.i.i