[AMDGPU] Reserve ELF code

[t-tye]

Summary

Reserve AMD GPU ELF machine code 0x040.

Minor AMDGPUUsage format consistency change.

[kzhuravl]

probably update the title to reflect there is more than one change in the commit?

llvm/include/llvm/BinaryFormat/ELF.h

736–737

move this to line 736. make line 737 empty.

[kzhuravl]

you also should add reserved number to docs.

[t-tye]

Address review comments.

[t-tye]

Address review comments.

[kzhuravl]

Thanks.

llvm/include/llvm/BinaryFormat/ELF.h

736–737

move this to line 736. make line 737 empty.

llvm/docs/AMDGPUUsage.rst

.. table:: AMDGPU ``EF_AMDGPU_MACH`` Values
      ``EF_AMDGPU_MACH_AMDGCN_GFX1032``    0x038      ``gfx1032``
      ``EF_AMDGPU_MACH_AMDGCN_GFX1033``    0x039      ``gfx1033``
      ``EF_AMDGPU_MACH_AMDGCN_GFX602``     0x03a      ``gfx602``
      ``EF_AMDGPU_MACH_AMDGCN_GFX705``     0x03b      ``gfx705``
      ``EF_AMDGPU_MACH_AMDGCN_GFX805``     0x03c      ``gfx805``
      *reserved*                           0x03d      Reserved.
      *reserved*                           0x03e      Reserved.
      ``EF_AMDGPU_MACH_AMDGCN_GFX90A``     0x03f      ``gfx90a``
+     *reserved*                           0x040      Reserved.
      ==================================== ========== =============================
 
 Sections
 --------
 
 An AMDGPU target ELF code object has the standard ELF sections which include:
 
   .. table:: AMDGPU ELF Sections
23:15   9 bits  GRANULATED_LDS_SIZE             Must be 0.
                                                      directly to
                                                      ``COMPUTE_PGM_RSRC2.LDS_SIZE``.
 
                                                      Amount of group segment
                                                      (LDS) to allocate for each
                                                      work-group. Granularity is
                                                      device specific:
 
-                                                     GFX6:
+                                                     GFX6
                                                        roundup(lds-size / (64 * 4))
-                                                     GFX7-GFX10:
+                                                     GFX7-GFX10
                                                        roundup(lds-size / (128 * 4))
 
      24      1 bit   ENABLE_EXCEPTION_IEEE_754_FP    Wavefront starts execution
                      _INVALID_OPERATION              with specified exceptions
                                                      enabled.
 
                                                      Used by CP to set up
                                                      ``COMPUTE_PGM_RSRC2.EXCP_EN``

llvm/include/llvm/BinaryFormat/ELF.h

 //===- llvm/BinaryFormat/ELF.h - ELF constants and structures ---*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
enum : unsigned {
   EF_AMDGPU_MACH_R600_RESERVED_FIRST = 0x011,
   EF_AMDGPU_MACH_R600_RESERVED_LAST = 0x01f,
 
   // First/last R600-based processors.
   EF_AMDGPU_MACH_R600_FIRST = EF_AMDGPU_MACH_R600_R600,
   EF_AMDGPU_MACH_R600_LAST = EF_AMDGPU_MACH_R600_TURKS,
 
   // AMDGCN-based processors.
   EF_AMDGPU_MACH_AMDGCN_GFX600        = 0x020,
   EF_AMDGPU_MACH_AMDGCN_GFX601        = 0x021,
   EF_AMDGPU_MACH_AMDGCN_GFX700        = 0x022,
   EF_AMDGPU_MACH_AMDGCN_GFX701        = 0x023,
   EF_AMDGPU_MACH_AMDGCN_GFX702        = 0x024,
   EF_AMDGPU_MACH_AMDGCN_GFX703        = 0x025,
   EF_AMDGPU_MACH_AMDGCN_GFX704        = 0x026,
   EF_AMDGPU_MACH_AMDGCN_RESERVED_0X27 = 0x027,
   EF_AMDGPU_MACH_AMDGCN_GFX801        = 0x028,
   EF_AMDGPU_MACH_AMDGCN_GFX802        = 0x029,
   EF_AMDGPU_MACH_AMDGCN_GFX803        = 0x02a,
   EF_AMDGPU_MACH_AMDGCN_GFX810        = 0x02b,
   EF_AMDGPU_MACH_AMDGCN_GFX900        = 0x02c,
   EF_AMDGPU_MACH_AMDGCN_GFX902        = 0x02d,
   EF_AMDGPU_MACH_AMDGCN_GFX904        = 0x02e,
   EF_AMDGPU_MACH_AMDGCN_GFX906        = 0x02f,
   EF_AMDGPU_MACH_AMDGCN_GFX908        = 0x030,
   EF_AMDGPU_MACH_AMDGCN_GFX909        = 0x031,
   EF_AMDGPU_MACH_AMDGCN_GFX90C        = 0x032,
   EF_AMDGPU_MACH_AMDGCN_GFX1010       = 0x033,
   EF_AMDGPU_MACH_AMDGCN_GFX1011       = 0x034,
   EF_AMDGPU_MACH_AMDGCN_GFX1012       = 0x035,
   EF_AMDGPU_MACH_AMDGCN_GFX1030       = 0x036,
   EF_AMDGPU_MACH_AMDGCN_GFX1031       = 0x037,
   EF_AMDGPU_MACH_AMDGCN_GFX1032       = 0x038,
   EF_AMDGPU_MACH_AMDGCN_GFX1033       = 0x039,
   EF_AMDGPU_MACH_AMDGCN_GFX602        = 0x03a,
   EF_AMDGPU_MACH_AMDGCN_GFX705        = 0x03b,
   EF_AMDGPU_MACH_AMDGCN_GFX805        = 0x03c,
   EF_AMDGPU_MACH_AMDGCN_RESERVED_0X3D = 0x03d,
   EF_AMDGPU_MACH_AMDGCN_RESERVED_0X3E = 0x03e,
   EF_AMDGPU_MACH_AMDGCN_GFX90A        = 0x03f,
 
+  EF_AMDGPU_MACH_AMDGCN_RESERVED_0X40 = 0x040,
   // First/last AMDGCN-based processors.
   EF_AMDGPU_MACH_AMDGCN_FIRST = EF_AMDGPU_MACH_AMDGCN_GFX600,
   EF_AMDGPU_MACH_AMDGCN_LAST = EF_AMDGPU_MACH_AMDGCN_GFX90A,
 
   // Indicates if the "xnack" target feature is enabled for all code contained
   // in the object.
   EF_AMDGPU_XNACK = 0x100,
   // Indicates if the "sram-ecc" target feature is enabled for all code