[AArch64][GlobalISel][RegBankSelect] Improve rbs of G_BUILD_VECTOR when fed by fp values.

[aemerson]

Summary

This is actually two changes. One is to avoid copies when fp values are fed into a build_vector, without being able to tell from the opcode.

The other is that build_vectors are also marked as only defining FP, since they produce vector results.

[paquette]

LGTM

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
                                             const TargetRegisterInfo &TRI,
                                             unsigned Depth) const {
   switch (MI.getOpcode()) {
   case AArch64::G_DUP:
   case TargetOpcode::G_SITOFP:
   case TargetOpcode::G_UITOFP:
   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
   case TargetOpcode::G_INSERT_VECTOR_ELT:
+  case TargetOpcode::G_BUILD_VECTOR:
+  case TargetOpcode::G_BUILD_VECTOR_TRUNC:
     return true;
   default:
     break;
   }
   return hasFPConstraints(MI, MRI, TRI, Depth);
 }
 
 const RegisterBankInfo::InstructionMapping &
case TargetOpcode::G_BUILD_VECTOR: {
     unsigned DefOpc = DefMI->getOpcode();
     const LLT SrcTy = MRI.getType(VReg);
     if (all_of(MI.operands(), [&](const MachineOperand &Op) {
           return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() ==
                                    TargetOpcode::G_CONSTANT;
         }))
       break;
     if (isPreISelGenericFloatingPointOpcode(DefOpc) ||
-        SrcTy.getSizeInBits() < 32) {
+        SrcTy.getSizeInBits() < 32 ||
+        getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank) {
       // Have a floating point op.
       // Make sure every operand gets mapped to a FPR register class.
       unsigned NumOperands = MI.getNumOperands();
       for (unsigned Idx = 0; Idx < NumOperands; ++Idx)
         OpRegBankIdx[Idx] = PMI_FirstFPR;
     }
     break;
   }

llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-build-vector.mir

bb.1:
     %7:_(s8) = G_CONSTANT i8 22
     %8:_(s8) = G_CONSTANT i8 19
     %9:_(s8) = G_CONSTANT i8 55
     %0:_(<16 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8), %4(s8), %5(s8), %1(s8), %2(s8), %6(s8), %7(s8), %5(s8), %1(s8), %8(s8), %3(s8), %4(s8), %5(s8), %9(s8)
     $q0 = COPY %0(<16 x s8>)
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            fed_by_fp_load
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x0' }
+  - { reg: '$x1' }
+  - { reg: '$x2' }
+  - { reg: '$s0' }
+frameInfo:
+  maxAlignment:    1
+body:             |
+  bb.1:
+    liveins: $s0, $x0, $x1, $x2
+
+    ; CHECK-LABEL: name: fed_by_fp_load
+    ; CHECK: liveins: $s0, $x0, $x1, $x2
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
+    ; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 328
+    ; CHECK: [[PTR_ADD:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+    ; CHECK: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 344
+    ; CHECK: [[PTR_ADD1:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
+    ; CHECK: [[LOAD:%[0-9]+]]:fpr(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4)
+    ; CHECK: [[LOAD1:%[0-9]+]]:fpr(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load 4)
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:fpr(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
+    ; CHECK: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
+    ; CHECK: RET_ReallyLR implicit $d0
+    %0:_(p0) = COPY $x0
+    %4:_(s64) = G_CONSTANT i64 328
+    %5:_(p0) = G_PTR_ADD %0, %4(s64)
+    %6:_(s64) = G_CONSTANT i64 344
+    %7:_(p0) = G_PTR_ADD %0, %6(s64)
+    %15:_(s32) = G_LOAD %5(p0) :: (load 4)
+    %20:_(s32) = G_LOAD %7(p0) :: (load 4)
+    %21:_(<2 x s32>) = G_BUILD_VECTOR %15(s32), %20(s32)
+    $d0 = COPY %21(<2 x s32>)
+    RET_ReallyLR implicit $d0
+
+...