[AMDGPU] Set threshold for regbanks reassign pass

[rampitec]

Summary

This is to limit compile time. I did experiments with some
inputs and found that compile time keeps reasonable for this
pass if we have less than 100000 virtual registers and then
starts to explode somewhere between 100000 and 150000.

[rampitec]

Fixed debug output.

[alex-t]

LGTM

[arsenm]

llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

54

This seems like a pretty low threshold

[rampitec]

llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

54

It is. Here is what happens when we have ~150000 vregs:

147.0184 ( 75.8%)   0.0000 (  0.0%)  147.0184 ( 75.5%)  147.1465 ( 75.5%)  GCN RegBank Reassign
14.0944 (  7.3%)   0.0800 ( 12.7%)  14.1743 (  7.3%)  14.1812 (  7.3%)  Machine Instruction Scheduler

And when we have ~100000 the pass is not even visible at the top of -time-passes. So unless there are better ideas we need to limit it.

One idea I have is to use kind of heuristic to account not only for the number of vregs, but for the number of registers allocated. What makes it slow is checkInterference() for every probed register at every conflict. Obviously time will be proportional to the number of overlapping LIs at the point of conflict and that more or less can be approximated by the number of registers, at least in a most "fat" portion of a program. Moreover, more overlapping LIs we have less chances we will be able to find a combination of registers to resolve a conflict.

If there would be a cheap way to estimate register pressure at a given instruction we could skip individual instructions from search, but I am afraid RPT is not a cheap way.

[arsenm]

llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

668

Can you redo this search process in terms of regunits instead?

[rampitec]

llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

668

I will need to supply a physreg for VRM at the end. Plus all these isAllocatable() et all checks are not for reg units.

[arsenm]

llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

668

VRM should be using regunits internally. It does have LiveRegMatrix::checkRegUnitInterference. Overall we need to rewrite everything considering registers to operate on regunits instead (including reframing reserved registers in terms of reserved regunits)

[arsenm]

llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

668

I guess checkRegUnitInterference is part of the implementation, but that just means you're repeating that multiple times by scanning over all of the registers in tuple classes

llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

 
 using namespace llvm;
 
 static cl::opt<unsigned> VerifyStallCycles("amdgpu-verify-regbanks-reassign",
   cl::desc("Verify stall cycles in the regbanks reassign pass"),
   cl::value_desc("0|1|2"),
   cl::init(0), cl::Hidden);
 
+// Threshold to keep compile time reasonable.
+static cl::opt<unsigned> VRegThresh("amdgpu-regbanks-reassign-threshold",
+  cl::desc("Max number of vregs to run the regbanks reassign pass"),
+  cl::init(100000), cl::Hidden);
+
 #define DEBUG_TYPE "amdgpu-regbanks-reassign"
 
 #define NUM_VGPR_BANKS 4
 #define NUM_SGPR_BANKS 8
 #define NUM_BANKS (NUM_VGPR_BANKS + NUM_SGPR_BANKS)
 #define SGPR_BANK_OFFSET NUM_VGPR_BANKS
 #define VGPR_BANK_MASK 0xf
 #define SGPR_BANK_MASK 0xff0

 MCRegister GCNRegBankReassign::scavengeReg(LiveInterval &LI, unsigned Bank,
                                            unsigned SubReg) const {
   const TargetRegisterClass *RC = MRI->getRegClass(LI.reg());
   unsigned MaxNumRegs = (Bank < NUM_VGPR_BANKS) ? MaxNumVGPRs
                                                 : MaxNumSGPRs;
   unsigned MaxReg = MaxNumRegs + (Bank < NUM_VGPR_BANKS ? AMDGPU::VGPR0
                                                         : AMDGPU::SGPR0);
 
   for (MCRegister Reg : RC->getRegisters()) {
     // Check occupancy limit.
     if (TRI->isSubRegisterEq(Reg, MaxReg))
       break;
 
     if (!MRI->isAllocatable(Reg) || getPhysRegBank(Reg, SubReg) != Bank)
       continue;
 
     for (unsigned I = 0; CSRegs[I]; ++I)

 }
 
 bool GCNRegBankReassign::runOnMachineFunction(MachineFunction &MF) {
   ST = &MF.getSubtarget<GCNSubtarget>();
   if (!ST->hasRegisterBanking() || skipFunction(MF.getFunction()))
     return false;
 
   MRI = &MF.getRegInfo();
+
+  LLVM_DEBUG(dbgs() << "=== RegBanks reassign analysis on function " << MF.getName()
+                    << "\nNumVirtRegs = " << MRI->getNumVirtRegs() << "\n\n");
+
+  if (MRI->getNumVirtRegs() > VRegThresh) {
+    LLVM_DEBUG(dbgs() << "NumVirtRegs > " << VRegThresh
+                      << " threshold, skipping function.\n\n");
+    return false;
+  }
+
   TRI = ST->getRegisterInfo();
   MLI = &getAnalysis<MachineLoopInfo>();
   VRM = &getAnalysis<VirtRegMap>();
   LRM = &getAnalysis<LiveRegMatrix>();
   LIS = &getAnalysis<LiveIntervals>();
 
   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
   unsigned Occupancy = MFI->getOccupancy();
   MaxNumVGPRs = ST->getMaxNumVGPRs(MF);
   MaxNumSGPRs = ST->getMaxNumSGPRs(MF);
   MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(Occupancy), MaxNumVGPRs);
   MaxNumSGPRs = std::min(ST->getMaxNumSGPRs(Occupancy, true), MaxNumSGPRs);
 
   CSRegs = MRI->getCalleeSavedRegs();
   unsigned NumRegBanks = AMDGPU::VGPR_32RegClass.getNumRegs() +
                          // Not a tight bound
                          AMDGPU::SReg_32RegClass.getNumRegs() / 2 + 1;
   RegsUsed.resize(NumRegBanks);
 
-  LLVM_DEBUG(dbgs() << "=== RegBanks reassign analysis on function " << MF.getName()
-               << '\n');
-
   unsigned StallCycles = collectCandidates(MF);
   NumStallsDetected += StallCycles;
 
   LLVM_DEBUG(dbgs() << "=== " << StallCycles << " stall cycles detected in "
                   "function " << MF.getName() << '\n');
 
   LLVM_DEBUG(Candidates.dump(this));