[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3

[dp]

Summary

Summary of changes:

• enabled "bound_ctrl:1" syntax;
• disabled "bound_ctrl:-1" syntax;
• corrected printer to output "bound_ctrl:1" instead of "bound_ctrl:0".

See bug 35397 for detailed issue description.

[rampitec]

LGTM

[foad]

Thanks!

llvm/docs/AMDGPUModifierSyntax.rst

 ~~~~~~~~~~
 
 Controls data sharing when accessing an invalid lane. By default, data sharing with
 invalid lanes is disabled.
 
     ======================================== ================================================
     Syntax                                   Description
     ======================================== ================================================
-    bound_ctrl:0                             Enables data sharing with invalid lanes.
+    bound_ctrl:1                             Enables data sharing with invalid lanes.
 
                                              Accessing data from an invalid lane will
                                              return zero.
     ======================================== ================================================
 
 .. _amdgpu_synid_fi16:
 
 fi

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

static bool ConvertOmodDiv(int64_t &Div) {
   if (Div == 2) {
     Div = 3;
     return true;
   }
 
   return false;
 }
 
+// Both bound_ctrl:0 and bound_ctrl:1 are encoded as 1.
+// This is intentional and ensures compatibility with sp3.
+// See bug 35397 for details.
 static bool ConvertBoundCtrl(int64_t &BoundCtrl) {
-  if (BoundCtrl == 0) {
+  if (BoundCtrl == 0 || BoundCtrl == 1) {
     BoundCtrl = 1;
     return true;
   }
-
-  if (BoundCtrl == -1) {
-    BoundCtrl = 0;
-    return true;
-  }
-
   return false;
 }
 
 // Note: the order in this table matches the order of operands in AsmString.
 static const OptionalOperand AMDGPUOptionalOperandTable[] = {
   {"offen",   AMDGPUOperand::ImmTyOffen, true, nullptr},
   {"idxen",   AMDGPUOperand::ImmTyIdxen, true, nullptr},
   {"addr64",  AMDGPUOperand::ImmTyAddr64, true, nullptr},

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
   printU4ImmOperand(MI, OpNo, STI, O);
 }
 
 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
                                        const MCSubtargetInfo &STI,
                                        raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
   if (Imm) {
-    O << " bound_ctrl:0"; // XXX - this syntax is used in sp3
+    O << " bound_ctrl:1";
   }
 }
 
 void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo,
                                 const MCSubtargetInfo &STI,
                                 raw_ostream &O) {
   using namespace llvm::AMDGPU::DPP;
   unsigned Imm = MI->getOperand(OpNo).getImm();

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX10 %s
 
 ; FIXME: Merge with DAG test
 
 define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in) {
 ; GFX8-LABEL: dpp_test:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX8-NEXT:    s_load_dword s0, s[0:1], 0x2c
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX8-NEXT:    s_nop 0
-; GFX8-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; GFX8-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1
 ; GFX8-NEXT:    flat_store_dword v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: dpp_test:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf]
 ; GFX10-NEXT:    s_load_dword s4, s[0:1], 0x2c ; encoding: [0x00,0x01,0x00,0xf4,0x2c,0x00,0x00,0xfa]
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24 ; encoding: [0x80,0x00,0x04,0xf4,0x24,0x00,0x00,0xfa]
 ; GFX10-NEXT:    v_mov_b32_e32 v1, 0 ; encoding: [0x80,0x02,0x02,0x7e]
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf]
 ; GFX10-NEXT:    v_mov_b32_e32 v0, s4 ; encoding: [0x04,0x02,0x00,0x7e]
-; GFX10-NEXT:    v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
+; GFX10-NEXT:    v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
 ; GFX10-NEXT:    global_store_dword v1, v0, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x01,0x00,0x02,0x00]
 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
   %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 true) #0
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 define amdgpu_kernel void @mov_dpp64_test(i64 addrspace(1)* %out, i64 %in1) {
 ; GFX8-LABEL: mov_dpp64_test:

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll

 ; SI-NEXT:    s_wqm_b64 s[6:7], s[0:1]
 ; SI-NEXT:    s_and_b64 exec, exec, s[6:7]
 ; SI-NEXT:  ; %bb.3: ; %.continue0
 ; SI-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; SI-NEXT:    s_mov_b64 s[4:5], s[0:1]
 ; SI-NEXT:    v_cndmask_b32_e64 v0, 1.0, 0, s[4:5]
 ; SI-NEXT:    v_mov_b32_e32 v1, v0
 ; SI-NEXT:    s_nop 1
-; SI-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; SI-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; SI-NEXT:    s_nop 1
-; SI-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; SI-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; SI-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; SI-NEXT:    s_and_b64 exec, exec, s[0:1]
 ; SI-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
 ; SI-NEXT:    s_and_b64 s[4:5], s[0:1], vcc
 ; SI-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
 ; SI-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
 ; SI-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
 ; SI-NEXT:  ; %bb.4: ; %.demote1

 ; GFX9-NEXT:    s_wqm_b64 s[4:5], s[0:1]
 ; GFX9-NEXT:    s_and_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:  ; %bb.3: ; %.continue0
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
 ; GFX9-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; GFX9-NEXT:    s_and_b64 exec, exec, s[0:1]
 ; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
 ; GFX9-NEXT:    s_and_b64 s[2:3], s[0:1], vcc
 ; GFX9-NEXT:    s_xor_b64 s[2:3], s[2:3], -1
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], s[2:3]
 ; GFX9-NEXT:    s_xor_b64 s[2:3], exec, s[4:5]
 ; GFX9-NEXT:  ; %bb.4: ; %.demote1

 ; GFX10-32-NEXT:  ; %bb.2: ; %.demote0
 ; GFX10-32-NEXT:    s_wqm_b32 s2, s0
 ; GFX10-32-NEXT:    s_and_b32 exec_lo, exec_lo, s2
 ; GFX10-32-NEXT:  ; %bb.3: ; %.continue0
 ; GFX10-32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
 ; GFX10-32-NEXT:    s_mov_b32 s1, s0
 ; GFX10-32-NEXT:    v_cndmask_b32_e64 v0, 1.0, 0, s1
 ; GFX10-32-NEXT:    v_mov_b32_e32 v1, v0
-; GFX10-32-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX10-32-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX10-32-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX10-32-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX10-32-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; GFX10-32-NEXT:    s_and_b32 exec_lo, exec_lo, s0
 ; GFX10-32-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v0
 ; GFX10-32-NEXT:    s_and_b32 s1, s0, vcc_lo
 ; GFX10-32-NEXT:    s_xor_b32 s1, s1, -1
 ; GFX10-32-NEXT:    s_and_saveexec_b32 s2, s1
 ; GFX10-32-NEXT:    s_xor_b32 s1, exec_lo, s2
 ; GFX10-32-NEXT:  ; %bb.4: ; %.demote1

 ; GFX10-64-NEXT:  ; %bb.2: ; %.demote0
 ; GFX10-64-NEXT:    s_wqm_b64 s[4:5], s[0:1]
 ; GFX10-64-NEXT:    s_and_b64 exec, exec, s[4:5]
 ; GFX10-64-NEXT:  ; %bb.3: ; %.continue0
 ; GFX10-64-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX10-64-NEXT:    s_mov_b64 s[2:3], s[0:1]
 ; GFX10-64-NEXT:    v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
 ; GFX10-64-NEXT:    v_mov_b32_e32 v1, v0
-; GFX10-64-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX10-64-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX10-64-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX10-64-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX10-64-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; GFX10-64-NEXT:    s_and_b64 exec, exec, s[0:1]
 ; GFX10-64-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
 ; GFX10-64-NEXT:    s_and_b64 s[2:3], s[0:1], vcc
 ; GFX10-64-NEXT:    s_xor_b64 s[2:3], s[2:3], -1
 ; GFX10-64-NEXT:    s_and_saveexec_b64 s[4:5], s[2:3]
 ; GFX10-64-NEXT:    s_xor_b64 s[2:3], exec, s[4:5]
 ; GFX10-64-NEXT:  ; %bb.4: ; %.demote1

 ; SI-NEXT:    s_andn2_b64 exec, exec, s[4:5]
 ; SI-NEXT:    s_cbranch_execz BB7_8
 ; SI-NEXT:  BB7_5: ; %.continue0
 ; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; SI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; SI-NEXT:    v_cndmask_b32_e64 v2, v0, 0, s[6:7]
 ; SI-NEXT:    v_mov_b32_e32 v3, v2
 ; SI-NEXT:    s_nop 1
-; SI-NEXT:    v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; SI-NEXT:    v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; SI-NEXT:    s_nop 1
-; SI-NEXT:    v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; SI-NEXT:    v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; SI-NEXT:    ; kill: def $vgpr2 killed $vgpr2 killed $exec
 ; SI-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
 ; SI-NEXT:    s_and_b64 s[6:7], s[0:1], vcc
 ; SI-NEXT:    s_xor_b64 s[6:7], s[6:7], -1
 ; SI-NEXT:    s_and_saveexec_b64 s[8:9], s[6:7]
 ; SI-NEXT:    s_xor_b64 s[6:7], exec, s[8:9]
 ; SI-NEXT:    s_cbranch_execz BB7_4
 ; SI-NEXT:  ; %bb.6: ; %.demote1

 ; GFX9-NEXT:    s_andn2_b64 exec, exec, s[2:3]
 ; GFX9-NEXT:    s_cbranch_execz BB7_8
 ; GFX9-NEXT:  BB7_5: ; %.continue0
 ; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX9-NEXT:    s_mov_b64 s[4:5], s[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v0, 0, s[4:5]
 ; GFX9-NEXT:    v_mov_b32_e32 v3, v2
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    ; kill: def $vgpr2 killed $vgpr2 killed $exec
 ; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
 ; GFX9-NEXT:    s_and_b64 s[4:5], s[0:1], vcc
 ; GFX9-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
 ; GFX9-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
 ; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
 ; GFX9-NEXT:    s_cbranch_execz BB7_4
 ; GFX9-NEXT:  ; %bb.6: ; %.demote1

 ; GFX10-32-NEXT:    s_or_b32 s1, vcc_lo, s1
 ; GFX10-32-NEXT:    s_andn2_b32 exec_lo, exec_lo, s1
 ; GFX10-32-NEXT:    s_cbranch_execz BB7_8
 ; GFX10-32-NEXT:  BB7_5: ; %.continue0
 ; GFX10-32-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX10-32-NEXT:    s_mov_b32 s2, s0
 ; GFX10-32-NEXT:    v_cndmask_b32_e64 v2, v0, 0, s2
 ; GFX10-32-NEXT:    v_mov_b32_e32 v3, v2
-; GFX10-32-NEXT:    v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX10-32-NEXT:    v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX10-32-NEXT:    v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX10-32-NEXT:    v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX10-32-NEXT:    ; kill: def $vgpr2 killed $vgpr2 killed $exec
 ; GFX10-32-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
 ; GFX10-32-NEXT:    s_and_b32 s2, s0, vcc_lo
 ; GFX10-32-NEXT:    s_xor_b32 s2, s2, -1
 ; GFX10-32-NEXT:    s_and_saveexec_b32 s3, s2
 ; GFX10-32-NEXT:    s_xor_b32 s2, exec_lo, s3
 ; GFX10-32-NEXT:    s_cbranch_execz BB7_4
 ; GFX10-32-NEXT:  ; %bb.6: ; %.demote1

 ; GFX10-64-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
 ; GFX10-64-NEXT:    s_andn2_b64 exec, exec, s[2:3]
 ; GFX10-64-NEXT:    s_cbranch_execz BB7_8
 ; GFX10-64-NEXT:  BB7_5: ; %.continue0
 ; GFX10-64-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX10-64-NEXT:    s_mov_b64 s[4:5], s[0:1]
 ; GFX10-64-NEXT:    v_cndmask_b32_e64 v2, v0, 0, s[4:5]
 ; GFX10-64-NEXT:    v_mov_b32_e32 v3, v2
-; GFX10-64-NEXT:    v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX10-64-NEXT:    v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX10-64-NEXT:    v_mov_b32_dpp v3, v3 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX10-64-NEXT:    v_subrev_f32_dpp v2, v2, v3 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX10-64-NEXT:    ; kill: def $vgpr2 killed $vgpr2 killed $exec
 ; GFX10-64-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
 ; GFX10-64-NEXT:    s_and_b64 s[4:5], s[0:1], vcc
 ; GFX10-64-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
 ; GFX10-64-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
 ; GFX10-64-NEXT:    s_xor_b64 s[4:5], exec, s[6:7]
 ; GFX10-64-NEXT:    s_cbranch_execz BB7_4
 ; GFX10-64-NEXT:  ; %bb.6: ; %.demote1

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX8-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX8-NEXT:    s_nop 0
 ; GFX8-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]

 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX9-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]

 ;
 ; GFX1064-LABEL: add_i32_varying:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1064-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf

 ;
 ; GFX1032-LABEL: add_i32_varying:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15

 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX8-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX8-NEXT:    s_nop 0
 ; GFX8-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]

 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX9-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]

 ;
 ; GFX1064-LABEL: add_i32_varying_gfx1032:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1064-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf

 ;
 ; GFX1032-LABEL: add_i32_varying_gfx1032:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15

 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX8-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX8-NEXT:    s_nop 0
 ; GFX8-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]

 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX9-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]

 ;
 ; GFX1064-LABEL: add_i32_varying_gfx1064:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1064-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf

 ;
 ; GFX1032-LABEL: add_i32_varying_gfx1064:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15

 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX8-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX8-NEXT:    s_nop 0
 ; GFX8-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]

 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX9-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]

 ;
 ; GFX1064-LABEL: sub_i32_varying:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1064-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf

 ;
 ; GFX1032-LABEL: sub_i32_varying:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15

 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_or_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX8-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX8-NEXT:    s_nop 0
 ; GFX8-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]

 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_or_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX9-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]

 ;
 ; GFX1064-LABEL: or_i32_varying:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1064-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1064-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1064-NEXT:    v_or_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX1064-NEXT:    v_or_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf

 ;
 ; GFX1032-LABEL: or_i32_varying:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1032-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_or_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15

 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_xor_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX8-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX8-NEXT:    s_nop 0
 ; GFX8-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]

 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_xor_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX9-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]

 ;
 ; GFX1064-LABEL: xor_i32_varying:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1064-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1064-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1064-NEXT:    v_xor_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX1064-NEXT:    v_xor_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf

 ;
 ; GFX1032-LABEL: xor_i32_varying:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1032-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_xor_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15

 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX8-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_max_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_max_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX8-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX8-NEXT:    s_nop 0
 ; GFX8-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX8-NEXT:    s_mov_b64 exec, s[2:3]

 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX9-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_max_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_max_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_max_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX9-NEXT:    v_readlane_b32 s4, v2, 63
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX9-NEXT:    s_mov_b64 exec, s[2:3]

 ;
 ; GFX1064-LABEL: umax_i32_varying:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
-; GFX1064-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1064-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1064-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1064-NEXT:    v_max_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX1064-NEXT:    v_max_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf

 ;
 ; GFX1032-LABEL: umax_i32_varying:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
-; GFX1032-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1032-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_max_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_max_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15

llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll

 ; GFX8-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX8-NEXT:    s_mov_b64 exec, s[10:11]
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX8-NEXT:    s_not_b64 exec, exec
 ; GFX8-NEXT:    s_or_saveexec_b64 s[10:11], -1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
-; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX8-NEXT:    s_nop 1
 ; GFX8-NEXT:    v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX8-NEXT:    v_readlane_b32 s12, v2, 63
 ; GFX8-NEXT:    s_nop 0
 ; GFX8-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX8-NEXT:    s_mov_b64 exec, s[10:11]

 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    s_mov_b64 exec, s[10:11]
 ; GFX9-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX9-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_not_b64 exec, exec
 ; GFX9-NEXT:    s_or_saveexec_b64 s[10:11], -1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf
 ; GFX9-NEXT:    s_nop 1
 ; GFX9-NEXT:    v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf
 ; GFX9-NEXT:    v_readlane_b32 s12, v2, 63
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX9-NEXT:    s_mov_b64 exec, s[10:11]

 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[8:9], s[10:11]
 ; GFX1064-NEXT:    s_cbranch_execz BB1_4
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1064-NEXT:    s_not_b64 exec, exec
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[10:11], -1
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1064-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s12, v1, 31
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s12
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s12, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf

 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s8, s9
 ; GFX1032-NEXT:    s_cbranch_execz BB1_4
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX1032-NEXT:    s_not_b32 exec_lo, exec_lo
 ; GFX1032-NEXT:    s_or_saveexec_b32 s9, -1
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_readlane_b32 s11, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    v_readlane_b32 s10, v1, 15
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s9
 ; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0

llvm/test/CodeGen/AMDGPU/dpp64_combine.ll

 ; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP64,GFX90A
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10
 
 ; GCN-LABEL: {{^}}dpp64_ceil:
 ; GCN:           global_load_dwordx2 [[V:v\[[0-9:]+\]]],
-; DPP64:         v_ceil_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
-; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
+; DPP64:         v_ceil_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
+; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
 define amdgpu_kernel void @dpp64_ceil(i64 addrspace(1)* %arg, i64 %in1) {
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
   %load = load i64, i64 addrspace(1)* %gep
   %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
   %tmp1 = bitcast i64 %tmp0 to double
   %round = tail call double @llvm.ceil.f64(double %tmp1)
   %tmp2 = bitcast double %round to i64
   store i64 %tmp2, i64 addrspace(1)* %gep
   ret void
 }
 
 ; GCN-LABEL: {{^}}dpp64_rcp:
 ; GCN:           global_load_dwordx2 [[V:v\[[0-9:]+\]]],
-; DPP64:         v_rcp_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
-; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
+; DPP64:         v_rcp_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
+; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
 define amdgpu_kernel void @dpp64_rcp(i64 addrspace(1)* %arg, i64 %in1) {
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
   %load = load i64, i64 addrspace(1)* %gep
   %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
   %tmp1 = bitcast i64 %tmp0 to double
   %rcp = call double @llvm.amdgcn.rcp.f64(double %tmp1)
   %tmp2 = bitcast double %rcp to i64
   store i64 %tmp2, i64 addrspace(1)* %gep
   ret void
 }
 
 ; GCN-LABEL: {{^}}dpp64_rcp_unsupported_ctl:
-; GCN-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
+; GCN-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
 ; GCN:         v_rcp_f64_e32
 define amdgpu_kernel void @dpp64_rcp_unsupported_ctl(i64 addrspace(1)* %arg, i64 %in1) {
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
   %load = load i64, i64 addrspace(1)* %gep
   %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 15, i32 15, i1 1) #0
   %tmp1 = bitcast i64 %tmp0 to double
   %rcp = fdiv fast double 1.0, %tmp1
   %tmp2 = bitcast double %rcp to i64
   store i64 %tmp2, i64 addrspace(1)* %gep
   ret void
 }
 
 ; GCN-LABEL: {{^}}dpp64_div:
 ; GCN:            global_load_dwordx2 [[V:v\[[0-9:]+\]]],
-; GFX90A-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
-; GFX10-COUNT-2:  v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
+; GFX90A-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
+; GFX10-COUNT-2:  v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
 ; GCN:            v_div_scale_f64
 ; GCN:            v_rcp_f64_e32
 define amdgpu_kernel void @dpp64_div(i64 addrspace(1)* %arg, i64 %in1) {
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
   %load = load i64, i64 addrspace(1)* %gep
   %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
   %tmp1 = bitcast i64 %tmp0 to double

llvm/test/CodeGen/AMDGPU/dpp_combine.ll

 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
 
 ; GCN-LABEL: {{^}}dpp_add:
 ; GCN: global_load_dword [[V:v[0-9]+]],
-; GCN: v_add_{{(nc_)?}}u32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
+; GCN: v_add_{{(nc_)?}}u32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
 define amdgpu_kernel void @dpp_add(i32 addrspace(1)* %arg) {
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
   %load = load i32, i32 addrspace(1)* %gep
   %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
   %add = add i32 %tmp0, %load
   store i32 %add, i32 addrspace(1)* %gep
   ret void
 }
 
 ; GCN-LABEL: {{^}}dpp_ceil:
 ; GCN: global_load_dword [[V:v[0-9]+]],
-; GCN: v_ceil_f32_dpp [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
+; GCN: v_ceil_f32_dpp [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
 define amdgpu_kernel void @dpp_ceil(i32 addrspace(1)* %arg) {
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
   %load = load i32, i32 addrspace(1)* %gep
   %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
   %tmp1 = bitcast i32 %tmp0 to float
   %round = tail call float @llvm.ceil.f32(float %tmp1)
   %tmp2 = bitcast float %round to i32
   store i32 %tmp2, i32 addrspace(1)* %gep
   ret void
 }
 
 ; GCN-LABEL: {{^}}dpp_fadd:
 ; GCN: global_load_dword [[V:v[0-9]+]],
-; GCN: v_add_f32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
+; GCN: v_add_f32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
 define amdgpu_kernel void @dpp_fadd(i32 addrspace(1)* %arg) {
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
   %load = load i32, i32 addrspace(1)* %gep
   %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
   %tmp1 = bitcast i32 %tmp0 to float
   %t = bitcast i32 %load to float
   %add = fadd float %tmp1, %t

llvm/test/CodeGen/AMDGPU/dpp_combine.mir

 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
 
 ---
 # old is undefined: only combine when masks are fully enabled and
-# bound_ctrl:0 is set, otherwise the result of DPP VALU op can be undefined.
+# bound_ctrl:1 is set, otherwise the result of DPP VALU op can be undefined.
 # GCN-LABEL: name: old_is_undef
 # GCN: %2:vgpr_32 = IMPLICIT_DEF
 # VOP2:
 # GCN: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec
 # GCN: %6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec
 # GCN: %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec
 # GCN: %10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec
 # VOP1:
bb.0:
     %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
 ...
 
 # old is zero cases:
 
 # GCN-LABEL: name: old_is_0
 
 # VOP2:
-# case 1: old is zero, masks are fully enabled, bound_ctrl:0 is on:
+# case 1: old is zero, masks are fully enabled, bound_ctrl:1 is on:
 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
 # out of range}) or active src lane result - can combine with old = undef.
 # undef is preffered as it makes life easier for the regalloc.
 # GCN: [[U1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
 # GCN: %4:vgpr_32 = V_ADD_U32_dpp [[U1]], %0, %1, 1, 15, 15, 1, implicit $exec
 
-# case 2: old is zero, masks are fully enabled, bound_ctrl:0 is off:
+# case 2: old is zero, masks are fully enabled, bound_ctrl:1 is off:
 # as the DPP mov old is zero this case is no different from case 1 - combine it
-# setting bound_ctrl0 on for the combined DPP VALU op to make old undefined
+# setting bound_ctrl:1 on for the combined DPP VALU op to make old undefined
 # GCN: [[U2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
 # GCN: %6:vgpr_32 = V_ADD_U32_dpp [[U2]], %0, %1, 1, 15, 15, 1, implicit $exec
 
-# case 3: masks are partialy disabled, bound_ctrl:0 is on:
+# case 3: masks are partialy disabled, bound_ctrl:1 is on:
 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
 # out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
 # active src lane result - can combine with old = src1 of the VALU op.
 # The VALU op should have the same masks as DPP mov as they select lanes
 # with identity value.
 # Special case: the bound_ctrl for the combined DPP VALU op isn't important
 # here but let's make it off to keep the combiner's logic simpler.
 # GCN: %8:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 
-# case 4: masks are partialy disabled, bound_ctrl:0 is off:
+# case 4: masks are partialy disabled, bound_ctrl:1 is off:
 # the DPP mov result would be either zero ({src lane disabled}|{src lane is
 # out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
 # active src lane result - can combine with old = src1 of the VALU op.
 # The VALU op should have the same masks as DPP mov as they select
 # lanes with identity value
 # GCN: %10:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
 
 # VOP1:
bb.0:
     %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
 
     %17:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
     %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
 ...
 
 # old is nonzero identity cases:
 
-# old is nonzero identity, masks are fully enabled, bound_ctrl:0 is off:
+# old is nonzero identity, masks are fully enabled, bound_ctrl:1 is off:
 # the DPP mov result would be either identity ({src lane disabled}|{out of
 # range}) or src lane result - can combine with old = src1 of the VALU op
 # The DPP VALU op should have the same masks (and bctrl) as DPP mov as they
 # select lanes with identity value
 
 # GCN-LABEL: name: nonzero_old_is_identity_masks_enabled_bctl_off
 # GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec
 # GCN: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec
bb.0:
     %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 15, 15, 0, implicit $exec
     %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
 
     %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
     %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 15, 0, implicit $exec
     %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
 ...
 
-# old is nonzero identity, masks are partially enabled, bound_ctrl:0 is off:
+# old is nonzero identity, masks are partially enabled, bound_ctrl:1 is off:
 # the DPP mov result would be either identity ({src lane disabled}|{src lane is
 # out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
 # active src lane result - can combine with old = src1 of the VALU op.
 # The DPP VALU op should have the same masks (and bctrl) as DPP mov as they
 # select lanes with identity value
 
 # GCN-LABEL: name: nonzero_old_is_identity_masks_partially_disabled_bctl_off
 # GCN: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
bb.0:
     %9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec
     %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
 
     %11:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
     %12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec
     %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
 ...
 
-# old is nonzero identity, masks are partially enabled, bound_ctrl:0 is on:
+# old is nonzero identity, masks are partially enabled, bound_ctrl:1 is on:
 # the DPP mov result may have 3 different values:
 #   1. the active src lane result
 #   2. 0 if the src lane is disabled|out of range
 #   3. DPP mov's old value if the mov's dest VGPR write is disabled by masks
 # can't combine
 
 # GCN-LABEL: name: nonzero_old_is_identity_masks_partially_disabled_bctl0
 # GCN: %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
bb.0:
     %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     %3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec
     %4:vgpr_32 = V_ADD_U32_e32 %3, %0, implicit $exec
 ...
 
-# old reg def is in diff BB but bound_ctrl:0 - can combine
+# old reg def is in diff BB but bound_ctrl:1 - can combine
 # GCN-LABEL: name: old_in_diff_bb_bctrl_zero
 # GCN: %4:vgpr_32 = V_ADD_U32_dpp {{%[0-9]}}, %0, %1, 1, 15, 15, 1, implicit $exec
 
 name: old_in_diff_bb_bctrl_zero
 tracksRegLiveness: true
 body: |
   bb.0:
     successors: %bb.1

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll

 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT,PREGFX10,PREGFX10-OPT %s
 ; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-NOOPT,PREGFX10,PREGFX10-NOOPT %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT %s
 
 ; FIXME: The register allocator / scheduler should be able to avoid these hazards.
 
 ; VI-LABEL: {{^}}dpp_test:
 ; VI: v_mov_b32_e32 v0, s{{[0-9]+}}
 ; VI-NOOPT: v_mov_b32_e32 v1, s{{[0-9]+}}
 ; PREGFX10: s_nop 1
-; VI-OPT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
-; VI-NOOPT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x01,0x08,0x11]
+; VI-OPT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
+; VI-NOOPT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x01,0x08,0x11]
 define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in) {
   %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 
 ; VI-LABEL: {{^}}dpp_wait_states:
 ; VI-NOOPT: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s{{[0-9]+}}
 ; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}}
 ; PREGFX10: s_nop 1
-; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1
 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:
 ; PREGFX10: s_nop 1
-; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
-; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1
+; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1
 define amdgpu_kernel void @dpp_wait_states(i32 addrspace(1)* %out, i32 %in) {
   %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0
   %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0
   store i32 %tmp1, i32 addrspace(1)* %out
   ret void
 }
 
 ; VI-LABEL: {{^}}dpp_first_in_bb:
 ; VI: ; %endif
 ; PREGFX10-NOOPT: s_waitcnt
 ; PREGFX10-NOOPT: v_mov_b32_e32
-; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1
 ; PREGFX10-OPT: s_mov_b32
 ; PREGFX10-OPT: s_mov_b32
-; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1
 ; PREGFX10: s_nop 1
-; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
+; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1
 define amdgpu_kernel void @dpp_first_in_bb(float addrspace(1)* %out, float addrspace(1)* %in, float %cond, float %a, float %b) {
   %cmp = fcmp oeq float %cond, 0.0
   br i1 %cmp, label %if, label %else
 
 if:
   %out_val = load float, float addrspace(1)* %out
   %if_val = fadd float %a, %out_val
   br label %endif

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll

define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}dpp_test_bc:
 ; GCN:  v_mov_b32_e32 [[DST:v[0-9]+]], s{{[0-9]+}}
 ; GCN:  v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
 ; GFX8: s_nop 1
-; GCN:  v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[2,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0{{$}}
+; GCN:  v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[2,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1{{$}}
 define amdgpu_kernel void @dpp_test_bc(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
   %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 2, i32 1, i32 1, i1 1) #0
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 
 
 ; GCN-LABEL: {{^}}dpp_test1:

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll

 ; SI-NEXT:    s_and_b64 exec, exec, s[4:5]
 ; SI-NEXT:  ; %bb.3: ; %.continue0
 ; SI-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; SI-NEXT:    s_mov_b64 s[2:3], s[0:1]
 ; SI-NEXT:    v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
 ; SI-NEXT:    v_mov_b32_e32 v1, v0
 ; SI-NEXT:    s_xor_b64 s[2:3], s[0:1], -1
 ; SI-NEXT:    s_nop 0
-; SI-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; SI-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; SI-NEXT:    s_nop 1
-; SI-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; SI-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; SI-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; SI-NEXT:    s_and_b64 exec, exec, s[0:1]
 ; SI-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
 ; SI-NEXT:    s_or_b64 s[2:3], s[2:3], vcc
 ; SI-NEXT:    s_and_saveexec_b64 s[4:5], s[2:3]
 ; SI-NEXT:    s_xor_b64 s[2:3], exec, s[4:5]
 ; SI-NEXT:  ; %bb.4: ; %.demote1
 ; SI-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec

 ; GFX9-NEXT:    s_and_b64 exec, exec, s[4:5]
 ; GFX9-NEXT:  ; %bb.3: ; %.continue0
 ; GFX9-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX9-NEXT:    s_mov_b64 s[2:3], s[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
 ; GFX9-NEXT:    v_mov_b32_e32 v1, v0
 ; GFX9-NEXT:    s_xor_b64 s[2:3], s[0:1], -1
 ; GFX9-NEXT:    s_nop 0
-; GFX9-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; GFX9-NEXT:    s_and_b64 exec, exec, s[0:1]
 ; GFX9-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
 ; GFX9-NEXT:    s_or_b64 s[2:3], s[2:3], vcc
 ; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], s[2:3]
 ; GFX9-NEXT:    s_xor_b64 s[2:3], exec, s[4:5]
 ; GFX9-NEXT:  ; %bb.4: ; %.demote1
 ; GFX9-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec

 ; GFX10-32-NEXT:  ; %bb.2: ; %.demote0
 ; GFX10-32-NEXT:    s_wqm_b32 s2, s0
 ; GFX10-32-NEXT:    s_and_b32 exec_lo, exec_lo, s2
 ; GFX10-32-NEXT:  ; %bb.3: ; %.continue0
 ; GFX10-32-NEXT:    s_or_b32 exec_lo, exec_lo, s1
 ; GFX10-32-NEXT:    s_mov_b32 s1, s0
 ; GFX10-32-NEXT:    v_cndmask_b32_e64 v0, 1.0, 0, s1
 ; GFX10-32-NEXT:    v_mov_b32_e32 v1, v0
-; GFX10-32-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX10-32-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX10-32-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX10-32-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX10-32-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; GFX10-32-NEXT:    s_and_b32 exec_lo, exec_lo, s0
 ; GFX10-32-NEXT:    v_cmp_neq_f32_e32 vcc_lo, 0, v0
 ; GFX10-32-NEXT:    s_xor_b32 s1, s0, -1
 ; GFX10-32-NEXT:    s_or_b32 s1, s1, vcc_lo
 ; GFX10-32-NEXT:    s_and_saveexec_b32 s2, s1
 ; GFX10-32-NEXT:    s_xor_b32 s1, exec_lo, s2
 ; GFX10-32-NEXT:  ; %bb.4: ; %.demote1

 ; GFX10-64-NEXT:  ; %bb.2: ; %.demote0
 ; GFX10-64-NEXT:    s_wqm_b64 s[4:5], s[0:1]
 ; GFX10-64-NEXT:    s_and_b64 exec, exec, s[4:5]
 ; GFX10-64-NEXT:  ; %bb.3: ; %.continue0
 ; GFX10-64-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX10-64-NEXT:    s_mov_b64 s[2:3], s[0:1]
 ; GFX10-64-NEXT:    v_cndmask_b32_e64 v0, 1.0, 0, s[2:3]
 ; GFX10-64-NEXT:    v_mov_b32_e32 v1, v0
-; GFX10-64-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX10-64-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX10-64-NEXT:    v_mov_b32_dpp v1, v1 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX10-64-NEXT:    v_subrev_f32_dpp v0, v0, v1 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX10-64-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; GFX10-64-NEXT:    s_and_b64 exec, exec, s[0:1]
 ; GFX10-64-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
 ; GFX10-64-NEXT:    s_xor_b64 s[2:3], s[0:1], -1
 ; GFX10-64-NEXT:    s_or_b64 s[2:3], s[2:3], vcc
 ; GFX10-64-NEXT:    s_and_saveexec_b64 s[4:5], s[2:3]
 ; GFX10-64-NEXT:    s_xor_b64 s[2:3], exec, s[4:5]
 ; GFX10-64-NEXT:  ; %bb.4: ; %.demote1

 ; SI-NEXT:  BB7_5: ; %.continue0
 ; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; SI-NEXT:    v_mov_b32_e32 v0, s2
 ; SI-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; SI-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[6:7]
 ; SI-NEXT:    v_mov_b32_e32 v2, v0
 ; SI-NEXT:    s_xor_b64 s[6:7], s[0:1], -1
 ; SI-NEXT:    s_nop 0
-; SI-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; SI-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; SI-NEXT:    s_nop 1
-; SI-NEXT:    v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; SI-NEXT:    v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; SI-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; SI-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
 ; SI-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
 ; SI-NEXT:    s_and_saveexec_b64 s[8:9], s[6:7]
 ; SI-NEXT:    s_xor_b64 s[6:7], exec, s[8:9]
 ; SI-NEXT:    s_cbranch_execz BB7_4
 ; SI-NEXT:  ; %bb.6: ; %.demote1
 ; SI-NEXT:    ; in Loop: Header=BB7_5 Depth=1

 ; GFX9-NEXT:  BB7_5: ; %.continue0
 ; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[6:7]
 ; GFX9-NEXT:    v_mov_b32_e32 v2, v0
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], -1
 ; GFX9-NEXT:    s_nop 0
-; GFX9-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX9-NEXT:    v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX9-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; GFX9-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
 ; GFX9-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
 ; GFX9-NEXT:    s_and_saveexec_b64 s[8:9], s[6:7]
 ; GFX9-NEXT:    s_xor_b64 s[6:7], exec, s[8:9]
 ; GFX9-NEXT:    s_cbranch_execz BB7_4
 ; GFX9-NEXT:  ; %bb.6: ; %.demote1
 ; GFX9-NEXT:    ; in Loop: Header=BB7_5 Depth=1

 ; GFX10-32-NEXT:    s_andn2_b32 exec_lo, exec_lo, s1
 ; GFX10-32-NEXT:    s_cbranch_execz BB7_8
 ; GFX10-32-NEXT:  BB7_5: ; %.continue0
 ; GFX10-32-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX10-32-NEXT:    s_mov_b32 s3, s0
 ; GFX10-32-NEXT:    v_cndmask_b32_e64 v0, s2, 0, s3
 ; GFX10-32-NEXT:    s_xor_b32 s3, s0, -1
 ; GFX10-32-NEXT:    v_mov_b32_e32 v2, v0
-; GFX10-32-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX10-32-NEXT:    v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX10-32-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX10-32-NEXT:    v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX10-32-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; GFX10-32-NEXT:    v_cmp_neq_f32_e32 vcc_lo, 0, v0
 ; GFX10-32-NEXT:    s_or_b32 s3, s3, vcc_lo
 ; GFX10-32-NEXT:    s_and_saveexec_b32 s4, s3
 ; GFX10-32-NEXT:    s_xor_b32 s3, exec_lo, s4
 ; GFX10-32-NEXT:    s_cbranch_execz BB7_4
 ; GFX10-32-NEXT:  ; %bb.6: ; %.demote1
 ; GFX10-32-NEXT:    ; in Loop: Header=BB7_5 Depth=1

 ; GFX10-64-NEXT:    s_andn2_b64 exec, exec, s[4:5]
 ; GFX10-64-NEXT:    s_cbranch_execz BB7_8
 ; GFX10-64-NEXT:  BB7_5: ; %.continue0
 ; GFX10-64-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX10-64-NEXT:    s_mov_b64 s[6:7], s[0:1]
 ; GFX10-64-NEXT:    v_cndmask_b32_e64 v0, s2, 0, s[6:7]
 ; GFX10-64-NEXT:    s_xor_b64 s[6:7], s[0:1], -1
 ; GFX10-64-NEXT:    v_mov_b32_e32 v2, v0
-; GFX10-64-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:0
-; GFX10-64-NEXT:    v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0
+; GFX10-64-NEXT:    v_mov_b32_dpp v2, v2 quad_perm:[1,1,1,1] row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX10-64-NEXT:    v_subrev_f32_dpp v0, v0, v2 quad_perm:[0,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX10-64-NEXT:    ; kill: def $vgpr0 killed $vgpr0 killed $exec
 ; GFX10-64-NEXT:    v_cmp_neq_f32_e32 vcc, 0, v0
 ; GFX10-64-NEXT:    s_or_b64 s[6:7], s[6:7], vcc
 ; GFX10-64-NEXT:    s_and_saveexec_b64 s[8:9], s[6:7]
 ; GFX10-64-NEXT:    s_xor_b64 s[6:7], exec, s[8:9]
 ; GFX10-64-NEXT:    s_cbranch_execz BB7_4
 ; GFX10-64-NEXT:  ; %bb.6: ; %.demote1
 ; GFX10-64-NEXT:    ; in Loop: Header=BB7_5 Depth=1

llvm/test/MC/AMDGPU/gfx10_asm_dpp16.s

 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x0f]
 
 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0
 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x0f]
 
 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x08,0x00]
 
+v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:1
+// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x08,0x00]
+
 v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 // GFX10: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 
 v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 // GFX10: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 
 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 // GFX10: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0x00]

 // GFX10: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x04,0x00]
 
 v_add_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0x00]
 
 v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 // GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x08,0x00]
 
+v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:1
+// GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x08,0x00]
+
 v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 // GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x04,0x00]
 
 v_sub_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
 // GFX10: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0x00]
 
 v_sub_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
 // GFX10: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0x00]

llvm/test/MC/AMDGPU/vop_dpp.s

 // VI9: v_mov_b32_dpp v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x42,0x01,0xff]
 v_mov_b32 v0, v0 row_bcast:15
 
 // NOSICI: error: not a valid operand.
 // VI9: v_mov_b32_dpp v0, v0 row_bcast:31 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x43,0x01,0xff]
 v_mov_b32 v0, v0 row_bcast:31
 
 //===----------------------------------------------------------------------===//
-// Check optional fields
+// Check bound_control modifier.
+// Both bound_ctrl:0 and bound_ctrl:1 are legal and encoded as 1.
+// See bug 35397 for details.
 //===----------------------------------------------------------------------===//
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
+// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
 v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
+// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
+v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:1
+
+// NOSICI: error: not a valid operand.
+// NOGFX9: error: invalid bound_ctrl value.
+// NOVI: error: invalid bound_ctrl value.
+v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:-1
+
+// NOSICI: error: not a valid operand.
+// NOGFX9: error: invalid bound_ctrl value.
+// NOVI: error: invalid bound_ctrl value.
+v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:2
+
+//===----------------------------------------------------------------------===//
+// Check optional fields
+//===----------------------------------------------------------------------===//
+
+// NOSICI: error: not a valid operand.
 // VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xaf]
 v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa
 
 // NOSICI: error: not a valid operand.
 // VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xf1]
 v_mov_b32 v0, v0 quad_perm:[1,3,0,1] bank_mask:0x1
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xff]
+// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xff]
 v_mov_b32 v0, v0 quad_perm:[1,3,0,1] bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
 // VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xa1]
 v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xaf]
+// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xaf]
 v_mov_b32 v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xf1]
+// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xf1]
 v_mov_b32 v0, v0 quad_perm:[1,3,0,1] bank_mask:0x1 bound_ctrl:0
 
 //===----------------------------------------------------------------------===//
 // Check modifiers
 //===----------------------------------------------------------------------===//
 
 // NOSICI: error: not a valid operand.
-// VI9: v_add_f32_dpp v0, -v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x19,0xa1]
+// VI9: v_add_f32_dpp v0, -v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x19,0xa1]
 v_add_f32 v0, -v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_add_f32_dpp v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x89,0xa1]
+// VI9: v_add_f32_dpp v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x89,0xa1]
 v_add_f32 v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_add_f32_dpp v0, -v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x99,0xa1]
+// VI9: v_add_f32_dpp v0, -v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x99,0xa1]
 v_add_f32 v0, -v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_add_f32_dpp v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x69,0xa1]
+// VI9: v_add_f32_dpp v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x69,0xa1]
 v_add_f32 v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 //===----------------------------------------------------------------------===//
 // Check VOP1 opcodes
 //===----------------------------------------------------------------------===//
 
 // NOSICI: error: not a valid operand.
 // GCN: v_nop row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x7e,0x00,0x01,0x09,0xa1]
 v_nop row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_u32_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x0e,0x00,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_u32_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x0e,0x00,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_u32_f32 v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_fract_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x36,0x00,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_fract_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x36,0x00,0x7e,0x00,0x01,0x09,0xa1]
 v_fract_f32 v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_sin_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x52,0x00,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_sin_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x52,0x00,0x7e,0x00,0x01,0x09,0xa1]
 v_sin_f32 v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mov_b32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_mov_b32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_mov_b32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_f32_i32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x0a,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_f32_i32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x0a,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_f32_i32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_f32_u32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x0c,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_f32_u32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x0c,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_f32_u32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x10,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x10,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_i32_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_f16_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x14,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_f16_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x14,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_f16_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_f32_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x16,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_f32_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x16,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_f32_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_rpi_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x18,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_rpi_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x18,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_rpi_i32_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_flr_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x1a,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_flr_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x1a,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_flr_i32_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_off_f32_i4_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x1c,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_off_f32_i4_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x1c,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_off_f32_i4 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_f32_ubyte0_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x22,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_f32_ubyte0_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x22,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_f32_ubyte0 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_f32_ubyte1_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x24,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_f32_ubyte1_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x24,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_f32_ubyte1 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_f32_ubyte2_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x26,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_f32_ubyte2_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x26,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_f32_ubyte2 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cvt_f32_ubyte3_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x28,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_f32_ubyte3_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x28,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_f32_ubyte3 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_trunc_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x38,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_trunc_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x38,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_trunc_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_ceil_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x3a,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_ceil_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x3a,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_ceil_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_rndne_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x3c,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_rndne_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x3c,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_rndne_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_floor_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x3e,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_floor_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x3e,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_floor_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_exp_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x40,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_exp_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x40,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_exp_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_log_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x42,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_log_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x42,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_log_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_rcp_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x44,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_rcp_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x44,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_rcp_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_rcp_iflag_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x46,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_rcp_iflag_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x46,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_rcp_iflag_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_rsq_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x48,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_rsq_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x48,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_rsq_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_sqrt_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x4e,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_sqrt_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x4e,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_sqrt_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_cos_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x54,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cos_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x54,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cos_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_not_b32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x56,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_not_b32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x56,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_not_b32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_bfrev_b32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x58,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_bfrev_b32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x58,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_bfrev_b32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_ffbh_u32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x5a,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_ffbh_u32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x5a,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_ffbh_u32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_ffbl_b32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x5c,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_ffbl_b32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x5c,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_ffbl_b32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_ffbh_i32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x5e,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_ffbh_i32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x5e,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_ffbh_i32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_frexp_exp_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x66,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_frexp_exp_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x66,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_frexp_exp_i32_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_frexp_mant_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x68,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_frexp_mant_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x68,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_frexp_mant_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
-// VI9: v_log_legacy_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x98,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_log_legacy_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x98,0x02,0x7e,0x00,0x01,0x09,0xa1]
 // NOSI: error: instruction not supported on this GPU
 // NOCI: error: not a valid operand.
 v_log_legacy_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
-// VI9: v_exp_legacy_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x96,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_exp_legacy_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x96,0x02,0x7e,0x00,0x01,0x09,0xa1]
 // NOSI: error: instruction not supported on this GPU
 // NOCI: error: not a valid operand.
 v_exp_legacy_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_cvt_f16_u16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x72,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_f16_u16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x72,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_f16_u16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_cvt_f16_i16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x74,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_f16_i16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x74,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_f16_i16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_cvt_u16_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x76,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_u16_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x76,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_u16_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_cvt_i16_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x78,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cvt_i16_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x78,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cvt_i16_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_rcp_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x7a,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_rcp_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x7a,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_rcp_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_sqrt_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x7c,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_sqrt_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x7c,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_sqrt_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_rsq_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x7e,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_rsq_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x7e,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_rsq_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_log_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x80,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_log_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x80,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_log_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_exp_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x82,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_exp_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x82,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_exp_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_frexp_mant_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x84,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_frexp_mant_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x84,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_frexp_mant_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_frexp_exp_i16_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x86,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_frexp_exp_i16_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x86,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_frexp_exp_i16_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_floor_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x88,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_floor_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x88,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_floor_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_ceil_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x8a,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_ceil_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x8a,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_ceil_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_trunc_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x8c,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_trunc_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x8c,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_trunc_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_rndne_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x8e,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_rndne_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x8e,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_rndne_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_fract_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x90,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_fract_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x90,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_fract_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_sin_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x92,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_sin_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x92,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_sin_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_cos_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x94,0x02,0x7e,0x00,0x01,0x09,0xa1]
+// VI9: v_cos_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x94,0x02,0x7e,0x00,0x01,0x09,0xa1]
 v_cos_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // GFX9:   v_cvt_norm_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 // NOSICI: error: instruction not supported on this GPU
 // NOVI:   error: instruction not supported on this GPU
 v_cvt_norm_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 
 // GFX9:   v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 // NOSICI: error: instruction not supported on this GPU
 // NOVI:   error: instruction not supported on this GPU
 v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 
 // GFX9:   v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x9e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
 // NOSICI: error: instruction not supported on this GPU
 // NOVI:   error: instruction not supported on this GPU
 v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
 
 // NOSICI: error: instruction not supported on this GPU
 // NOVI: error: instruction not supported on this GPU
-// GFX9: v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+// GFX9: v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 
 //===----------------------------------------------------------------------===//
 // Check VOP2 opcodes
 //===----------------------------------------------------------------------===//
 // ToDo: VOP2bInst instructions: v_add_u32, v_sub_u32 ... (vcc and ApplyMnemonic in AsmMatcherEmitter.cpp)
 
 // NOSICI: error: not a valid operand.
 // VI9: v_mac_f32_dpp v0, v0, v0  row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x01,0x01,0xff]
 v_mac_f32 v0, v0, v0 row_shl:1
 
 // NOSICI: error: not a valid operand.
 // VI9: v_mac_f32_dpp v0, v0, v0  row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x1f,0x01,0xff]
 v_mac_f32 v0, v0, v0 row_shr:0xf
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mac_f32_dpp v0, v0, v0  quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x4d,0x08,0xaf]
+// VI9: v_mac_f32_dpp v0, v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x4d,0x08,0xaf]
 v_mac_f32 v0, v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_add_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x09,0xa1]
+// VI9: v_add_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x09,0xa1]
 v_add_f32 v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_min_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x14,0x00,0x01,0x09,0xa1]
+// VI9: v_min_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x14,0x00,0x01,0x09,0xa1]
 v_min_f32 v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_and_b32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x26,0x00,0x01,0x09,0xa1]
+// VI9: v_and_b32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x26,0x00,0x01,0x09,0xa1]
 v_and_b32 v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mul_i32_i24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x0c,0x02,0x01,0x09,0xa1]
+// VI9: v_mul_i32_i24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x0c,0x02,0x01,0x09,0xa1]
 v_mul_i32_i24 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_sub_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x04,0x02,0x01,0x09,0xa1]
+// VI9: v_sub_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x04,0x02,0x01,0x09,0xa1]
 v_sub_f32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_subrev_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x06,0x02,0x01,0x09,0xa1]
+// VI9: v_subrev_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x06,0x02,0x01,0x09,0xa1]
 v_subrev_f32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mul_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x0a,0x02,0x01,0x09,0xa1]
+// VI9: v_mul_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x0a,0x02,0x01,0x09,0xa1]
 v_mul_f32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mul_hi_i32_i24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x0e,0x02,0x01,0x09,0xa1]
+// VI9: v_mul_hi_i32_i24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x0e,0x02,0x01,0x09,0xa1]
 v_mul_hi_i32_i24 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mul_u32_u24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x10,0x02,0x01,0x09,0xa1]
+// VI9: v_mul_u32_u24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x10,0x02,0x01,0x09,0xa1]
 v_mul_u32_u24 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_mul_hi_u32_u24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x12,0x02,0x01,0x09,0xa1]
+// VI9: v_mul_hi_u32_u24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x12,0x02,0x01,0x09,0xa1]
 v_mul_hi_u32_u24 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_max_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x16,0x02,0x01,0x09,0xa1]
+// VI9: v_max_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x16,0x02,0x01,0x09,0xa1]
 v_max_f32 v1, v2 v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_min_i32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x18,0x02,0x01,0x09,0xa1]
+// VI9: v_min_i32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x18,0x02,0x01,0x09,0xa1]
 v_min_i32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_max_i32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x1a,0x02,0x01,0x09,0xa1]
+// VI9: v_max_i32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x1a,0x02,0x01,0x09,0xa1]
 v_max_i32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_min_u32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x1c,0x02,0x01,0x09,0xa1]
+// VI9: v_min_u32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x1c,0x02,0x01,0x09,0xa1]
 v_min_u32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_max_u32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x1e,0x02,0x01,0x09,0xa1]
+// VI9: v_max_u32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x1e,0x02,0x01,0x09,0xa1]
 v_max_u32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_lshrrev_b32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x20,0x02,0x01,0x09,0xa1]
+// VI9: v_lshrrev_b32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x20,0x02,0x01,0x09,0xa1]
 v_lshrrev_b32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_ashrrev_i32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x22,0x02,0x01,0x09,0xa1]
+// VI9: v_ashrrev_i32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x22,0x02,0x01,0x09,0xa1]
 v_ashrrev_i32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_lshlrev_b32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x24,0x02,0x01,0x09,0xa1]
+// VI9: v_lshlrev_b32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x24,0x02,0x01,0x09,0xa1]
 v_lshlrev_b32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_or_b32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x28,0x02,0x01,0x09,0xa1]
+// VI9: v_or_b32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x28,0x02,0x01,0x09,0xa1]
 v_or_b32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
-// VI9: v_xor_b32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x2a,0x02,0x01,0x09,0xa1]
+// VI9: v_xor_b32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x2a,0x02,0x01,0x09,0xa1]
 v_xor_b32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_add_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x3e,0x02,0x01,0x09,0xa1]
+// VI9: v_add_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x3e,0x02,0x01,0x09,0xa1]
 v_add_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_sub_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x40,0x02,0x01,0x09,0xa1]
+// VI9: v_sub_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x40,0x02,0x01,0x09,0xa1]
 v_sub_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_subrev_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x42,0x02,0x01,0x09,0xa1]
+// VI9: v_subrev_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x42,0x02,0x01,0x09,0xa1]
 v_subrev_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_mul_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x44,0x02,0x01,0x09,0xa1]
+// VI9: v_mul_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x44,0x02,0x01,0x09,0xa1]
 v_mul_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_mac_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x46,0x02,0x01,0x09,0xa1]
+// VI9: v_mac_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x46,0x02,0x01,0x09,0xa1]
 v_mac_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_add_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x4c,0x02,0x01,0x09,0xa1]
+// VI9: v_add_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x4c,0x02,0x01,0x09,0xa1]
 v_add_u16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_sub_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x4e,0x02,0x01,0x09,0xa1]
+// VI9: v_sub_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x4e,0x02,0x01,0x09,0xa1]
 v_sub_u16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_subrev_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x50,0x02,0x01,0x09,0xa1]
+// VI9: v_subrev_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x50,0x02,0x01,0x09,0xa1]
 v_subrev_u16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_mul_lo_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x52,0x02,0x01,0x09,0xa1]
+// VI9: v_mul_lo_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x52,0x02,0x01,0x09,0xa1]
 v_mul_lo_u16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_lshlrev_b16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x54,0x02,0x01,0x09,0xa1]
+// VI9: v_lshlrev_b16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x54,0x02,0x01,0x09,0xa1]
 v_lshlrev_b16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_lshrrev_b16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x56,0x02,0x01,0x09,0xa1]
+// VI9: v_lshrrev_b16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x56,0x02,0x01,0x09,0xa1]
 v_lshrrev_b16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_ashrrev_i16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x58,0x02,0x01,0x09,0xa1]
+// VI9: v_ashrrev_i16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x58,0x02,0x01,0x09,0xa1]
 v_ashrrev_i16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_max_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x5a,0x02,0x01,0x09,0xa1]
+// VI9: v_max_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x5a,0x02,0x01,0x09,0xa1]
 v_max_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_min_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x5c,0x02,0x01,0x09,0xa1]
+// VI9: v_min_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x5c,0x02,0x01,0x09,0xa1]
 v_min_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_max_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x5e,0x02,0x01,0x09,0xa1]
+// VI9: v_max_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x5e,0x02,0x01,0x09,0xa1]
 v_max_u16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_max_i16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x60,0x02,0x01,0x09,0xa1]
+// VI9: v_max_i16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x60,0x02,0x01,0x09,0xa1]
 v_max_i16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_min_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x62,0x02,0x01,0x09,0xa1]
+// VI9: v_min_u16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x62,0x02,0x01,0x09,0xa1]
 v_min_u16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_min_i16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x64,0x02,0x01,0x09,0xa1]
+// VI9: v_min_i16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x64,0x02,0x01,0x09,0xa1]
 v_min_i16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
-// VI9: v_ldexp_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x66,0x02,0x01,0x09,0xa1]
+// VI9: v_ldexp_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x66,0x02,0x01,0x09,0xa1]
 v_ldexp_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
 // NOGFX9: error: not a valid operand.
-// VI: v_add_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x32,0x02,0x01,0x09,0xa1]
+// VI: v_add_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x32,0x02,0x01,0x09,0xa1]
 v_add_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
 // NOGFX9: error: not a valid operand.
-// VI: v_sub_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x34,0x02,0x01,0x09,0xa1]
+// VI: v_sub_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x34,0x02,0x01,0x09,0xa1]
 v_sub_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
 // NOGFX9: error: not a valid operand.
-// VI: v_subrev_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x36,0x02,0x01,0x09,0xa1]
+// VI: v_subrev_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x36,0x02,0x01,0x09,0xa1]
 v_subrev_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
 // NOGFX9: error: instruction not supported on this GPU
-// VI: v_addc_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x38,0x02,0x01,0x09,0xa1]
+// VI: v_addc_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x38,0x02,0x01,0x09,0xa1]
 v_addc_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
 // NOGFX9: error: instruction not supported on this GPU
-// VI: v_subb_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x3a,0x02,0x01,0x09,0xa1]
+// VI: v_subb_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x3a,0x02,0x01,0x09,0xa1]
 v_subb_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
 // NOGFX9: error: instruction not supported on this GPU
-// VI: v_subbrev_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x3c,0x02,0x01,0x09,0xa1]
+// VI: v_subbrev_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x3c,0x02,0x01,0x09,0xa1]
 v_subbrev_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
 // NOVI: error: instruction not supported on this GPU
-// GFX9: v_add_co_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x32,0x02,0x01,0x09,0xa1]
+// GFX9: v_add_co_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x32,0x02,0x01,0x09,0xa1]
 v_add_co_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
 // NOVI: error: instruction not supported on this GPU
-// GFX9: v_sub_co_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x34,0x02,0x01,0x09,0xa1]
+// GFX9: v_sub_co_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x34,0x02,0x01,0x09,0xa1]
 v_sub_co_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
 // NOVI: error: instruction not supported on this GPU
-// GFX9: v_subrev_co_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x36,0x02,0x01,0x09,0xa1]
+// GFX9: v_subrev_co_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x36,0x02,0x01,0x09,0xa1]
 v_subrev_co_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
 // NOVI: error: instruction not supported on this GPU
-// GFX9: v_addc_co_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x38,0x02,0x01,0x09,0xa1]
+// GFX9: v_addc_co_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x38,0x02,0x01,0x09,0xa1]
 v_addc_co_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
 // NOVI: error: instruction not supported on this GPU
-// GFX9: v_subb_co_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x3a,0x02,0x01,0x09,0xa1]
+// GFX9: v_subb_co_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x3a,0x02,0x01,0x09,0xa1]
 v_subb_co_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: instruction not supported on this GPU
 // NOVI: error: instruction not supported on this GPU
-// GFX9: v_subbrev_co_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x3c,0x02,0x01,0x09,0xa1]
+// GFX9: v_subbrev_co_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x3c,0x02,0x01,0x09,0xa1]
 v_subbrev_co_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0
 
 // NOSICI: error: not a valid operand.
 // VI9:    v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
 v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 
 // NOSICI: error: not a valid operand.
 // VI9:    v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0x0f,0x01,0x00]

llvm/test/MC/AMDGPU/vop_dpp_expr.s

 
 v_mov_b32 v0, v0 wave_ror:two*2-3
 // VI9: v_mov_b32_dpp v0, v0 wave_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x3c,0x01,0xff]
 
 v_mov_b32 v0, v0 row_bcast:150/(two*2+zero/one+two*3)
 // VI9: v_mov_b32_dpp v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x42,0x01,0xff]
 
 v_mov_b32 v0, v0 quad_perm:[one,two+one,zero,2-one] row_mask:2*5 bank_mask:0x2-one bound_ctrl:1-1
-// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
+// VI9: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]

llvm/test/MC/Disassembler/AMDGPU/dl-insts.txt

 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x03
 
 # CHECK: v_fmac_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x0f
 
 # CHECK: v_fmac_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_fmac_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x08,0x00]
+# CHECK: v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x08,0x00
 
 # CHECK: v_fmac_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x10,0x00
 
 # CHECK: v_fmac_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x20,0x00
 

llvm/test/MC/Disassembler/AMDGPU/dpp_vi.txt

 0xfa 0x02 0x00 0x7e 0x00 0x41 0x01 0xff
 
 # VI: v_mov_b32_dpp v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x42,0x01,0xff]
 0xfa 0x02 0x00 0x7e 0x00 0x42 0x01 0xff
 
 # VI: v_mov_b32_dpp v0, v0 row_bcast:31 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x43,0x01,0xff]
 0xfa 0x02 0x00 0x7e 0x00 0x43 0x01 0xff
 
-# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xa1
 
 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xaf]
 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xaf
 
 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xf1]
 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xf1
 
-# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xff]
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xff]
 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xff
 
 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xa1]
 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xa1
 
-# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xaf]
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xaf]
 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xaf
 
-# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xf1]
+# VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xf1]
 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xf1
 
-# VI: v_cvt_u32_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x0e,0x00,0x7e,0x00,0x01,0x09,0xa1]
+# VI: v_cvt_u32_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x0e,0x00,0x7e,0x00,0x01,0x09,0xa1]
 0xfa 0x0e 0x00 0x7e 0x00 0x01 0x09 0xa1
 
-# VI: v_fract_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x36,0x00,0x7e,0x00,0x01,0x09,0xa1]
+# VI: v_fract_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x36,0x00,0x7e,0x00,0x01,0x09,0xa1]
 0xfa 0x36 0x00 0x7e 0x00 0x01 0x09 0xa1
 
-# VI: v_sin_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x52,0x00,0x7e,0x00,0x01,0x09,0xa1]
+# VI: v_sin_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x52,0x00,0x7e,0x00,0x01,0x09,0xa1]
 0xfa 0x52 0x00 0x7e 0x00 0x01 0x09 0xa1
 
-# VI: v_add_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x09,0xa1]
+# VI: v_add_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x09,0xa1]
 0xfa 0x00 0x00 0x02 0x00 0x01 0x09 0xa1
 
-# VI: v_min_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x14,0x00,0x01,0x09,0xa1]
+# VI: v_min_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x14,0x00,0x01,0x09,0xa1]
 0xfa 0x00 0x00 0x14 0x00 0x01 0x09 0xa1
 
-# VI: v_and_b32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x26,0x00,0x01,0x09,0xa1]
+# VI: v_and_b32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x26,0x00,0x01,0x09,0xa1]
 0xfa 0x00 0x00 0x26 0x00 0x01 0x09 0xa1
 
-# VI: v_add_f32_dpp v0, -v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x19,0xa1]
+# VI: v_add_f32_dpp v0, -v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x19,0xa1]
 0xfa 0x00 0x00 0x02 0x00 0x01 0x19 0xa1
 
-# VI: v_add_f32_dpp v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x89,0xa1]
+# VI: v_add_f32_dpp v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x89,0xa1]
 0xfa 0x00 0x00 0x02 0x00 0x01 0x89 0xa1
 
-# VI: v_add_f32_dpp v0, -v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x99,0xa1]
+# VI: v_add_f32_dpp v0, -v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x99,0xa1]
 0xfa 0x00 0x00 0x02 0x00 0x01 0x99 0xa1
 
-# VI: v_add_f32_dpp v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x69,0xa1]
+# VI: v_add_f32_dpp v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x69,0xa1]
 0xfa 0x00 0x00 0x02 0x00 0x01 0x69 0xa1
 
 # VI: v_mac_f32_dpp v76, v76, v114  quad_perm:[2,3,0,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xe4,0x98,0x2c,0x4c,0x4e,0x00,0xff]
 0xfa 0xe4 0x98 0x2c 0x4c 0x4e 0x00 0xff
 
-# VI: v_mac_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x06,0x02,0x46,0x02,0x01,0x09,0xa1]
+# VI: v_mac_f16_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x46,0x02,0x01,0x09,0xa1]
 0xfa 0x06 0x02 0x46 0x02 0x01 0x09 0xa1
 
 # VI: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00
 
 # VI: v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x00,0x01,0x0f,0x01,0x00]
 0xfa,0x04,0x0a,0x00,0x01,0x0f,0x01,0x00

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

 0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00
 
 # GFX10: v_add_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x10,0x00
 
 # GFX10: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x00
 
-# GFX10: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
+# GFX10: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00
 
 # GFX10: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01
 
 # GFX10: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00
 
 # GFX10: v_add_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x40,0x00]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x40,0x00
 
 # GFX10: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x00
 
-# GFX10: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
+# GFX10: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00
 
 # GFX10: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01
 
 # GFX10: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x4f,0xd5,0x6a,0x04,0x0e,0x04
 
 # GFX10: v_and_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x37,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x37,0x01,0xe4,0x00,0x00
 
 # GFX10: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x00
 
-# GFX10: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
+# GFX10: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00
 
 # GFX10: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01
 
 # GFX10: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x08,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_ashrrev_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x31,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x31,0x01,0xe4,0x00,0x00
 
 # GFX10: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x00
 
-# GFX10: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x08,0x00]
+# GFX10: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x30,0x01,0xe4,0x08,0x00
 
 # GFX10: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x01
 
 # GFX10: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x63,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_bfrev_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x70,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x70,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x70,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_ceil_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xb8,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xb8,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_ceil_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x44,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x44,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x01,0xd5,0xff,0x05,0x1a,0x00
 
 # GFX10: v_cos_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xc2,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xc2,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_cos_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x6c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x6c,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x07,0x46,0xd5,0x01,0x05,0x0e,0x04
 
 # GFX10: v_cvt_f16_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x14,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x14,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x14,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_cvt_f16_i16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xa2,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xa2,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xa2,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_cvt_f16_u16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xa0,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xa0,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xa0,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_cvt_f32_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x16,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x16,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x01,0x8f,0xd5,0x01,0x01,0x00,0x00
 
 # GFX10: v_cvt_f32_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x0a,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x0a,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_cvt_f32_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x0c,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x0c,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_cvt_f32_ubyte0_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x22,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x22,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x22,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_cvt_f32_ubyte1_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x24,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x24,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x24,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_cvt_f32_ubyte2_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x26,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x26,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x26,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_cvt_f32_ubyte3_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x28,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x28,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x96,0xd5,0x6a,0x00,0x00,0x00
 
 # GFX10: v_cvt_flr_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x1a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x1a,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_cvt_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xa6,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xa6,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_cvt_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x10,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x10,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x01,0x83,0xd5,0x01,0x01,0x00,0x00
 
 # GFX10: v_cvt_norm_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xc6,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xc6,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_cvt_norm_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xc8,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xc8,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_cvt_off_f32_i4_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x1c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x1c,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x03,0x2f,0xd5,0x01,0x05,0x02,0x00
 
 # GFX10: v_cvt_rpi_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x18,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x18,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x18,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_cvt_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xa4,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xa4,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_cvt_u32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x0e,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x6d,0xd5,0x6a,0x04,0x0e,0x04
 
 # GFX10: v_exp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xb0,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xb0,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_exp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x4a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x4a,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_ffbh_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x76,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x76,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x76,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_ffbh_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x72,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x72,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x72,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_ffbl_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x74,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x74,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x74,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
 # GFX10: v_floor_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xb6,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xb6,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_floor_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x48,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x48,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xff,0x07,0x0a,0x58,0x41,0x31,0x21,0x11
 
 # GFX10: v_fract_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xbe,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xbe,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_fract_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x40,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x40,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x01,0xbe,0xd5,0x01,0x01,0x00,0x00
 
 # GFX10: v_frexp_exp_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xb4,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xb4,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_frexp_exp_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x7e,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x01,0xbc,0xd5,0x01,0x01,0x00,0x00
 
 # GFX10: v_frexp_mant_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xb2,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xb2,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_frexp_mant_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x80,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x80,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0xfe,0x77,0x01,0xe4,0x00,0x00
 
 # GFX10: v_ldexp_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x10,0x00
 
 # GFX10: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x00
 
-# GFX10: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x08,0x00]
+# GFX10: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x08,0x00
 
 # GFX10: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x01
 
 # GFX10: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x4d,0xd5,0x6a,0x04,0x0e,0x04
 
 # GFX10: v_log_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xae,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xae,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xae,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_log_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x4e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x4e,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x14,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_lshlrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00
 
 # GFX10: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00
 
-# GFX10: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
+# GFX10: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00
 
 # GFX10: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01
 
 # GFX10: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x07,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_lshrrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00
 
 # GFX10: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00
 
-# GFX10: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
+# GFX10: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00
 
 # GFX10: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01
 
 # GFX10: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0xfe,0x73,0x01,0xe4,0x00,0x00
 
 # GFX10: v_max_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x72,0x01,0xe4,0x10,0x00
 
 # GFX10: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x00
 
-# GFX10: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x08,0x00]
+# GFX10: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x72,0x01,0xe4,0x08,0x00
 
 # GFX10: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x01
 
 # GFX10: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x10,0x00
 
 # GFX10: v_max_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x40,0x00]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x40,0x00
 
 # GFX10: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x00
 
-# GFX10: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
+# GFX10: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00
 
 # GFX10: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01
 
 # GFX10: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x0a,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_max_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00
 
 # GFX10: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00
 
-# GFX10: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
+# GFX10: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00
 
 # GFX10: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01
 
 # GFX10: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x09,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_max_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00
 
 # GFX10: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00
 
-# GFX10: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
+# GFX10: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00
 
 # GFX10: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01
 
 # GFX10: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0xfe,0x75,0x01,0xe4,0x00,0x00
 
 # GFX10: v_min_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x10,0x00
 
 # GFX10: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x00
 
-# GFX10: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
+# GFX10: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00
 
 # GFX10: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x01
 
 # GFX10: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x10,0x00
 
 # GFX10: v_min_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x40,0x00]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x40,0x00
 
 # GFX10: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
+# GFX10: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x0c,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_min_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00
 
 # GFX10: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00
 
-# GFX10: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
+# GFX10: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00
 
 # GFX10: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01
 
 # GFX10: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x0b,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_min_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00
 
 # GFX10: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00
 
-# GFX10: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
+# GFX10: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00
 
 # GFX10: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01
 
 # GFX10: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03
 

 0xf9,0x04,0x0a,0x26,0x6a,0x06,0x86,0x06
 
 # GFX10: v_mov_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x02,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x02,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0xfe,0x6b,0x01,0xe4,0x00,0x00
 
 # GFX10: v_mul_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x10,0x00
 
 # GFX10: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x00
 
-# GFX10: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x08,0x00]
+# GFX10: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x08,0x00
 
 # GFX10: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x01
 
 # GFX10: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x10,0x00
 
 # GFX10: v_mul_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x40,0x00]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x40,0x00
 
 # GFX10: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x00
 
-# GFX10: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
+# GFX10: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00
 
 # GFX10: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01
 
 # GFX10: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x6c,0xd5,0x6a,0x04,0x02,0x00
 
 # GFX10: v_mul_hi_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x15,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x15,0x01,0xe4,0x00,0x00
 
 # GFX10: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x00
 
-# GFX10: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
+# GFX10: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00
 
 # GFX10: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01
 
 # GFX10: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x6a,0xd5,0x6a,0x04,0x02,0x00
 
 # GFX10: v_mul_hi_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x19,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x19,0x01,0xe4,0x00,0x00
 
 # GFX10: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x00
 
-# GFX10: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
+# GFX10: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00
 
 # GFX10: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01
 
 # GFX10: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03
 

 0xf9,0x04,0x0a,0x18,0x6a,0x06,0x86,0x06
 
 # GFX10: v_mul_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x13,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x13,0x01,0xe4,0x00,0x00
 
 # GFX10: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x00
 
-# GFX10: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
+# GFX10: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00
 
 # GFX10: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01
 
 # GFX10: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x10,0x00
 
 # GFX10: v_mul_legacy_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x40,0x00]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x40,0x00
 
 # GFX10: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
+# GFX10: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x69,0xd5,0x6a,0x04,0x02,0x00
 
 # GFX10: v_mul_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x17,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x17,0x01,0xe4,0x00,0x00
 
 # GFX10: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x00
 
-# GFX10: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
+# GFX10: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00
 
 # GFX10: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01
 
 # GFX10: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03
 

 0x00,0x00,0x00,0x7e
 
 # GFX10: v_not_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x6e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x6e,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x72,0xd7,0x6a,0x04,0x0e,0x04
 
 # GFX10: v_or_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x39,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x39,0x01,0xe4,0x00,0x00
 
 # GFX10: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x00
 
-# GFX10: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
+# GFX10: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00
 
 # GFX10: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01
 
 # GFX10: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x72,0xd5,0x6a,0x04,0x0e,0x04
 
 # GFX10: v_rcp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xa8,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xa8,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_rcp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x54,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x54,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x01,0xaf,0xd5,0x01,0x01,0x00,0x00
 
 # GFX10: v_rcp_iflag_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x56,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x56,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x60,0xd7,0xff,0x05,0x00,0x00
 
 # GFX10: v_rndne_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xbc,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xbc,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_rndne_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x46,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x46,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x99,0xd5,0x6a,0x00,0x00,0x00
 
 # GFX10: v_rsq_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xac,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xac,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xac,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_rsq_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x5c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x5c,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x5a,0xd5,0x6a,0x04,0x0e,0x04
 
 # GFX10: v_sin_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xc0,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xc0,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_sin_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x6a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x6a,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_sqrt_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xaa,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xaa,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_sqrt_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x66,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x66,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0xfe,0x67,0x01,0xe4,0x00,0x00
 
 # GFX10: v_sub_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00
 
 # GFX10: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x00
 
-# GFX10: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
+# GFX10: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00
 
 # GFX10: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01
 
 # GFX10: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00
 
 # GFX10: v_sub_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x40,0x00]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x40,0x00
 
 # GFX10: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x00
 
-# GFX10: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
+# GFX10: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00
 
 # GFX10: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01
 
 # GFX10: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0xfe,0x69,0x01,0xe4,0x00,0x00
 
 # GFX10: v_subrev_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x10,0x00
 
 # GFX10: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x00
 
-# GFX10: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x08,0x00]
+# GFX10: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x08,0x00
 
 # GFX10: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x01
 
 # GFX10: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x03
 

 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00
 
 # GFX10: v_subrev_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x40,0x00]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x40,0x00
 
 # GFX10: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x00
 
-# GFX10: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
+# GFX10: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00
 
 # GFX10: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01
 
 # GFX10: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03
 

 0x05,0x01,0x74,0xd5,0x01,0x05,0x02,0x00
 
 # GFX10: v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xba,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0xba,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0xf9,0xba,0x0a,0x7e,0x01,0x06,0x26,0x00
 
 # GFX10: v_trunc_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x42,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x42,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x00
 
-# GFX10: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# GFX10: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # GFX10: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x01]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # GFX10: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x45,0xd7,0x6a,0x04,0x0e,0x04
 
 # GFX10: v_xnor_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x3d,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x3d,0x01,0xe4,0x00,0x00
 
 # GFX10: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x00
 
-# GFX10: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
+# GFX10: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00
 
 # GFX10: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01
 
 # GFX10: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03
 

 0x05,0x00,0x78,0xd5,0x6a,0x04,0x0e,0x04
 
 # GFX10: v_xor_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x3b,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x3b,0x01,0xe4,0x00,0x00
 
 # GFX10: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x00
 
-# GFX10: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
+# GFX10: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00
 
 # GFX10: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01]
 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01
 
 # GFX10: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03
 

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_dpp16.txt

 0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x01
 
 # GFX10: v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x03]
 0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x03
 
 # GFX10: v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x0f]
 0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x0f
 
-# GFX10: v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x08,0x00]
+# GFX10: v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x08,0x00]
 0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x08,0x00
 
 # GFX10: v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x04,0x00
 
 # GFX10: v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00
 

 0xfa,0x04,0x0a,0x74,0x01,0x1b,0x04,0x00
 
 # GFX10: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x04,0x00]
 0xfa,0x04,0x0a,0x76,0x01,0x1b,0x04,0x00
 
 # GFX10: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0x00]
 0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0x00
 
-# GFX10: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x08,0x00]
+# GFX10: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x08,0x00]
 0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x08,0x00
 
 # GFX10: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x04,0x00]
 0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x04,0x00
 
 # GFX10: v_sub_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0x00]
 0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0x00
 

llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt

 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0a,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x0a,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0c,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x0c,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_u32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_u32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_u32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f16_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_f16_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_f32_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_rpi_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_rpi_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_flr_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_flr_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_ubyte0_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x22,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x22,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_ubyte1_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x24,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x24,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_ubyte2_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x26,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x26,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_ubyte3_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x28,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x28,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_fract_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x36,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x36,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_fract_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_fract_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_trunc_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_trunc_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ceil_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_ceil_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rndne_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rndne_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_floor_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_floor_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_exp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_exp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_log_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_log_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rcp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rcp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rcp_iflag_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rcp_iflag_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rsq_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rsq_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sqrt_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sqrt_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sin_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sin_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cos_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cos_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_bfrev_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x58,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x58,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_ffbh_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5a,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x5a,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_ffbl_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5c,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x5c,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_ffbh_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5e,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x5e,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_frexp_exp_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x66,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x66,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_frexp_exp_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_frexp_exp_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_frexp_mant_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_frexp_mant_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f16_i16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x74,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x74,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x76,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x76,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_u16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_u16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rcp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rcp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sqrt_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sqrt_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rsq_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rsq_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_log_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_log_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_exp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_exp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_frexp_mant_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_frexp_mant_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_frexp_exp_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_frexp_exp_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_floor_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_floor_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ceil_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_ceil_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_trunc_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_trunc_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rndne_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rndne_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_fract_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_fract_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sin_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sin_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cos_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cos_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_exp_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_exp_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_log_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_log_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x01
 
 # CHECK: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x03
 
 # CHECK: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00]
+# CHECK: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00
 
 # CHECK: v_add_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x10,0x00
 
 # CHECK: v_add_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
+# CHECK: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sub_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sub_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
+# CHECK: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subrev_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00
 
 # CHECK: v_subrev_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_legacy_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00
 
 # CHECK: v_mul_legacy_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00
 
 # CHECK: v_mul_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06
 
 # CHECK: v_mul_hi_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06
 
 # CHECK: v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06
 
 # CHECK: v_mul_hi_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06
 
 # CHECK: v_min_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x10,0x00
 
 # CHECK: v_min_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x10,0x00
 
 # CHECK: v_max_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06
 
 # CHECK: v_max_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x1b,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x1b,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06
 
 # CHECK: v_min_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x1d,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x1d,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06
 
 # CHECK: v_max_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06
 
 # CHECK: v_lshrrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01
 
 # CHECK: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03
 
 # CHECK: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
+# CHECK: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06
 
 # CHECK: v_ashrrev_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
+# CHECK: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00
 
 # CHECK: v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06
 
 # CHECK: v_lshlrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01
 
 # CHECK: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03
 
 # CHECK: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
+# CHECK: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00
 
 # CHECK: v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06
 
 # CHECK: v_and_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01
 
 # CHECK: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03
 
 # CHECK: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
+# CHECK: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00
 
 # CHECK: v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06
 
 # CHECK: v_or_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01
 
 # CHECK: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03
 
 # CHECK: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
+# CHECK: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00
 
 # CHECK: v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06
 
 # CHECK: v_xor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x2b,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x2b,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00]
+# CHECK: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06
 
 # CHECK: v_mac_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x2d,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x2d,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
+# CHECK: v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mac_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x10,0x00
 
 # CHECK: v_mac_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x01
 
 # CHECK: v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x03
 
 # CHECK: v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00]
+# CHECK: v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06
 
 # CHECK: v_sub_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
+# CHECK: v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06
 
 # CHECK: v_subrev_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
+# CHECK: v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00
 
 # CHECK: v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06
 
 # CHECK: v_addc_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01
 
 # CHECK: v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03
 
 # CHECK: v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
+# CHECK: v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06
 
 # CHECK: v_subb_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
+# CHECK: v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06
 
 # CHECK: v_subbrev_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
+# CHECK: v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06
 
 # CHECK: v_add_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x3f,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x3f,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00]
+# CHECK: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_add_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_add_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00]
+# CHECK: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sub_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sub_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00]
+# CHECK: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subrev_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x10,0x00
 
 # CHECK: v_subrev_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x10,0x00
 
 # CHECK: v_mul_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00]
+# CHECK: v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mac_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x10,0x00
 
 # CHECK: v_mac_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00]
+# CHECK: v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06
 
 # CHECK: v_sub_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00]
+# CHECK: v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06
 
 # CHECK: v_subrev_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00]
+# CHECK: v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06
 
 # CHECK: v_mul_lo_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00
 
 # CHECK: v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06
 
 # CHECK: v_lshlrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x01
 
 # CHECK: v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x03
 
 # CHECK: v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00]
+# CHECK: v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00
 
 # CHECK: v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06
 
 # CHECK: v_lshrrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x57,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x57,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x01
 
 # CHECK: v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x03
 
 # CHECK: v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00]
+# CHECK: v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06
 
 # CHECK: v_ashrrev_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x59,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x59,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00]
+# CHECK: v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06
 
 # CHECK: v_max_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x5b,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x5b,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x10,0x00
 
 # CHECK: v_max_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x10,0x00
 
 # CHECK: v_min_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06
 
 # CHECK: v_max_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x61,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x61,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06
 
 # CHECK: v_min_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x63,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x63,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06
 
 # CHECK: v_min_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06
 
 # CHECK: v_ldexp_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
+# CHECK: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ldexp_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00
 
 # CHECK: v_ldexp_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00
 

llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt

 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0a,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x0a,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0c,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x0c,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_u32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_u32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_u32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f16_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_f16_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_f32_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_rpi_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_rpi_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_flr_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_flr_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_ubyte0_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x22,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x22,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_ubyte1_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x24,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x24,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_ubyte2_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x26,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x26,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f32_ubyte3_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x28,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x28,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_fract_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x36,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x36,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_fract_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_fract_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_trunc_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_trunc_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ceil_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_ceil_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rndne_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rndne_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_floor_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_floor_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_exp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_exp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_log_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_log_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rcp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rcp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rcp_iflag_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rcp_iflag_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rsq_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rsq_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sqrt_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sqrt_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sin_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sin_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cos_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cos_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_bfrev_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x58,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x58,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_ffbh_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5a,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x5a,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_ffbl_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5c,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x5c,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_ffbh_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x5e,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x5e,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_frexp_exp_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x66,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x66,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_frexp_exp_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_frexp_exp_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_frexp_mant_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_frexp_mant_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_f16_i16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x74,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x74,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
 0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00
 
 # CHECK: v_cvt_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x76,0xfe,0x7f,0x01,0x06,0x06,0x00]
 0xf9,0x76,0xfe,0x7f,0x01,0x06,0x06,0x00
 

 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_u16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_u16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cvt_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cvt_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rcp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rcp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sqrt_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sqrt_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rsq_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rsq_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_log_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_log_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_exp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_exp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_frexp_mant_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_frexp_mant_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_frexp_exp_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_frexp_exp_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_floor_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_floor_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ceil_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_ceil_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_trunc_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_trunc_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_rndne_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_rndne_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_fract_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_fract_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sin_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sin_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cos_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_cos_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_exp_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_exp_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x03]
 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+# CHECK: v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x08,0x00]
 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_log_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x10,0x00]
 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_log_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x20,0x00]
 0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x01
 
 # CHECK: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x03
 
 # CHECK: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00]
+# CHECK: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00
 
 # CHECK: v_add_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x10,0x00
 
 # CHECK: v_add_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
+# CHECK: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sub_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sub_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
+# CHECK: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subrev_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00
 
 # CHECK: v_subrev_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_legacy_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00
 
 # CHECK: v_mul_legacy_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00
 
 # CHECK: v_mul_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06
 
 # CHECK: v_mul_hi_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06
 
 # CHECK: v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06
 
 # CHECK: v_mul_hi_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06
 
 # CHECK: v_min_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x10,0x00
 
 # CHECK: v_min_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x10,0x00
 
 # CHECK: v_max_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06
 
 # CHECK: v_max_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x1b,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x1b,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06
 
 # CHECK: v_min_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x1d,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x1d,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06
 
 # CHECK: v_max_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06
 
 # CHECK: v_lshrrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01
 
 # CHECK: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03
 
 # CHECK: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
+# CHECK: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06
 
 # CHECK: v_ashrrev_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
+# CHECK: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00
 
 # CHECK: v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06
 
 # CHECK: v_lshlrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01
 
 # CHECK: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03
 
 # CHECK: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
+# CHECK: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00
 
 # CHECK: v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06
 
 # CHECK: v_and_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01
 
 # CHECK: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03
 
 # CHECK: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
+# CHECK: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00
 
 # CHECK: v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06
 
 # CHECK: v_or_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01
 
 # CHECK: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03
 
 # CHECK: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
+# CHECK: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00
 
 # CHECK: v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06
 
 # CHECK: v_xor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x2b,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x2b,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00]
+# CHECK: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00
 
 # CHECK: v_mac_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00
 

 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
+# CHECK: v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mac_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x10,0x00
 
 # CHECK: v_mac_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x01
 
 # CHECK: v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x03
 
 # CHECK: v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00]
+# CHECK: v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06
 
 # CHECK: v_sub_co_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
+# CHECK: v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06
 
 # CHECK: v_subrev_co_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
+# CHECK: v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00
 
 # CHECK: v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06
 
 # CHECK: v_addc_co_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01
 
 # CHECK: v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03
 
 # CHECK: v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
+# CHECK: v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06
 
 # CHECK: v_subb_co_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
+# CHECK: v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06
 
 # CHECK: v_subbrev_co_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
+# CHECK: v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06
 
 # CHECK: v_add_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x3f,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x3f,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00]
+# CHECK: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_add_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_add_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00]
+# CHECK: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sub_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x10,0x00
 
 # CHECK: v_sub_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x40,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00]
+# CHECK: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subrev_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x10,0x00
 
 # CHECK: v_subrev_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x42,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x10,0x00
 
 # CHECK: v_mul_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x44,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00]
+# CHECK: v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mac_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x10,0x00
 
 # CHECK: v_mac_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x46,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00]
+# CHECK: v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06
 
 # CHECK: v_sub_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00]
+# CHECK: v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06
 
 # CHECK: v_subrev_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00]
+# CHECK: v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00
 
 # CHECK: v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06
 
 # CHECK: v_mul_lo_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x01
 
 # CHECK: v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x03
 
 # CHECK: v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00]
+# CHECK: v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00
 
 # CHECK: v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06
 
 # CHECK: v_lshlrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x01
 
 # CHECK: v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x03
 
 # CHECK: v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00]
+# CHECK: v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00
 
 # CHECK: v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06
 
 # CHECK: v_lshrrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x57,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x57,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x01
 
 # CHECK: v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x03
 
 # CHECK: v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00]
+# CHECK: v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06
 
 # CHECK: v_ashrrev_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x59,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x59,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00]
+# CHECK: v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06
 
 # CHECK: v_max_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x5b,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x5b,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x10,0x00
 
 # CHECK: v_max_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x10,0x00
 
 # CHECK: v_min_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06
 
 # CHECK: v_max_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x61,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x61,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x01
 
 # CHECK: v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x03
 
 # CHECK: v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00]
+# CHECK: v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06
 
 # CHECK: v_min_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x63,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x63,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00
 
 # CHECK: v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06
 
 # CHECK: v_min_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01
 
 # CHECK: v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03
 
 # CHECK: v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
+# CHECK: v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06
 
 # CHECK: v_ldexp_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01
 
 # CHECK: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03
 
 # CHECK: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
+# CHECK: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00
 
 # CHECK: v_ldexp_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00
 
 # CHECK: v_ldexp_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x01
 
 # CHECK: v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x03
 
 # CHECK: v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x08,0x00]
+# CHECK: v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x08,0x00
 
 # CHECK: v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06
 
 # CHECK: v_sub_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x6b,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x6b,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x01
 
 # CHECK: v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x08,0x00]
+# CHECK: v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x08,0x00
 
 # CHECK: v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x06
 
 # CHECK: v_subrev_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x6d,0x01,0x06,0x06,0x06]
 0xf9,0x04,0xfe,0x6d,0x01,0x06,0x06,0x06
 

 0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x01
 
 # CHECK: v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x03
 
 # CHECK: v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x08,0x00]
+# CHECK: v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x08,0x00
 
 # CHECK: v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x06]
 0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x06
 
 # CHECK: v_cmp_class_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x88,0x06,0x06]
 0xf9,0x04,0x20,0x7c,0x01,0x88,0x06,0x06
 

llvm/test/MC/Disassembler/AMDGPU/xdl-insts-gfx1011-gfx1012.txt

 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03
 
 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f
 
 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_dot2c_f32_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
+# CHECK: v_dot2c_f32_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00
 
 # CHECK: v_dot2c_f32_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00
 
 # CHECK: v_dot2c_f32_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03
 
 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f
 
 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_dot4c_i32_i8_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
+# CHECK: v_dot4c_i32_i8_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00

llvm/test/MC/Disassembler/AMDGPU/xdl-insts-gfx908.txt

 0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x01
 
 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x03
 
 # CHECK: v_dot2c_f32_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_dot2c_f32_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x08,0x00]
+# CHECK: v_dot2c_f32_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x08,0x00
 
 # CHECK: v_dot2c_f32_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x10,0x00
 
 # CHECK: v_dot2c_f32_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x20,0x00]
 0xfa,0x04,0x0a,0x6e,0x01,0xe4,0x20,0x00
 

 0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x01
 
 # CHECK: v_dot2c_i32_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x03
 
 # CHECK: v_dot2c_i32_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x70,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_dot2c_i32_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x08,0x00]
+# CHECK: v_dot2c_i32_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x70,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x70,0x01,0xe4,0x08,0x00
 
 # CHECK: v_dot4c_i32_i8_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x72]
 0x01,0x05,0x0a,0x72
 
 # CHECK: v_dot4c_i32_i8_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x73]
 0x01,0x05,0xfe,0x73
 

 0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x01
 
 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x03
 
 # CHECK: v_dot4c_i32_i8_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_dot4c_i32_i8_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x08,0x00]
+# CHECK: v_dot4c_i32_i8_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x72,0x01,0xe4,0x08,0x00
 
 # CHECK: v_dot8c_i32_i4_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x74]
 0x01,0x05,0x0a,0x74
 
 # CHECK: v_dot8c_i32_i4_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x75]
 0x01,0x05,0xfe,0x75
 

 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x01
 
 # CHECK: v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x03]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x03
 
 # CHECK: v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x0f]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x0f
 
-# CHECK: v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
+# CHECK: v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00
 
 # CHECK: v_pk_fmac_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x78]
 0x01,0x05,0x0a,0x78
 
 # CHECK: v_pk_fmac_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x79]
 0x01,0x05,0xfe,0x79