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Differential D97022

[RISCV] Remove redundant test cases for index segment load (3/8).
ClosedPublic

Authored by HsiangKai on Feb 18 2021, 7:32 PM.

Details

Reviewers
craig.topper
Commits
rG8cc0b1cbea7d: [RISCV] Remove redundant test cases for index segment load (3/8).

Diff Detail

Unit TestsFailed

TimeTest
790 msx64 windows > MLIR.Examples/Toy/Ch6::jit.toy
4,770 msx64 windows > MLIR.Examples/Toy/Ch7::jit.toy

Event Timeline

HsiangKai created this revision.Feb 18 2021, 7:32 PM
Herald added subscribers: StephenFan, vkmr, frasercrmck and 26 others. · View Herald TranscriptFeb 18 2021, 7:32 PM
HsiangKai requested review of this revision.Feb 18 2021, 7:32 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 18 2021, 7:32 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
craig.topper accepted this revision.Feb 18 2021, 7:42 PM

LGTM

This revision is now accepted and ready to land.Feb 18 2021, 7:42 PM
This revision was landed with ongoing or failed builds.Feb 18 2021, 7:57 PM
Closed by commit rG8cc0b1cbea7d: [RISCV] Remove redundant test cases for index segment load (3/8). (authored by HsiangKai). · Explain Why
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rG8cc0b1cbea7d: [RISCV] Remove redundant test cases for index segment load (3/8)..
Harbormaster completed remote builds in B89846: Diff 324848.Feb 18 2021, 9:29 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
87355 lines

Diff 324848

llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll

This file has a very large number of changes (87,355 lines). Show File Contents