[X86] Zero AMX config buffer for non AVX512 cases.

[pengfei]

Summary

Zero AMX config buffer for non AVX512 cases.

[LuoYuanke]

llvm/lib/Target/X86/X86PreTileConfig.cpp

107

Can we remove the FIXME now?

127

SSE2 is by default enabled?

[pengfei]

Address Yuanke's comments.

llvm/lib/Target/X86/X86PreTileConfig.cpp

127

SSE2 is enabled on X64 by default, though it can be disabled. I added an assertion for it.

[LuoYuanke]

LGTM. Thanks.

llvm/lib/Target/X86/X86PreTileConfig.cpp

void X86PreTileConfig::getAnalysisUsage(AnalysisUsage &AU) const {
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 static void buildConfigMI(MachineBasicBlock::iterator MI, int FrameIdx,
                           const TargetInstrInfo *TII, MachineRegisterInfo *MRI,
                           const X86Subtarget *ST) {
   auto *MBB = MI->getParent();
 
+  // Zero stack slot.
   // FIXME: AMX should assume AVX512 enabled.
   if (ST->hasAVX512()) {
-    // Zero stack slot.
     Register Zmm = MRI->createVirtualRegister(&X86::VR512RegClass);
     BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::VPXORDZrr), Zmm)
         .addReg(Zmm, RegState::Undef)
         .addReg(Zmm, RegState::Undef);
     addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::VMOVUPSZmr)),
                       FrameIdx)
         .addReg(Zmm);
+  } else if (ST->hasAVX2()) {
+    Register Ymm = MRI->createVirtualRegister(&X86::VR256RegClass);
+    BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::VPXORYrr), Ymm)
+        .addReg(Ymm, RegState::Undef)
+        .addReg(Ymm, RegState::Undef);
+    addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::VMOVUPSYmr)),
+                      FrameIdx)
+        .addReg(Ymm);
+    addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::VMOVUPSYmr)),
+                      FrameIdx, 32)
+        .addReg(Ymm);
+  } else {
+    Register Xmm = MRI->createVirtualRegister(&X86::VR128RegClass);
+    BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::PXORrr), Xmm)
+        .addReg(Xmm, RegState::Undef)
+        .addReg(Xmm, RegState::Undef);
+    addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::MOVUPSmr)),
+                      FrameIdx)
+        .addReg(Xmm);
+    addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::MOVUPSmr)),
+                      FrameIdx, 16)
+        .addReg(Xmm);
+    addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::MOVUPSmr)),
+                      FrameIdx, 32)
+        .addReg(Xmm);
+    addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::MOVUPSmr)),
+                      FrameIdx, 48)
+        .addReg(Xmm);
   }
 
   // build psuedo ldtilecfg
   addFrameReference(BuildMI(*MBB, MI, DebugLoc(), TII->get(X86::LDTILECFG)),
                     FrameIdx);
 }
 
 static ShapeT getShape(const MachineInstr &MI, MachineRegisterInfo *MRI) {

llvm/test/CodeGen/X86/AMX/amx-config.ll

 ; AVX512-NEXT:    tilerelease
 ; AVX512-NEXT:    vzeroupper
 ; AVX512-NEXT:    retq
 ;
 ; AVX2-LABEL: test_api:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    testl %edi, %edi
 ; AVX2-NEXT:    movsbl %sil, %eax
+; AVX2-NEXT:    vxorps %ymm0, %ymm0, %ymm0
+; AVX2-NEXT:    vmovups %ymm0, -{{[0-9]+}}(%rsp)
+; AVX2-NEXT:    vmovups %ymm0, -{{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    movb $1, -{{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    movw %si, -{{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    movw %dx, -{{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    movw %dx, -{{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    ldtilecfg -{{[0-9]+}}(%rsp)
 ; AVX2-NEXT:    je .LBB0_2
 ; AVX2-NEXT:  # %bb.1:
 ; AVX2-NEXT:    movl $buf, %ecx
 ; AVX2-NEXT:    jmp .LBB0_3
 ; AVX2-NEXT:  .LBB0_2:
 ; AVX2-NEXT:    movl $buf2, %ecx
 ; AVX2-NEXT:  .LBB0_3:
 ; AVX2-NEXT:    movl $32, %edi
 ; AVX2-NEXT:    tileloadd (%rcx,%rdi), %tmm0
 ; AVX2-NEXT:    tileloadd (%rcx,%rdi), %tmm2
 ; AVX2-NEXT:    tileloadd (%rcx,%rdi), %tmm1
 ; AVX2-NEXT:    tdpbssd %tmm2, %tmm0, %tmm1
 ; AVX2-NEXT:    movl $buf, %ecx
 ; AVX2-NEXT:    movl $32, %esi
 ; AVX2-NEXT:    tilestored %tmm1, (%rcx,%rsi)
 ; AVX2-NEXT:    tilerelease
+; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; SSE2-LABEL: test_api:
 ; SSE2:       # %bb.0:
 ; SSE2-NEXT:    testl %edi, %edi
 ; SSE2-NEXT:    movsbl %sil, %eax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    movups %xmm0, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT:    movups %xmm0, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT:    movups %xmm0, -{{[0-9]+}}(%rsp)
+; SSE2-NEXT:    movups %xmm0, -{{[0-9]+}}(%rsp)
 ; SSE2-NEXT:    movb $1, -{{[0-9]+}}(%rsp)
 ; SSE2-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
 ; SSE2-NEXT:    movw %si, -{{[0-9]+}}(%rsp)
 ; SSE2-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
 ; SSE2-NEXT:    movw %dx, -{{[0-9]+}}(%rsp)
 ; SSE2-NEXT:    movb %al, -{{[0-9]+}}(%rsp)
 ; SSE2-NEXT:    movw %dx, -{{[0-9]+}}(%rsp)
 ; SSE2-NEXT:    ldtilecfg -{{[0-9]+}}(%rsp)