[libunwind] Add support for PC reg column in arm64

[charco]

Summary

This change adds support for the dwarf PC register column in arm64, allowing
CFI directives to make use of it.

As of the last revision of the DWARF for ARM 64-bit architecture[0], the pc
register has been added as a valir register, with number 32.

This allows libunwinder to restore both pc and lr, which is useful
for stack switches and signal contexts.

[0]:
https://github.com/ARM-software/abi-aa/blob/f52e1ad3f81254497a83578dc102f6aac89e52d0/aadwarf64/aadwarf64.rst

[danielkiss]

Could you add [libunwind] to the beginning of title?
but otherwise LGTM as the author of the corresponding dwarf spec change.

Thanks for this patch.

[phosek]

LGTM

[charco]

Add [libunwind] to the commit message.

[charco]

In D96901#2570117, @danielkiss wrote:

Could you add [libunwind] to the beginning of title?
but otherwise LGTM as the author of the corresponding dwarf spec change.

Thanks for this patch.

Thanks for the review! Maybe with this change the sigreturn code for linux can be simplified? (see https://reviews.llvm.org/D90898 for context)

[joerg]

I don't get this change. The restore code is literally returning by jumping to x30, so how is splitting PC and LR supposed to work?

[charco]

In D96901#2570259, @joerg wrote:

I don't get this change. The restore code is literally returning by jumping to x30, so how is splitting PC and LR supposed to work?

My understanding is that it would be used with .cfi_return_column 32, so x30 is no longer used as the return address. I tested it locally in Fuchsia and it worked.

[joerg]

Let me rephrase then. The restore code explicitly ends in "ret x30". It cannot set "pc" separate from "x30" in the current form. I'm not saying that the DWARF register shouldn't be supported, but this change doesn't do that.

[charco]

In D96901#2570297, @joerg wrote:

Let me rephrase then. The restore code explicitly ends in "ret x30". It cannot set "pc" separate from "x30" in the current form. I'm not saying that the DWARF register shouldn't be supported, but this change doesn't do that.

I am not really familiar with libunwind. What restore code are you talking about? If there's anything else that needs to be changed, I would be happy to do so.

[joerg]

Registers_arm64::jumpto in UnwindRegistersRestore.S.

[charco]

In D96901#2570327, @joerg wrote:

Registers_arm64::jumpto in UnwindRegistersRestore.S.

Isn't that code filling x30 with the __pc register?

Line 587 says: ldr x30, [x0, #0x100] // restore pc into lr

And offset #0x100 is __pc

[charco]

In D96901#2570338, @charco wrote:

In D96901#2570327, @joerg wrote:

Registers_arm64::jumpto in UnwindRegistersRestore.S.

Isn't that code filling x30 with the __pc register?

Line 587 says: ldr x30, [x0, #0x100] // restore pc into lr

And offset #0x100 is __pc

Ah, but we are not restoring the x30 register.

libunwind/include/libunwind.h

enum {
   UNW_PPC64_VS60    = UNW_PPC64_V28,
   UNW_PPC64_VS61    = UNW_PPC64_V29,
   UNW_PPC64_VS62    = UNW_PPC64_V30,
   UNW_PPC64_VS63    = UNW_PPC64_V31
 };
 
 // 64-bit ARM64 registers
 enum {
-  UNW_ARM64_X0  = 0,
-  UNW_ARM64_X1  = 1,
-  UNW_ARM64_X2  = 2,
-  UNW_ARM64_X3  = 3,
-  UNW_ARM64_X4  = 4,
-  UNW_ARM64_X5  = 5,
-  UNW_ARM64_X6  = 6,
-  UNW_ARM64_X7  = 7,
-  UNW_ARM64_X8  = 8,
-  UNW_ARM64_X9  = 9,
+  UNW_ARM64_X0 = 0,
+  UNW_ARM64_X1 = 1,
+  UNW_ARM64_X2 = 2,
+  UNW_ARM64_X3 = 3,
+  UNW_ARM64_X4 = 4,
+  UNW_ARM64_X5 = 5,
+  UNW_ARM64_X6 = 6,
+  UNW_ARM64_X7 = 7,
+  UNW_ARM64_X8 = 8,
+  UNW_ARM64_X9 = 9,
   UNW_ARM64_X10 = 10,
   UNW_ARM64_X11 = 11,
   UNW_ARM64_X12 = 12,
   UNW_ARM64_X13 = 13,
   UNW_ARM64_X14 = 14,
   UNW_ARM64_X15 = 15,
   UNW_ARM64_X16 = 16,
   UNW_ARM64_X17 = 17,
   UNW_ARM64_X18 = 18,
   UNW_ARM64_X19 = 19,
   UNW_ARM64_X20 = 20,
   UNW_ARM64_X21 = 21,
   UNW_ARM64_X22 = 22,
   UNW_ARM64_X23 = 23,
   UNW_ARM64_X24 = 24,
   UNW_ARM64_X25 = 25,
   UNW_ARM64_X26 = 26,
   UNW_ARM64_X27 = 27,
   UNW_ARM64_X28 = 28,
   UNW_ARM64_X29 = 29,
-  UNW_ARM64_FP  = 29,
+  UNW_ARM64_FP = 29,
   UNW_ARM64_X30 = 30,
-  UNW_ARM64_LR  = 30,
+  UNW_ARM64_LR = 30,
   UNW_ARM64_X31 = 31,
-  UNW_ARM64_SP  = 31,
+  UNW_ARM64_SP = 31,
+  UNW_ARM64_PC = 32,
   // reserved block
   UNW_ARM64_RA_SIGN_STATE = 34,
   // reserved block
-  UNW_ARM64_D0  = 64,
-  UNW_ARM64_D1  = 65,
-  UNW_ARM64_D2  = 66,
-  UNW_ARM64_D3  = 67,
-  UNW_ARM64_D4  = 68,
-  UNW_ARM64_D5  = 69,
-  UNW_ARM64_D6  = 70,
-  UNW_ARM64_D7  = 71,
-  UNW_ARM64_D8  = 72,
-  UNW_ARM64_D9  = 73,
+  UNW_ARM64_D0 = 64,
+  UNW_ARM64_D1 = 65,
+  UNW_ARM64_D2 = 66,
+  UNW_ARM64_D3 = 67,
+  UNW_ARM64_D4 = 68,
+  UNW_ARM64_D5 = 69,
+  UNW_ARM64_D6 = 70,
+  UNW_ARM64_D7 = 71,
+  UNW_ARM64_D8 = 72,
+  UNW_ARM64_D9 = 73,
   UNW_ARM64_D10 = 74,
   UNW_ARM64_D11 = 75,
   UNW_ARM64_D12 = 76,
   UNW_ARM64_D13 = 77,
   UNW_ARM64_D14 = 78,
   UNW_ARM64_D15 = 79,
   UNW_ARM64_D16 = 80,
   UNW_ARM64_D17 = 81,

libunwind/src/Registers.hpp

inline bool Registers_arm64::validRegister(int regNum) const {
   if (regNum == UNW_REG_SP)
     return true;
   if (regNum < 0)
     return false;
   if (regNum > 95)
     return false;
   if (regNum == UNW_ARM64_RA_SIGN_STATE)
     return true;
-  if ((regNum > 31) && (regNum < 64))
+  if ((regNum > 32) && (regNum < 64))
     return false;
   return true;
 }
 
 inline uint64_t Registers_arm64::getRegister(int regNum) const {
-  if (regNum == UNW_REG_IP)
+  if (regNum == UNW_REG_IP || regNum == UNW_ARM64_PC)
     return _registers.__pc;
-  if (regNum == UNW_REG_SP)
+  if (regNum == UNW_REG_SP || regNum == UNW_ARM64_SP)
     return _registers.__sp;
   if (regNum == UNW_ARM64_RA_SIGN_STATE)
     return _registers.__ra_sign_state;
-  if ((regNum >= 0) && (regNum < 32))
+  if (regNum == UNW_ARM64_FP)
+    return _registers.__fp;
+  if (regNum == UNW_ARM64_LR)
+    return _registers.__lr;
+  if ((regNum >= 0) && (regNum < 29))
     return _registers.__x[regNum];
   _LIBUNWIND_ABORT("unsupported arm64 register");
 }
 
 inline void Registers_arm64::setRegister(int regNum, uint64_t value) {
-  if (regNum == UNW_REG_IP)
+  if (regNum == UNW_REG_IP || regNum == UNW_ARM64_PC)
     _registers.__pc = value;
-  else if (regNum == UNW_REG_SP)
+  else if (regNum == UNW_REG_SP || regNum == UNW_ARM64_SP)
     _registers.__sp = value;
   else if (regNum == UNW_ARM64_RA_SIGN_STATE)
     _registers.__ra_sign_state = value;
-  else if ((regNum >= 0) && (regNum < 32))
+  else if (regNum == UNW_ARM64_FP)
+    _registers.__fp = value;
+  else if (regNum == UNW_ARM64_LR)
+    _registers.__lr = value;
+  else if ((regNum >= 0) && (regNum < 29))
     _registers.__x[regNum] = value;
   else
     _LIBUNWIND_ABORT("unsupported arm64 register");
 }
 
 inline const char *Registers_arm64::getRegisterName(int regNum) {
   switch (regNum) {
   case UNW_REG_IP:
inline const char *Registers_arm64::getRegisterName(int regNum) {
   case UNW_ARM64_X25:
     return "x25";
   case UNW_ARM64_X26:
     return "x26";
   case UNW_ARM64_X27:
     return "x27";
   case UNW_ARM64_X28:
     return "x28";
-  case UNW_ARM64_X29:
+  case UNW_ARM64_FP:
     return "fp";
-  case UNW_ARM64_X30:
+  case UNW_ARM64_LR:
     return "lr";
-  case UNW_ARM64_X31:
+  case UNW_ARM64_SP:
     return "sp";
+  case UNW_ARM64_PC:
+    return "pc";
   case UNW_ARM64_D0:
     return "d0";
   case UNW_ARM64_D1:
     return "d1";
   case UNW_ARM64_D2:
     return "d2";
   case UNW_ARM64_D3:
     return "d3";