[AMDGPU] Mark SMRD atomics

[rampitec]

Summary

We did not have atomic flags on SMRD, did not copy TSFlags
to real instructions, and did not have ret/noret atomic map.

At the moment it is NFC, but needed for D96469.

[arsenm]

llvm/lib/Target/AMDGPU/SMInstructions.td

600

Why parse this out instead of appending _RTN?

[rampitec]

llvm/lib/Target/AMDGPU/SMInstructions.td

600

It is real, _RTN is in the middle and full name is not available. I could construct proper name from the multiclass instantiating this, but it is more code.

[foad]

At the moment it is NFC

Doesn't this mean that SITargetLowering::AdjustInstrPostInstrSelection will start optimizing the ret form to the noret form?

[rampitec]

In D96823#2567703, @foad wrote:

At the moment it is NFC

Doesn't this mean that SITargetLowering::AdjustInstrPostInstrSelection will start optimizing the ret form to the noret form?

Hm... Theoretically.

[arsenm]

In D96823#2567703, @foad wrote:

At the moment it is NFC

Doesn't this mean that SITargetLowering::AdjustInstrPostInstrSelection will start optimizing the ret form to the noret form?

I don't think selecting the scalar atomics was ever supported

[rampitec]

In D96823#2568327, @arsenm wrote:

In D96823#2567703, @foad wrote:

At the moment it is NFC

Doesn't this mean that SITargetLowering::AdjustInstrPostInstrSelection will start optimizing the ret form to the noret form?

I don't think selecting the scalar atomics was ever supported

Right, I do not see patterns.

llvm/lib/Target/AMDGPU/SMInstructions.td

class SM_Real <SM_Pseudo ps>
   Instruction Opcode = !cast<Instruction>(NAME);
 
   // copy relevant pseudo op flags
   let SubtargetPredicate = ps.SubtargetPredicate;
   let AsmMatchConverter  = ps.AsmMatchConverter;
   let UseNamedOperandTable = ps.UseNamedOperandTable;
   let SMRD = ps.SMRD;
 
+  let TSFlags = ps.TSFlags;
+
   bit is_buffer = ps.is_buffer;
 
   // encoding
   bits<7>  sbase;
   bits<7>  sdst;
   bits<32> offset;
   bits<1> imm = !if(ps.has_offset, ps.offset_is_imm, 0);
 }
class SM_Atomic_Pseudo <string opName,
   let mayStore = 1;
   let has_glc = 1;
   let has_dlc = 1;
 
   // Should these be set?
   let ScalarStore = 1;
   let hasSideEffects = 1;
   let maybeAtomic = 1;
+
+  let IsAtomicNoRet = !not(isRet);
+  let IsAtomicRet = isRet;
 }
 
 class SM_Pseudo_Atomic<string opName,
                        RegisterClass baseClass,
                        RegisterClass dataClass,
                        bit isImm,
-                       bit isRet> :
+                       bit isRet,
+                       string opNameWithSuffix = opName # !if(isImm,
+                                 !if(isRet, "_IMM_RTN", "_IMM"),
+                                 !if(isRet, "_SGPR_RTN", "_SGPR"))> :
   SM_Atomic_Pseudo<opName,
                    !if(isRet, (outs dataClass:$sdst), (outs)),
                    !if(isImm,
                        (ins dataClass:$sdata, baseClass:$sbase, smem_offset:$offset, DLC:$dlc),
                        (ins dataClass:$sdata, baseClass:$sbase, SReg_32:$offset, DLC:$dlc)),
                    !if(isRet, " $sdst", " $sdata") # ", $sbase, $offset" # !if(isRet, " glc", "") # "$dlc",
-                   isRet> {
+                   isRet>,
+  AtomicNoRet <opNameWithSuffix, isRet> {
   let offset_is_imm = isImm;
-  let PseudoInstr = opName # !if(isImm,
-                                 !if(isRet, "_IMM_RTN", "_IMM"),
-                                 !if(isRet, "_SGPR_RTN", "_SGPR"));
+  let PseudoInstr = opNameWithSuffix;
 
   let Constraints = !if(isRet, "$sdst = $sdata", "");
   let DisableEncoding = !if(isRet, "$sdata", "");
 }
 
 multiclass SM_Pseudo_Atomics<string opName,
                              RegisterClass baseClass,
                              RegisterClass dataClass> {

 defm S_ATC_PROBE        : SM_Real_Probe_vi <0x26, "S_ATC_PROBE">;
 defm S_ATC_PROBE_BUFFER : SM_Real_Probe_vi <0x27, "S_ATC_PROBE_BUFFER">;
 
 //===----------------------------------------------------------------------===//
 // GFX9
 //===----------------------------------------------------------------------===//
 
 class SMEM_Atomic_Real_vi <bits<8> op, SM_Atomic_Pseudo ps>
-  : SMEM_Real_vi <op, ps> {
+  : SMEM_Real_vi <op, ps>,
+    AtomicNoRet <!subst("_RTN","",NAME), ps.glc> {
 
   bits<7> sdata;
 
   let Constraints = ps.Constraints;
   let DisableEncoding = ps.DisableEncoding;
 
   let glc = ps.glc;
   let Inst{12-6} = !if(glc, sdst{6-0}, sdata{6-0});
multiclass SM_Real_Probe_gfx10<bits<8> op, string ps> {
   def _IMM_gfx10  : SMEM_Real_Store_gfx10 <op, !cast<SM_Pseudo>(ps#_IMM)>;
   def _SGPR_gfx10 : SMEM_Real_Store_gfx10 <op, !cast<SM_Pseudo>(ps#_SGPR)>;
 }
 
 defm S_ATC_PROBE        : SM_Real_Probe_gfx10 <0x26, "S_ATC_PROBE">;
 defm S_ATC_PROBE_BUFFER : SM_Real_Probe_gfx10 <0x27, "S_ATC_PROBE_BUFFER">;
 
 class SMEM_Atomic_Real_gfx10 <bits<8> op, SM_Atomic_Pseudo ps>
-  : SMEM_Real_gfx10 <op, ps> {
+  : SMEM_Real_gfx10 <op, ps>,
+    AtomicNoRet <!subst("_RTN","",NAME), ps.glc> {
 
   bits<7> sdata;
   bit dlc;
 
   let Constraints = ps.Constraints;
   let DisableEncoding = ps.DisableEncoding;
 
   let glc = ps.glc;