[GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT

[foad]

Summary

There's no need to call verifyVectorElementMatch since we already know
that the source and destination types are identical.

[dsanders]

LGTM

llvm/lib/CodeGen/MachineVerifier.cpp

void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
   case TargetOpcode::G_ASSERT_ZEXT: {
     if (!MI->getOperand(2).isImm()) {
       report("G_ASSERT_ZEXT expects an immediate operand #2", MI);
       break;
     }
 
     Register Dst = MI->getOperand(0).getReg();
     Register Src = MI->getOperand(1).getReg();
-    LLT DstTy = MRI->getType(Dst);
     LLT SrcTy = MRI->getType(Src);
-    verifyVectorElementMatch(DstTy, SrcTy, MI);
     int64_t Imm = MI->getOperand(2).getImm();
     if (Imm <= 0) {
       report("G_ASSERT_ZEXT size must be >= 1", MI);
       break;
     }
 
     if (Imm >= SrcTy.getScalarSizeInBits()) {
       report("G_ASSERT_ZEXT size must be less than source bit width", MI);
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
     break;
   }
   case TargetOpcode::G_SEXT_INREG: {
     if (!MI->getOperand(2).isImm()) {
       report("G_SEXT_INREG expects an immediate operand #2", MI);
       break;
     }
 
-    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
     LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
-    verifyVectorElementMatch(DstTy, SrcTy, MI);
-
     int64_t Imm = MI->getOperand(2).getImm();
     if (Imm <= 0)
       report("G_SEXT_INREG size must be >= 1", MI);
     if (Imm >= SrcTy.getScalarSizeInBits())
       report("G_SEXT_INREG size must be less than source bit width", MI);
     break;
   }
   case TargetOpcode::G_SHUFFLE_VECTOR: {

llvm/test/MachineVerifier/test_g_assert_zext.mir

body: |
    %assert_zext_1:_(s64) = G_ASSERT_ZEXT %0, %0
 
    ; CHECK: *** Bad machine code: G_ASSERT_ZEXT expects an immediate operand #2 ***
    ; CHECK: instruction: %assert_zext_2:_(s64) = G_ASSERT_ZEXT
    %assert_zext_2:_(s64) = G_ASSERT_ZEXT %0, i8 8
 
    ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT
-   ; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar ***
-   ; CHECK: instruction: %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT
    %assert_zext_3:_(<2 x s32>) = G_ASSERT_ZEXT %0, 8
 
-   ; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
+   ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT
    %assert_zext_4:_(<2 x s32>) = G_ASSERT_ZEXT %1, 8
 
    ; CHECK: *** Bad machine code: G_ASSERT_ZEXT size must be >= 1 ***
    ; CHECK: instruction: %assert_zext_5:_(s64) = G_ASSERT_ZEXT
    %assert_zext_5:_(s64) = G_ASSERT_ZEXT %0, 0
 
    ; CHECK: *** Bad machine code: G_ASSERT_ZEXT size must be less than source bit width ***

llvm/test/MachineVerifier/test_g_sext_inreg.mir

body: |
    %2(s64) = G_SEXT_INREG %0, %0
 
    ; CHECK: *** Bad machine code: G_SEXT_INREG expects an immediate operand #2 ***
    ; CHECK: instruction: %3:gpr(s64) = G_SEXT_INREG
    %3(s64) = G_SEXT_INREG %0, i8 8
 
    ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
-   ; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar ***
-   ; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
    %4(<2 x s32>) = G_SEXT_INREG %0, 8
 
-   ; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
+   ; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
    ; CHECK: instruction: %5:gpr(<2 x s32>) = G_SEXT_INREG
    %5(<2 x s32>) = G_SEXT_INREG %1, 8
 
    ; CHECK: *** Bad machine code: G_SEXT_INREG size must be >= 1 ***
    ; CHECK: instruction: %6:gpr(s64) = G_SEXT_INREG
    %6(s64) = G_SEXT_INREG %0, 0
 
    ; CHECK: *** Bad machine code: G_SEXT_INREG size must be less than source bit width ***
    ; CHECK: instruction: %7:gpr(s64) = G_SEXT_INREG
    %7(s64) = G_SEXT_INREG %0, 128
 ...