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Differential D96311

[SPARC] Recognize the prefetch instruction
ClosedPublic

Authored by joerg on Feb 8 2021, 7:39 PM.

Details

Reviewers
LemonBoy
jrtc27
dcederman
Commits
rGec428f7b7806: [SPARC] Recognize the prefetch instruction

Diff Detail

Event Timeline

joerg created this revision.Feb 8 2021, 7:39 PM
Herald added subscribers: fedor.sergeev, hiraditya, jyknight. · View Herald TranscriptFeb 8 2021, 7:39 PM
joerg requested review of this revision.Feb 8 2021, 7:39 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 8 2021, 7:39 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
joerg updated this revision to Diff 322272.Feb 8 2021, 7:41 PM
brad added reviewers: LemonBoy, jrtc27.Jun 14 2021, 7:26 PM
LemonBoy accepted this revision.Jun 17 2021, 10:58 PM

LGTM

This revision is now accepted and ready to land.Jun 17 2021, 10:58 PM
brad added a subscriber: brad.Jun 21 2021, 9:13 PM

https://bugs.llvm.org/show_bug.cgi?id=34226

brad added a comment.Sep 23 2021, 5:35 PM

ping.

brad added a comment.Oct 6 2021, 3:59 PM

ping.

brad added a reviewer: dcederman.Oct 19 2021, 7:35 PM
Closed by commit rGec428f7b7806: [SPARC] Recognize the prefetch instruction (authored by joerg, committed by dcederman). · Explain WhyOct 20 2021, 1:59 AM
This revision was automatically updated to reflect the committed changes.
dcederman added a commit: rGec428f7b7806: [SPARC] Recognize the prefetch instruction.

Revision Contents

PathSize
llvm/
lib/
Target/
Sparc/
11 lines
test/
MC/
Sparc/
10 lines

Diff 322272

llvm/lib/Target/Sparc/SparcInstrInfo.td

Show First 20 Lines • Show All 1,617 Lines • ▼ Show 20 Lines
defm TSUBCC : F3_12np<"tsubcc", 0b100001>; defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
let hasSideEffects = 1 in { let hasSideEffects = 1 in {
defm TADDCCTV : F3_12np<"taddcctv", 0b100010>; defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>; defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
} }
} }
// Section A.42 - Prefetch Data
let Predicates = [HasV9] in {
def PREFETCHr : F3_1<3, 0b101101,
(outs), (ins MEMrr:$addr, shift_imm5:$rd),
"prefetch [$addr], $rd", []>;
def PREFETCHi : F3_2<3, 0b101101,
(outs), (ins MEMri:$addr, shift_imm5:$rd),
"prefetch [$addr], $rd", []>;
}
// Section A.43 - Read Privileged Register Instructions // Section A.43 - Read Privileged Register Instructions
let Predicates = [HasV9] in { let Predicates = [HasV9] in {
let rs2 = 0 in let rs2 = 0 in
def RDPR : F3_1<2, 0b101010, def RDPR : F3_1<2, 0b101010,
(outs IntRegs:$rd), (ins PRRegs:$rs1), (outs IntRegs:$rd), (ins PRRegs:$rs1),
"rdpr $rs1, $rd", []>; "rdpr $rs1, $rd", []>;
} }
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

llvm/test/MC/Sparc/sparcv9-instructions.s

Show First 20 Lines • Show All 295 Lines • ▼ Show 20 Lines! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
! V8: error: instruction requires a CPU feature not currently enabled ! V8: error: instruction requires a CPU feature not currently enabled
! V8-NEXT: rd %pc, %o7 ! V8-NEXT: rd %pc, %o7
! V9: rd %pc, %o7 ! encoding: [0x9f,0x41,0x40,0x00] ! V9: rd %pc, %o7 ! encoding: [0x9f,0x41,0x40,0x00]
rd %pc, %o7 rd %pc, %o7
! V9: st %o1, [%o0] ! encoding: [0xd2,0x22,0x00,0x00] ! V9: st %o1, [%o0] ! encoding: [0xd2,0x22,0x00,0x00]
stw %o1, [%o0] stw %o1, [%o0]
! V8: error: instruction requires a CPU feature not currently enabled
! V8-NEXT: prefetch [ %i1 + 0xf80 ], 1
! V9: prefetch [%i1+3968], 1 ! encoding: [0xc3,0x6e,0x6f,0x80]
prefetch [ %i1 + 0xf80 ], 1
! V8: error: instruction requires a CPU feature not currently enabled
! V8-NEXT: prefetch [ %i1 + %i2 ], 1
! V9: prefetch [%i1+%i2], 1 ! encoding: [0xc3,0x6e,0x40,0x1a]
prefetch [ %i1 + %i2 ], 1