[NVPTX][NewPM] Temporarily disable NVPTX passes in new PM pipeline

[aeubanks]

Summary

These passes are causing numerical discrepancies after being added to
the pipeline. Disable while investigating.

[rupprecht]

Verified, thanks!

[tra]

llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp

232–233

If we didn't run NVVMReflectPass before with the new PM and didn't fail, I'm very surprised.
This pass is necessary for using NVIDIA's libdevice bitcode. Without the pass we'd probably see compiler complaining about unresolved reference to __nvvm_reflect function.

NVVMIntrRangePass applies known range values to some CUDA functions which may allow compiler to optimize a bit better. Can be skipped w/o too much impact.

I don't know anything about createModuleToFunctionPassAdaptor.

[aeubanks]

llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp

232–233

https://reviews.llvm.org/D96291 to re-enable NVVMReflectPass, looks like only NVVMIntrRangePass is the issue (which makes sense).
createModuleToFunctionPassAdaptor() is just pass manager infra stuff (changes a function pass to a module pass).

llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp

PB.registerPipelineParsingCallback(
         }
         if (PassName == "nvvm-intr-range") {
           PM.addPass(NVVMIntrRangePass());
           return true;
         }
         return false;
       });
 
-  PB.registerPipelineStartEPCallback(
-      [this, DebugPassManager](ModulePassManager &PM,
-                               PassBuilder::OptimizationLevel Level) {
-        FunctionPassManager FPM(DebugPassManager);
-        FPM.addPass(NVVMReflectPass(Subtarget.getSmVersion()));
-        FPM.addPass(NVVMIntrRangePass(Subtarget.getSmVersion()));
-        PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
-      });
+  // FIXME: these passes are causing numerical discrepancies, investigate and
+  // re-enable.
+
+  // PB.registerPipelineStartEPCallback(
+  //     [this, DebugPassManager](ModulePassManager &PM,
+  //                              PassBuilder::OptimizationLevel Level) {
+  //       FunctionPassManager FPM(DebugPassManager);
+  //       FPM.addPass(NVVMReflectPass(Subtarget.getSmVersion()));
+  //       FPM.addPass(NVVMIntrRangePass(Subtarget.getSmVersion()));
+  //       PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
+  //     });
 }
 
 TargetTransformInfo
 NVPTXTargetMachine::getTargetTransformInfo(const Function &F) {
   return TargetTransformInfo(NVPTXTTIImpl(this, F));
 }
 
 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {

llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll

 ; Libdevice in recent CUDA versions relies on __CUDA_ARCH reflecting GPU type.
 ; Verify that __nvvm_reflect() is replaced with an appropriate value.
 ;
-; RUN: opt %s -S -nvvm-reflect -O2 -mtriple=nvptx64 \
+; FIXME: fix pass and re-enable under new PM
+; RUN: opt %s -S -nvvm-reflect -O2 -enable-new-pm=0 -mtriple=nvptx64 \
 ; RUN:   | FileCheck %s --check-prefixes=COMMON,SM20
-; RUN: opt %s -S -nvvm-reflect -O2 -mtriple=nvptx64 -mcpu=sm_35 \
+; RUN: opt %s -S -nvvm-reflect -O2 -enable-new-pm=0 -mtriple=nvptx64 -mcpu=sm_35 \
 ; RUN:   | FileCheck %s --check-prefixes=COMMON,SM35
 
 @"$str" = private addrspace(1) constant [12 x i8] c"__CUDA_ARCH\00"
 
 declare i32 @__nvvm_reflect(i8*)
 
 ; COMMON-LABEL: @foo
 define i32 @foo(float %a, float %b) {
 ; COMMON-NOT: call i32 @__nvvm_reflect
   %reflect = call i32 @__nvvm_reflect(i8* addrspacecast (i8 addrspace(1)* getelementptr inbounds ([12 x i8], [12 x i8] addrspace(1)* @"$str", i32 0, i32 0) to i8*))
 ; SM20: ret i32 200  
 ; SM35: ret i32 350  
   ret i32 %reflect
 }