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Differential D96291

[NVPTX][NewPM] Re-enable NVVMReflectPass
ClosedPublic

Authored by aeubanks on Feb 8 2021, 1:53 PM.

Details

Reviewers
tra
Commits
rGe84a4650eb7e: [NVPTX][NewPM] Re-enable NVVMReflectPass
Summary

Disabled alongside NVVMIntrRangePass in https://reviews.llvm.org/D96166,
but turns out NVVMIntrRangePass was the issue.

Diff Detail

Event Timeline

aeubanks created this revision.Feb 8 2021, 1:53 PM
Herald added subscribers: hiraditya, jholewinski. · View Herald TranscriptFeb 8 2021, 1:53 PM
aeubanks requested review of this revision.Feb 8 2021, 1:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 8 2021, 1:53 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
aeubanks mentioned this in D96166: [NVPTX][NewPM] Temporarily disable NVPTX passes in new PM pipeline.Feb 8 2021, 1:54 PM
tra accepted this revision.Feb 8 2021, 1:55 PM
This revision is now accepted and ready to land.Feb 8 2021, 1:55 PM
This revision was landed with ongoing or failed builds.Feb 8 2021, 1:58 PM
Closed by commit rGe84a4650eb7e: [NVPTX][NewPM] Re-enable NVVMReflectPass (authored by aeubanks). · Explain Why
This revision was automatically updated to reflect the committed changes.
aeubanks added a commit: rGe84a4650eb7e: [NVPTX][NewPM] Re-enable NVVMReflectPass.
Harbormaster completed remote builds in B88353: Diff 322211.Feb 8 2021, 2:36 PM

Revision Contents

PathSize
llvm/
lib/
Target/
NVPTX/
21 lines
test/
CodeGen/
NVPTX/
5 lines

Diff 322212

llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp

Show First 20 Lines • Show All 216 Lines • ▼ Show 20 Lines PB.registerPipelineParsingCallback(
} }
if (PassName == "nvvm-intr-range") { if (PassName == "nvvm-intr-range") {
PM.addPass(NVVMIntrRangePass()); PM.addPass(NVVMIntrRangePass());
return true; return true;
} }
return false; return false;
}); });
// FIXME: these passes are causing numerical discrepancies, investigate and PB.registerPipelineStartEPCallback(
// re-enable. [this, DebugPassManager](ModulePassManager &PM,
PassBuilder::OptimizationLevel Level) {
// PB.registerPipelineStartEPCallback( FunctionPassManager FPM(DebugPassManager);
// [this, DebugPassManager](ModulePassManager &PM, FPM.addPass(NVVMReflectPass(Subtarget.getSmVersion()));
// PassBuilder::OptimizationLevel Level) { // FIXME: NVVMIntrRangePass is causing numerical discrepancies,
// FunctionPassManager FPM(DebugPassManager); // investigate and re-enable.
// FPM.addPass(NVVMReflectPass(Subtarget.getSmVersion()));
// FPM.addPass(NVVMIntrRangePass(Subtarget.getSmVersion())); // FPM.addPass(NVVMIntrRangePass(Subtarget.getSmVersion()));
// PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM))); PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
// }); });
} }
TargetTransformInfo TargetTransformInfo
NVPTXTargetMachine::getTargetTransformInfo(const Function &F) { NVPTXTargetMachine::getTargetTransformInfo(const Function &F) {
return TargetTransformInfo(NVPTXTTIImpl(this, F)); return TargetTransformInfo(NVPTXTTIImpl(this, F));
} }
void NVPTXPassConfig::addEarlyCSEOrGVNPass() { void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
▲ Show 20 Lines • Show All 187 Lines • Show Last 20 Lines

llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll

; Libdevice in recent CUDA versions relies on __CUDA_ARCH reflecting GPU type. ; Libdevice in recent CUDA versions relies on __CUDA_ARCH reflecting GPU type.
; Verify that __nvvm_reflect() is replaced with an appropriate value. ; Verify that __nvvm_reflect() is replaced with an appropriate value.
; ;
; FIXME: fix pass and re-enable under new PM ; RUN: opt %s -S -nvvm-reflect -O2 -mtriple=nvptx64 \
; RUN: opt %s -S -nvvm-reflect -O2 -enable-new-pm=0 -mtriple=nvptx64 \
; RUN: | FileCheck %s --check-prefixes=COMMON,SM20 ; RUN: | FileCheck %s --check-prefixes=COMMON,SM20
; RUN: opt %s -S -nvvm-reflect -O2 -enable-new-pm=0 -mtriple=nvptx64 -mcpu=sm_35 \ ; RUN: opt %s -S -nvvm-reflect -O2 -mtriple=nvptx64 -mcpu=sm_35 \
; RUN: | FileCheck %s --check-prefixes=COMMON,SM35 ; RUN: | FileCheck %s --check-prefixes=COMMON,SM35
@"$str" = private addrspace(1) constant [12 x i8] c"__CUDA_ARCH\00" @"$str" = private addrspace(1) constant [12 x i8] c"__CUDA_ARCH\00"
declare i32 @__nvvm_reflect(i8*) declare i32 @__nvvm_reflect(i8*)
; COMMON-LABEL: @foo ; COMMON-LABEL: @foo
define i32 @foo(float %a, float %b) { define i32 @foo(float %a, float %b) {
; COMMON-NOT: call i32 @__nvvm_reflect ; COMMON-NOT: call i32 @__nvvm_reflect
%reflect = call i32 @__nvvm_reflect(i8* addrspacecast (i8 addrspace(1)* getelementptr inbounds ([12 x i8], [12 x i8] addrspace(1)* @"$str", i32 0, i32 0) to i8*)) %reflect = call i32 @__nvvm_reflect(i8* addrspacecast (i8 addrspace(1)* getelementptr inbounds ([12 x i8], [12 x i8] addrspace(1)* @"$str", i32 0, i32 0) to i8*))
; SM20: ret i32 200 ; SM20: ret i32 200
; SM35: ret i32 350 ; SM35: ret i32 350
ret i32 %reflect ret i32 %reflect
} }