[AMDGPU][MC][GFX10] Improved errors reporting for invalid MIMG NSA operands

[foad]

LGTM.

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ||
     return ResTy;
 
   SMLoc RBraceLoc;
   SMLoc LBraceLoc = getLoc();
   if (Mode == OperandMode_NSA && trySkipToken(AsmToken::LBrac)) {
     unsigned Prefix = Operands.size();
 
     for (;;) {
+      auto Loc = getLoc();
       ResTy = parseReg(Operands);
+      if (ResTy == MatchOperand_NoMatch)
+        Error(Loc, "expected a register");
       if (ResTy != MatchOperand_Success)
-        return ResTy;
+        return MatchOperand_ParseFail;
 
       RBraceLoc = getLoc();
       if (trySkipToken(AsmToken::RBrac))
         break;
 
-      if (!trySkipToken(AsmToken::Comma))
+      if (!skipToken(AsmToken::Comma,
+                     "expected a comma or a closing square bracket")) {
         return MatchOperand_ParseFail;
       }
+    }
 
     if (Operands.size() - Prefix > 1) {
       Operands.insert(Operands.begin() + Prefix,
                       AMDGPUOperand::CreateToken(this, "[", LBraceLoc));
       Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc));
     }
 
     return MatchOperand_Success;

llvm/test/MC/AMDGPU/gfx10_err_pos.s

 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0
 // CHECK-NEXT:{{^}}                       ^
 
 s_mov_b64 s[10:11], [s0,s1
 // CHECK: error: expected a comma or a closing square bracket
 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s1
 // CHECK-NEXT:{{^}}                          ^
 
+image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D
+// CHECK: error: expected a comma or a closing square bracket
+// CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D
+// CHECK-NEXT:{{^}}                                       ^
+
+image_load_mip v[253:255], [v255, v254
+// CHECK: error: expected a comma or a closing square bracket
+// CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254
+// CHECK-NEXT:{{^}}                                      ^
+
 //==============================================================================
 // expected a counter name
 
 s_waitcnt vmcnt(0) & expcnt(0) & 1
 // CHECK: error: expected a counter name
 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & 1
 // CHECK-NEXT:{{^}}                                 ^
 

 // expected a left square bracket
 
 v_pk_add_u16 v1, v2, v3 op_sel:
 // CHECK: error: expected a left square bracket
 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:
 // CHECK-NEXT:{{^}}                               ^
 
 //==============================================================================
+// expected a register
+
+image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm
+// CHECK: error: expected a register
+// CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm
+// CHECK-NEXT:{{^}}                            ^
+
+image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm
+// CHECK: error: expected a register
+// CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm
+// CHECK-NEXT:{{^}}                            ^
+
+//==============================================================================
 // expected a register or a list of registers
 
 s_mov_b32 s1, [s0, 1
 // CHECK: error: expected a register or a list of registers
 // CHECK-NEXT:{{^}}s_mov_b32 s1, [s0, 1
 // CHECK-NEXT:{{^}}                   ^
 
 //==============================================================================