[NFC][AMDGPU] Correct name of DWARF CFA extensions

[t-tye]

Summary

Add LLVM to the DW_CFA_LLVM_def_aspace_cfa and
DW_CFA_LLVM_def_aspace_cfa_sf DWARF extensions.

[scott.linder]

LGTM, thank you!

llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst

 architectures.
 
 DWARF address space identifiers are used by:
 
 * The DWARF expression operations: ``DW_OP_LLVM_aspace_bregx``,
   ``DW_OP_LLVM_form_aspace_address``, ``DW_OP_LLVM_implicit_aspace_pointer``,
   and ``DW_OP_xderef*``.
 
-* The CFI instructions: ``DW_CFA_def_aspace_cfa`` and
-  ``DW_CFA_def_aspace_cfa_sf``.
+* The CFI instructions: ``DW_CFA_LLVM_def_aspace_cfa`` and
+  ``DW_CFA_LLVM_def_aspace_cfa_sf``.
 
 .. note::
 
   With the definition of DWARF address classes and DWARF address spaces in these
   extensions, DWARF Version 5 table 2.7 needs to be updated. It seems it is an
   example of DWARF address spaces and not DWARF address classes.
 
 .. note::
2.  ``DW_CFA_def_cfa_sf``
     displacement B. AS is set to the target architecture default address space
     identifier. The required action is to define the current CFA rule to be the
     result of evaluating the DWARF operation expression ``DW_OP_constu AS;
     DW_OP_aspace_bregx R, B*data_alignment_factor`` as a location description.
 
     *The action is the same as* ``DW_CFA_def_cfa``\ *, except that the second
     operand is signed and factored.*
 
-3.  ``DW_CFA_def_aspace_cfa`` *New*
+3.  ``DW_CFA_LLVM_def_aspace_cfa`` *New*
 
-    The ``DW_CFA_def_aspace_cfa`` instruction takes three unsigned LEB128
+    The ``DW_CFA_LLVM_def_aspace_cfa`` instruction takes three unsigned LEB128
     operands representing a register number R, a (non-factored) byte
     displacement B, and a target architecture specific address space identifier
     AS. The required action is to define the current CFA rule to be the result
     of evaluating the DWARF operation expression ``DW_OP_constu AS;
     DW_OP_aspace_bregx R, B`` as a location description.
 
     If AS is not one of the values defined by the target architecture specific
     ``DW_ASPACE_*`` values then the DWARF expression is ill-formed.
 
-4.  ``DW_CFA_def_aspace_cfa_sf`` *New*
+4.  ``DW_CFA_LLVM_def_aspace_cfa_sf`` *New*
 
     The ``DW_CFA_def_cfa_sf`` instruction takes three operands: an unsigned
     LEB128 value representing a register number R, a signed LEB128 factored byte
     displacement B, and an unsigned LEB128 value representing a target
     architecture specific address space identifier AS. The required action is to
     define the current CFA rule to be the result of evaluating the DWARF
     operation expression ``DW_OP_constu AS; DW_OP_aspace_bregx R,
     B*data_alignment_factor`` as a location description.
.. note::
   This augments DWARF Version 5 section 7.24 and Table 7.29.
 
 The following table gives the encoding of the additional call frame information
 instructions.
 
 .. table:: Call frame instruction encodings
    :name: amdgpu-dwarf-call-frame-instruction-encodings-table
 
-   ======================== ====== ====== ================ ================ ================
-   Instruction              High 2 Low 6  Operand 1        Operand 2        Operand 3
+   ============================= ====== ====== ================ ================ =====================
+   Instruction                   High 2 Low 6  Operand 1        Operand 2        Operand 3
                                  Bits   Bits
-   ======================== ====== ====== ================ ================ ================
-   DW_CFA_def_aspace_cfa    0      0x30   ULEB128 register ULEB128 offset   ULEB128 address space
-   DW_CFA_def_aspace_cfa_sf 0      0x31   ULEB128 register SLEB128 offset   ULEB128 address space
-   ======================== ====== ====== ================ ================ ================
+   ============================= ====== ====== ================ ================ =====================
+   DW_CFA_LLVM_def_aspace_cfa    0      0x30   ULEB128 register ULEB128 offset   ULEB128 address space
+   DW_CFA_LLVM_def_aspace_cfa_sf 0      0x31   ULEB128 register SLEB128 offset   ULEB128 address space
+   ============================= ====== ====== ================ ================ =====================
 
 Attributes by Tag Value (Informative)
 -------------------------------------
 
 .. note::
 
   This augments DWARF Version 5 Appendix A and Table A.1.