[WebAssembly] Prototype i8x16 to i32x4 widening instructions

[tlively]

Summary

As proposed in https://github.com/WebAssembly/simd/pull/395 and matching the
opcodes used in V8:
https://chromium-review.googlesource.com/c/v8/v8/+/2617385/4/src/wasm/wasm-opcodes.h

[aheejin]

This does not yet have i64x2 version of the instructions in https://github.com/WebAssembly/simd/pull/395 yet, right?

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

1279

I think this is the first time we use timm in this file... Haven't we used LaneIdxN for these? The same for WIDEN_I8x16_TO_I32x4_U.

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

1279

Yes, this is the first use of timm. I needed to use timm instead of imm (or a LaneIdxN, which is just a restricted imm) because immarg arguments are apparently lowered to TargetConstant nodes rather than Constant nodes. This is also the first time I've used an immarg arument in one of the intrinsics, but I should definitely use them for many other intrinsics as well, and probably change LaneIdxN to be based on timm rather than imm. Since these are just prototype instructions, I am ok with them working differently from other instructions for now.

[tlively]

In D95557#2527731, @aheejin wrote:

This does not yet have i64x2 version of the instructions in https://github.com/WebAssembly/simd/pull/395 yet, right?

Yes, that's intentional. These are the only versions implemented in V8 as well.

clang/include/clang/Basic/BuiltinsWebAssembly.def

 TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, "V8UsV4UiV4Ui", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_widen_low_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_widen_high_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_widen_low_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_widen_high_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
 
+TARGET_BUILTIN(__builtin_wasm_widen_s_i8x16_i32x4, "V4iV16ScIi", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_widen_u_i8x16_i32x4, "V4UiV16UcIi", "nc", "simd128")
+
 TARGET_BUILTIN(__builtin_wasm_convert_low_s_i32x4_f64x2, "V2dV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_convert_low_u_i32x4_f64x2, "V2dV4Ui", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_zero_s_f64x2_i32x4, "V4iV2d", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_zero_u_f64x2_i32x4, "V4UiV2d", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_demote_zero_f64x2_f32x4, "V4fV2d", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_promote_low_f32x4_f64x2, "V2dV4f", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_load32_zero, "V4ii*", "n", "simd128")

clang/lib/CodeGen/CGBuiltin.cpp

case WebAssembly::BI__builtin_wasm_widen_low_u_i32x4_i64x2:
       break;
     case WebAssembly::BI__builtin_wasm_widen_high_u_i32x4_i64x2:
       IntNo = Intrinsic::wasm_widen_high_unsigned;
       break;
     }
     Function *Callee = CGM.getIntrinsic(IntNo);
     return Builder.CreateCall(Callee, Vec);
   }
+  case WebAssembly::BI__builtin_wasm_widen_s_i8x16_i32x4:
+  case WebAssembly::BI__builtin_wasm_widen_u_i8x16_i32x4: {
+    Value *Vec = EmitScalarExpr(E->getArg(0));
+    llvm::APSInt SubVecConst =
+        *E->getArg(1)->getIntegerConstantExpr(getContext());
+    Value *SubVec = llvm::ConstantInt::get(getLLVMContext(), SubVecConst);
+    unsigned IntNo;
+    switch (BuiltinID) {
+    case WebAssembly::BI__builtin_wasm_widen_s_i8x16_i32x4:
+      IntNo = Intrinsic::wasm_widen_signed;
+      break;
+    case WebAssembly::BI__builtin_wasm_widen_u_i8x16_i32x4:
+      IntNo = Intrinsic::wasm_widen_unsigned;
+      break;
+    }
+    Function *Callee = CGM.getIntrinsic(IntNo);
+    return Builder.CreateCall(Callee, {Vec, SubVec});
+  }
   case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2:
   case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2: {
     Value *Vec = EmitScalarExpr(E->getArg(0));
     unsigned IntNo;
     switch (BuiltinID) {
     case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2:
       IntNo = Intrinsic::wasm_convert_low_signed;
       break;

clang/test/CodeGen/builtins-wasm.c

 }
 
 u64x2 widen_high_u_i32x4_i64x2(u32x4 x) {
   return __builtin_wasm_widen_high_u_i32x4_i64x2(x);
   // WEBASSEMBLY: call <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32> %x)
   // WEBASSEMBLY: ret
 }
 
+i32x4 widen_s_i8x16_i32x4(i8x16 x) {
+  return __builtin_wasm_widen_s_i8x16_i32x4(x, 3);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.widen.signed(<16 x i8> %x, i32 3)
+  // WEBASSEMBLY: ret
+}
+
+u32x4 widen_u_i8x16_i32x4(u8x16 x) {
+  return __builtin_wasm_widen_u_i8x16_i32x4(x, 3);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8> %x, i32 3)
+  // WEBASSEMBLY: ret
+}
+
 f64x2 convert_low_s_i32x4_f64x2(i32x4 x) {
   return __builtin_wasm_convert_low_s_i32x4_f64x2(x);
   // WEBASSEMBLY: call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %x)
   // WEBASSEMBLY: ret
 }
 
 f64x2 convert_low_u_i32x4_f64x2(u32x4 x) {
   return __builtin_wasm_convert_low_u_i32x4_f64x2(x);

llvm/include/llvm/IR/IntrinsicsWebAssembly.td

Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty],
             [IntrNoMem, IntrSpeculatable]>;
 def int_wasm_demote_zero :
   Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty],
             [IntrNoMem, IntrSpeculatable]>;
 def int_wasm_promote_low :
   Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty],
             [IntrNoMem, IntrSpeculatable]>;
 
+// TODO: Remove these if possible if they are merged to the spec.
+def int_wasm_widen_signed :
+  Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_i32_ty],
+            [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
+def int_wasm_widen_unsigned :
+  Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_i32_ty],
+            [IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;
+
 //===----------------------------------------------------------------------===//
 // Thread-local storage intrinsics
 //===----------------------------------------------------------------------===//
 
 def int_wasm_tls_size :
   Intrinsic<[llvm_anyint_ty],
             [],
             [IntrNoMem, IntrSpeculatable]>;

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_signed,
                       "extadd_pairwise_i8x16_s", 0xc2>;
 defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_unsigned,
                       "extadd_pairwise_i8x16_u", 0xc3>;
 defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_signed,
                       "extadd_pairwise_i16x8_s", 0xa5>;
 defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_unsigned,
                       "extadd_pairwise_i16x8_u", 0xa6>;
 
-
 // Prototype f64x2 conversions
 defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_signed,
                       "convert_low_i32x4_s", 0x53>;
 defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_unsigned,
                       "convert_low_i32x4_u", 0x54>;
 defm "" : SIMDConvert<I32x4, F64x2, int_wasm_trunc_saturate_zero_signed,
                       "trunc_sat_zero_f64x2_s", 0x55>;
 defm "" : SIMDConvert<I32x4, F64x2, int_wasm_trunc_saturate_zero_unsigned,
                       "trunc_sat_zero_f64x2_u", 0x56>;
 defm "" : SIMDConvert<F32x4, F64x2, int_wasm_demote_zero,
                       "demote_zero_f64x2", 0x57>;
 defm "" : SIMDConvert<F64x2, F32x4, int_wasm_promote_low,
                       "promote_low_f32x4", 0x69>;
 
+// Prototype i8x16 to i32x4 widening
+defm WIDEN_I8x16_TO_I32x4_S :
+  SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
+         (outs), (ins vec_i8imm_op:$idx),
+         [(set (I32x4.vt V128:$dst),
+            (I32x4.vt (int_wasm_widen_signed
+              (I8x16.vt V128:$vec), (i32 timm:$idx))))],
+         "i32x4.widen_i8x16_s\t$dst, $vec, $idx",
+         "i32x4.widen_i8x16_s\t$idx", 0x67>;
+defm WIDEN_I8x16_TO_I32x4_U :
+  SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
+         (outs), (ins vec_i8imm_op:$idx),
+         [(set (I32x4.vt V128:$dst),
+            (I32x4.vt (int_wasm_widen_unsigned
+              (I8x16.vt V128:$vec), (i32 timm:$idx))))],
+         "i32x4.widen_i8x16_u\t$dst, $vec, $idx",
+         "i32x4.widen_i8x16_u\t$idx", 0x68>;
+
+
 //===----------------------------------------------------------------------===//
 // Quasi-Fused Multiply- Add and Subtract (QFMA/QFMS)
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDQFM<Vec vec, bits<32> simdopA, bits<32> simdopS> {
   defm QFMA_#vec :
     SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c),
            (outs), (ins),

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

 ; SIMD128-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double>)
 define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) {
   %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double> %a)
   ret <4 x i32> %v
 }
 
+
+; CHECK-LABEL: widen_signed_v4i32:
+; SIMD128-NEXT: .functype widen_signed_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.widen_i8x16_s $push[[R:[0-9]+]]=, $0, 1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.widen.signed(<16 x i8>, i32 immarg)
+define <4 x i32> @widen_signed_v4i32(<16 x i8> %x) {
+  %v = call <4 x i32> @llvm.wasm.widen.signed(<16 x i8> %x, i32 1)
+  ret <4 x i32> %v
+}
+
+; CHECK-LABEL: widen_unsigned_v4i32:
+; SIMD128-NEXT: .functype widen_unsigned_v4i32 (v128) -> (v128){{$}}
+; SIMD128-NEXT: i32x4.widen_i8x16_u $push[[R:[0-9]+]]=, $0, 1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8>, i32 immarg)
+define <4 x i32> @widen_unsigned_v4i32(<16 x i8> %x) {
+  %v = call <4 x i32> @llvm.wasm.widen.unsigned(<16 x i8> %x, i32 1)
+  ret <4 x i32> %v
+}
+
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: eq_v2i64:
 ; SIMD128-NEXT: .functype eq_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.eq(<2 x i64>, <2 x i64>)

llvm/test/MC/WebAssembly/simd-encodings.s

main:
     i32x4.trunc_sat_zero_f64x2_u
 
     # CHECK: f32x4.demote_zero_f64x2 # encoding: [0xfd,0x57]
     f32x4.demote_zero_f64x2
 
     # CHECK: f64x2.promote_low_f32x4 # encoding: [0xfd,0x69]
     f64x2.promote_low_f32x4
 
+    # CHECK: i32x4.widen_i8x16_s 3 # encoding: [0xfd,0x67,0x03]
+    i32x4.widen_i8x16_s 3
+
+    # CHECK: i32x4.widen_i8x16_u 3 # encoding: [0xfd,0x68,0x03]
+    i32x4.widen_i8x16_u 3
+
     end_function