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Differential D95377

[AMDGPU] Avoid mentioning GFX10 unnecessarily in docs
AbandonedPublic

Authored by foad on Jan 25 2021, 9:52 AM.

Details

Reviewers
rampitec
t-tye
Summary

In the text refer to e.g. "GFX8+" instead of "GFX8-GFX10". Change a
couple of internal table names to avoid mentioning GFX numbers
altogether where it didn't disambiguate anything.

The intent is to reduce the number of mechanical changes required every
time the document is updated for a new architecture.

Diff Detail

Event Timeline

foad created this revision.Jan 25 2021, 9:52 AM
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t-tye requested changes to this revision.Jan 25 2021, 5:14 PM

A concern I have is that we do not know if future hardware will match what previous hardware is doing. By explicitly stating the range of targets it is clear that the document is saying nothing about future hardware. For example, do you know that future hardware will have the same layout for compute_pgm_rsrc3 register? Or the memory model will be the same? If new hardware comes along I think it is better to simply search for the gfx10 and decide what to do. That seems less error prone than searching for '+'.

llvm/docs/AMDGPUUsage.rst
4105

The title says GFX10 so the label should also have gfx10 in the name.

This revision now requires changes to proceed.Jan 25 2021, 5:14 PM
foad abandoned this revision.Jan 25 2021, 11:17 PM

Revision Contents

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docs/
182 lines

Diff 319042

llvm/docs/AMDGPUUsage.rst

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 617 Lines • ▼ Show 20 Lines**Generic**
access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register
setup (see :ref:`amdgpu-amdhsa-kernel-prolog-m0`). setup (see :ref:`amdgpu-amdhsa-kernel-prolog-m0`).
To convert between a private or group address space address (termed a segment To convert between a private or group address space address (termed a segment
address) and a flat address the base address of the corresponding aperture address) and a flat address the base address of the corresponding aperture
can be used. For GFX7-GFX8 these are available in the can be used. For GFX7-GFX8 these are available in the
:ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with :ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with
Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For
GFX9-GFX10 the aperture base addresses are directly available as inline GFX9+ the aperture base addresses are directly available as inline
constant registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. constant registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``.
In 64-bit address mode the aperture sizes are 2^32 bytes and the base is In 64-bit address mode the aperture sizes are 2^32 bytes and the base is
aligned to 2^32 which makes it easier to convert from flat to segment or aligned to 2^32 which makes it easier to convert from flat to segment or
segment to flat. segment to flat.
A global address space address has the same value when used as a flat address A global address space address has the same value when used as a flat address
so no conversion is needed. so no conversion is needed.
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines**Private**
There are different ways that the wavefront scratch base address is There are different ways that the wavefront scratch base address is
determined by a wavefront (see determined by a wavefront (see
:ref:`amdgpu-amdhsa-initial-kernel-execution-state`). :ref:`amdgpu-amdhsa-initial-kernel-execution-state`).
Scratch memory can be accessed in an interleaved manner using buffer Scratch memory can be accessed in an interleaved manner using buffer
instructions with the scratch buffer descriptor and per wavefront scratch instructions with the scratch buffer descriptor and per wavefront scratch
offset, by the scratch instructions, or by flat instructions. Multi-dword offset, by the scratch instructions, or by flat instructions. Multi-dword
access is not supported except by flat and scratch instructions in access is not supported except by flat and scratch instructions in
GFX9-GFX10. GFX9+.
**Constant 32-bit** **Constant 32-bit**
*TODO* *TODO*
**Buffer Fat Pointer** **Buffer Fat Pointer**
The buffer fat pointer is an experimental address space that is currently The buffer fat pointer is an experimental address space that is currently
unsupported in the backend. It exposes a non-integral pointer that is in unsupported in the backend. It exposes a non-integral pointer that is in
the future intended to support the modelling of 128-bit buffer descriptors the future intended to support the modelling of 128-bit buffer descriptors
▲ Show 20 Lines • Show All 1,670 Lines • ▼ Show 20 Lines
``address_size`` (ubyte) ``address_size`` (ubyte)
Matches the address size for the ``Global`` address space defined in Matches the address size for the ``Global`` address space defined in
:ref:`amdgpu-dwarf-address-space-identifier`. :ref:`amdgpu-dwarf-address-space-identifier`.
``segment_selector_size`` (ubyte) ``segment_selector_size`` (ubyte)
AMDGPU does not use a segment selector so this is 0. AMDGPU does not use a segment selector so this is 0.
``minimum_instruction_length`` (ubyte) ``minimum_instruction_length`` (ubyte)
For GFX9-GFX10 this is 4. For GFX9+ this is 4.
``maximum_operations_per_instruction`` (ubyte) ``maximum_operations_per_instruction`` (ubyte)
For GFX9-GFX10 this is 1. For GFX9+ this is 1.
Source text for online-compiled programs (for example, those compiled by the Source text for online-compiled programs (for example, those compiled by the
OpenCL language runtime) may be embedded into the DWARF Version 5 line table. OpenCL language runtime) may be embedded into the DWARF Version 5 line table.
See DWARF Version 5 section 6.2.4.1 which is updated by *DWARF Extensions For See DWARF Version 5 section 6.2.4.1 which is updated by *DWARF Extensions For
Heterogeneous Debugging* section :ref:`DW_LNCT_LLVM_source Heterogeneous Debugging* section :ref:`DW_LNCT_LLVM_source
<amdgpu-dwarf-line-number-information-dw-lnct-llvm-source>`. <amdgpu-dwarf-line-number-information-dw-lnct-llvm-source>`.
The Clang option used to control source embedding in AMDGPU is defined in The Clang option used to control source embedding in AMDGPU is defined in
▲ Show 20 Lines • Show All 461 Lines • ▼ Show 20 Lines "KernargSegmentAlign" integer Required The maximum byte
arguments in the arguments in the
kernarg segment. Must kernarg segment. Must
be a power of 2. be a power of 2.
"WavefrontSize" integer Required Wavefront size. Must "WavefrontSize" integer Required Wavefront size. Must
be a power of 2. be a power of 2.
"NumSGPRs" integer Required Number of scalar "NumSGPRs" integer Required Number of scalar
registers used by a registers used by a
wavefront for wavefront for
GFX6-GFX10. This GFX6+. This
includes the special includes the special
SGPRs for VCC, Flat SGPRs for VCC, Flat
Scratch (GFX7-GFX10) Scratch (GFX7+)
and XNACK (for and XNACK (for
GFX8-GFX10). It does GFX8+). It does
not include the 16 not include the 16
SGPR added if a trap SGPR added if a trap
handler is handler is
enabled. It is not enabled. It is not
rounded up to the rounded up to the
allocation allocation
granularity. granularity.
"NumVGPRs" integer Required Number of vector "NumVGPRs" integer Required Number of vector
registers used by registers used by
each work-item for each work-item for
GFX6-GFX10 GFX6+
"MaxFlatWorkGroupSize" integer Required Maximum flat "MaxFlatWorkGroupSize" integer Required Maximum flat
work-group size work-group size
supported by the supported by the
kernel in work-items. kernel in work-items.
Must be >=1 and Must be >=1 and
consistent with consistent with
ReqdWorkGroupSize if ReqdWorkGroupSize if
not 0, 0, 0. not 0, 0, 0.
▲ Show 20 Lines • Show All 565 Lines • ▼ Show 20 Lines
There are different ways that the wavefront scratch base address is determined There are different ways that the wavefront scratch base address is determined
by a wavefront (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). This by a wavefront (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). This
memory can be accessed in an interleaved manner using buffer instruction with memory can be accessed in an interleaved manner using buffer instruction with
the scratch buffer descriptor and per wavefront scratch offset, by the scratch the scratch buffer descriptor and per wavefront scratch offset, by the scratch
instructions, or by flat instructions. If each lane of a wavefront accesses the instructions, or by flat instructions. If each lane of a wavefront accesses the
same private address, the interleaving results in adjacent dwords being accessed same private address, the interleaving results in adjacent dwords being accessed
and hence requires fewer cache lines to be fetched. Multi-dword access is not and hence requires fewer cache lines to be fetched. Multi-dword access is not
supported except by flat and scratch instructions in GFX9-GFX10. supported except by flat and scratch instructions in GFX9+.
The generic address space uses the hardware flat address support available in The generic address space uses the hardware flat address support available in
GFX7-GFX10. This uses two fixed ranges of virtual addresses (the private and GFX7+. This uses two fixed ranges of virtual addresses (the private and
local apertures), that are outside the range of addressible global memory, to local apertures), that are outside the range of addressible global memory, to
map from a flat address to a private or local address. map from a flat address to a private or local address.
FLAT instructions can take a flat address and access global, private (scratch) FLAT instructions can take a flat address and access global, private (scratch)
and group (LDS) memory depending in if the address is within one of the and group (LDS) memory depending in if the address is within one of the
aperture ranges. Flat access to scratch requires hardware aperture setup and aperture ranges. Flat access to scratch requires hardware aperture setup and
setup in the kernel prologue (see setup in the kernel prologue (see
:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`). Flat access to LDS requires :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`). Flat access to LDS requires
hardware aperture setup and M0 (GFX7-GFX8) register setup (see hardware aperture setup and M0 (GFX7-GFX8) register setup (see
:ref:`amdgpu-amdhsa-kernel-prolog-m0`). :ref:`amdgpu-amdhsa-kernel-prolog-m0`).
To convert between a segment address and a flat address the base address of the To convert between a segment address and a flat address the base address of the
apertures address can be used. For GFX7-GFX8 these are available in the apertures address can be used. For GFX7-GFX8 these are available in the
:ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with :ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with
Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For
GFX9-GFX10 the aperture base addresses are directly available as inline constant GFX9+ the aperture base addresses are directly available as inline constant
registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. In 64 bit registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. In 64 bit
address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32 address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32
which makes it easier to convert from flat to segment or segment to flat. which makes it easier to convert from flat to segment or segment to flat.
Image and Samplers Image and Samplers
~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~
Image and sample handles created by an HSA compatible runtime (see Image and sample handles created by an HSA compatible runtime (see
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines 383:352 4 bytes COMPUTE_PGM_RSRC3 GFX6-9
Reserved, must be 0. Reserved, must be 0.
GFX10 GFX10
Compute Shader (CS) Compute Shader (CS)
program settings used by program settings used by
CP to set up CP to set up
``COMPUTE_PGM_RSRC3`` ``COMPUTE_PGM_RSRC3``
configuration configuration
register. See register. See
:ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-table`.
415:384 4 bytes COMPUTE_PGM_RSRC1 Compute Shader (CS) 415:384 4 bytes COMPUTE_PGM_RSRC1 Compute Shader (CS)
program settings used by program settings used by
CP to set up CP to set up
``COMPUTE_PGM_RSRC1`` ``COMPUTE_PGM_RSRC1``
configuration configuration
register. See register. See
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
447:416 4 bytes COMPUTE_PGM_RSRC2 Compute Shader (CS) 447:416 4 bytes COMPUTE_PGM_RSRC2 Compute Shader (CS)
program settings used by program settings used by
CP to set up CP to set up
``COMPUTE_PGM_RSRC2`` ``COMPUTE_PGM_RSRC2``
configuration configuration
register. See register. See
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
458:448 7 bits *See separate bits below.* Enable the setup of the 458:448 7 bits *See separate bits below.* Enable the setup of the
SGPR user data registers SGPR user data registers
(see (see
:ref:`amdgpu-amdhsa-initial-kernel-execution-state`). :ref:`amdgpu-amdhsa-initial-kernel-execution-state`).
The total number of SGPR The total number of SGPR
user data registers user data registers
requested must not exceed requested must not exceed
Show All 26 Lines .. table:: Code Object V3 Kernel Descriptor
468 1 bit RESERVED_468 Deprecated, must be 0. 468 1 bit RESERVED_468 Deprecated, must be 0.
469:471 3 bits Reserved, must be 0. 469:471 3 bits Reserved, must be 0.
511:472 5 bytes Reserved, must be 0. 511:472 5 bytes Reserved, must be 0.
512 **Total size 64 bytes.** 512 **Total size 64 bytes.**
======= ==================================================================== ======= ====================================================================
.. ..
.. table:: compute_pgm_rsrc1 for GFX6-GFX10 .. table:: compute_pgm_rsrc1 for GFX6+
:name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table :name: amdgpu-amdhsa-compute_pgm_rsrc1-table
======= ======= =============================== =========================================================================== ======= ======= =============================== ===========================================================================
Bits Size Field Name Description Bits Size Field Name Description
======= ======= =============================== =========================================================================== ======= ======= =============================== ===========================================================================
5:0 6 bits GRANULATED_WORKITEM_VGPR_COUNT Number of vector register 5:0 6 bits GRANULATED_WORKITEM_VGPR_COUNT Number of vector register
blocks used by each work-item; blocks used by each work-item;
granularity is device granularity is device
specific: specific:
▲ Show 20 Lines • Show All 200 Lines • ▼ Show 20 Lines 25 1 bit CDBG_USER Must be 0.
Flag that can be used to Flag that can be used to
control debugging code. control debugging code.
CP is responsible for CP is responsible for
filling in filling in
``COMPUTE_PGM_RSRC1.CDBG_USER``. ``COMPUTE_PGM_RSRC1.CDBG_USER``.
26 1 bit FP16_OVFL GFX6-GFX8 26 1 bit FP16_OVFL GFX6-GFX8
Reserved, must be 0. Reserved, must be 0.
GFX9-GFX10 GFX9+
Wavefront starts execution Wavefront starts execution
with specified fp16 overflow with specified fp16 overflow
mode. mode.
- If 0, fp16 overflow generates - If 0, fp16 overflow generates
+/-INF values. +/-INF values.
- If 1, fp16 overflow that is the - If 1, fp16 overflow that is the
result of an +/-INF input value result of an +/-INF input value
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines 31 1 bit FWD_PROGRESS GFX6-9
Used by CP to set up Used by CP to set up
``COMPUTE_PGM_RSRC1.FWD_PROGRESS``. ``COMPUTE_PGM_RSRC1.FWD_PROGRESS``.
32 **Total size 4 bytes** 32 **Total size 4 bytes**
======= =================================================================================================================== ======= ===================================================================================================================
.. ..
.. table:: compute_pgm_rsrc2 for GFX6-GFX10 .. table:: compute_pgm_rsrc2 for GFX6+
:name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table :name: amdgpu-amdhsa-compute_pgm_rsrc2-table
======= ======= =============================== =========================================================================== ======= ======= =============================== ===========================================================================
Bits Size Field Name Description Bits Size Field Name Description
======= ======= =============================== =========================================================================== ======= ======= =============================== ===========================================================================
0 1 bit ENABLE_PRIVATE_SEGMENT Enable the setup of the 0 1 bit ENABLE_PRIVATE_SEGMENT Enable the setup of the
private segment. private segment.
In addition, enable the In addition, enable the
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines 23:15 9 bits GRANULATED_LDS_SIZE Must be 0.
Amount of group segment Amount of group segment
(LDS) to allocate for each (LDS) to allocate for each
work-group. Granularity is work-group. Granularity is
device specific: device specific:
GFX6: GFX6:
roundup(lds-size / (64 * 4)) roundup(lds-size / (64 * 4))
GFX7-GFX10: GFX7+:
roundup(lds-size / (128 * 4)) roundup(lds-size / (128 * 4))
24 1 bit ENABLE_EXCEPTION_IEEE_754_FP Wavefront starts execution 24 1 bit ENABLE_EXCEPTION_IEEE_754_FP Wavefront starts execution
_INVALID_OPERATION with specified exceptions _INVALID_OPERATION with specified exceptions
enabled. enabled.
Used by CP to set up Used by CP to set up
``COMPUTE_PGM_RSRC2.EXCP_EN`` ``COMPUTE_PGM_RSRC2.EXCP_EN``
Show All 17 Lines 30 1 bit ENABLE_EXCEPTION_INT_DIVIDE_BY Integer Division by Zero
only) only)
31 1 bit Reserved, must be 0. 31 1 bit Reserved, must be 0.
32 **Total size 4 bytes.** 32 **Total size 4 bytes.**
======= =================================================================================================================== ======= ===================================================================================================================
.. ..
.. table:: compute_pgm_rsrc3 for GFX10 .. table:: compute_pgm_rsrc3 for GFX10
:name: amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-table :name: amdgpu-amdhsa-compute_pgm_rsrc3-table
t-tyeUnsubmitted
Not Done
ReplyInline Actions

The title says GFX10 so the label should also have gfx10 in the name.

t-tye: The title says GFX10 so the label should also have gfx10 in the name.
======= ======= =============================== =========================================================================== ======= ======= =============================== ===========================================================================
Bits Size Field Name Description Bits Size Field Name Description
======= ======= =============================== =========================================================================== ======= ======= =============================== ===========================================================================
3:0 4 bits SHARED_VGPR_COUNT Number of shared VGPRs for wavefront size 64. Granularity 8. Value 0-120. 3:0 4 bits SHARED_VGPR_COUNT Number of shared VGPRs for wavefront size 64. Granularity 8. Value 0-120.
compute_pgm_rsrc1.vgprs + shared_vgpr_cnt cannot exceed 64. compute_pgm_rsrc1.vgprs + shared_vgpr_cnt cannot exceed 64.
31:4 28 Reserved, must be 0. 31:4 28 Reserved, must be 0.
bits bits
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines then Private Segment Size 1 The 32-bit byte size of a
Having CP load it once avoids Having CP load it once avoids
loading it at the beginning of loading it at the beginning of
every wavefront. every wavefront.
This is not used for This is not used for
GFX7-GFX8 since it is the same GFX7-GFX8 since it is the same
value as the second SGPR of value as the second SGPR of
Flat Scratch Init. However, it Flat Scratch Init. However, it
may be needed for GFX9-GFX10 which may be needed for GFX9+ which
changes the meaning of the changes the meaning of the
Flat Scratch Init value. Flat Scratch Init value.
then Grid Work-Group Count X 1 32-bit count of the number of then Grid Work-Group Count X 1 32-bit count of the number of
(enable_sgpr_grid work-groups in the X dimension (enable_sgpr_grid work-groups in the X dimension
_workgroup_count_X) for the grid being _workgroup_count_X) for the grid being
executed. Computed from the executed. Computed from the
fields in the kernel dispatch fields in the kernel dispatch
packet as ((grid_size.x + packet as ((grid_size.x +
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines3. Scratch Wavefront Offset is set by SPI in a per wavefront basis which is why
its value cannot be included with the flat scratch init value which is per its value cannot be included with the flat scratch init value which is per
queue (see :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`). queue (see :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`).
4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y) 4. The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
or (X, Y, Z). or (X, Y, Z).
5. Flat Scratch register pair initialization is described in 5. Flat Scratch register pair initialization is described in
:ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`. :ref:`amdgpu-amdhsa-kernel-prolog-flat-scratch`.
The global segment can be accessed either using buffer instructions (GFX6 which The global segment can be accessed either using buffer instructions (GFX6 which
has V# 64-bit address support), flat instructions (GFX7-GFX10), or global has V# 64-bit address support), flat instructions (GFX7+), or global
instructions (GFX9-GFX10). instructions (GFX9+).
If buffer operations are used, then the compiler can generate a V# with the If buffer operations are used, then the compiler can generate a V# with the
following properties: following properties:
* base address of 0 * base address of 0
* no swizzle * no swizzle
* ATC: 1 if IOMMU present (such as APU) * ATC: 1 if IOMMU present (such as APU)
* ptr64: 1 * ptr64: 1
Show All 29 Lines
++ ++
GFX6-GFX8 GFX6-GFX8
The M0 register must be initialized with a value at least the total LDS size The M0 register must be initialized with a value at least the total LDS size
if the kernel may access LDS via DS or flat operations. Total LDS size is if the kernel may access LDS via DS or flat operations. Total LDS size is
available in dispatch packet. For M0, it is also possible to use maximum available in dispatch packet. For M0, it is also possible to use maximum
possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for
GFX7-GFX8). GFX7-GFX8).
GFX9-GFX10 GFX9+
The M0 register is not used for range checking LDS accesses and so does not The M0 register is not used for range checking LDS accesses and so does not
need to be initialized in the prolog. need to be initialized in the prolog.
.. _amdgpu-amdhsa-kernel-prolog-stack-pointer: .. _amdgpu-amdhsa-kernel-prolog-stack-pointer:
Stack Pointer Stack Pointer
+++++++++++++ +++++++++++++
▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 Lines
``ds/flat_load/store/atomic`` instructions to local memory are termed LDS ``ds/flat_load/store/atomic`` instructions to local memory are termed LDS
operations. operations.
``buffer/global/flat_load/store/atomic`` instructions to global memory are ``buffer/global/flat_load/store/atomic`` instructions to global memory are
termed vector memory operations. termed vector memory operations.
Private address space uses ``buffer_load/store`` using the scratch V# Private address space uses ``buffer_load/store`` using the scratch V#
(GFX6-GFX8), or ``scratch_load/store`` (GFX9-GFX10). Since only a single thread (GFX6-GFX8), or ``scratch_load/store`` (GFX9+). Since only a single thread
is accessing the memory, atomic memory orderings are not meaningful, and all is accessing the memory, atomic memory orderings are not meaningful, and all
accesses are treated as non-atomic. accesses are treated as non-atomic.
Constant address space uses ``buffer/global_load`` instructions (or equivalent Constant address space uses ``buffer/global_load`` instructions (or equivalent
scalar memory instructions). Since the constant address space contents do not scalar memory instructions). Since the constant address space contents do not
change during the execution of a kernel dispatch it is not legal to perform change during the execution of a kernel dispatch it is not legal to perform
stores, and atomic memory orderings are not meaningful, and all accesses are stores, and atomic memory orderings are not meaningful, and all accesses are
treated as non-atomic. treated as non-atomic.
▲ Show 20 Lines • Show All 1,422 Lines • ▼ Show 20 Lines
with MTYPE NC (non-coherent). Since the private address space is only accessed with MTYPE NC (non-coherent). Since the private address space is only accessed
by a single thread, and is always write-before-read, there is never a need to by a single thread, and is always write-before-read, there is never a need to
invalidate these entries from the L0 or L1 caches. invalidate these entries from the L0 or L1 caches.
Wavefronts are executed in native mode with in-order reporting of loads and Wavefronts are executed in native mode with in-order reporting of loads and
sample instructions. In this mode vmcnt reports completion of load, atomic with sample instructions. In this mode vmcnt reports completion of load, atomic with
return and sample instructions in order, and the vscnt reports the completion of return and sample instructions in order, and the vscnt reports the completion of
store and atomic without return in order. See ``MEM_ORDERED`` field in store and atomic without return in order. See ``MEM_ORDERED`` field in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
Wavefronts can be executed in WGP or CU wavefront execution mode: Wavefronts can be executed in WGP or CU wavefront execution mode:
* In WGP wavefront execution mode the wavefronts of a work-group are executed * In WGP wavefront execution mode the wavefronts of a work-group are executed
on the SIMDs of both CUs of the WGP. Therefore, explicit management of the per on the SIMDs of both CUs of the WGP. Therefore, explicit management of the per
CU L0 caches is required for work-group synchronization. Also accesses to L1 CU L0 caches is required for work-group synchronization. Also accesses to L1
at work-group scope need to be explicitly ordered as the accesses from at work-group scope need to be explicitly ordered as the accesses from
different CUs are not ordered. different CUs are not ordered.
* In CU wavefront execution mode the wavefronts of a work-group are executed on * In CU wavefront execution mode the wavefronts of a work-group are executed on
the SIMDs of a single CU of the WGP. Therefore, all global memory access by the SIMDs of a single CU of the WGP. Therefore, all global memory access by
the work-group access the same L0 which in turn ensures L1 accesses are the work-group access the same L0 which in turn ensures L1 accesses are
ordered and so do not require explicit management of the caches for ordered and so do not require explicit management of the caches for
work-group synchronization. work-group synchronization.
See ``WGP_MODE`` field in See ``WGP_MODE`` field in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table` and :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table` and
:ref:`amdgpu-target-features`. :ref:`amdgpu-target-features`.
The code sequences used to implement the memory model for GFX10 are defined in The code sequences used to implement the memory model for GFX10 are defined in
table :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx10-table`. table :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx10-table`.
.. table:: AMDHSA Memory Model Code Sequences GFX10 .. table:: AMDHSA Memory Model Code Sequences GFX10
:name: amdgpu-amdhsa-memory-model-code-sequences-gfx10-table :name: amdgpu-amdhsa-memory-model-code-sequences-gfx10-table
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1. The HSA memory model is used (see :ref:`amdgpu-amdhsa-memory-model`). 1. The HSA memory model is used (see :ref:`amdgpu-amdhsa-memory-model`).
.. _amdgpu-assembler: .. _amdgpu-assembler:
Assembler Assembler
--------- ---------
AMDGPU backend has LLVM-MC based assembler which is currently in development. AMDGPU backend has LLVM-MC based assembler which is currently in development.
It supports AMDGCN GFX6-GFX10. It supports AMDGCN GFX6+.
This section describes general syntax for instructions and operands. This section describes general syntax for instructions and operands.
Instructions Instructions
~~~~~~~~~~~~ ~~~~~~~~~~~~
An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`: An instruction has the following :doc:`syntax<AMDGPUInstructionSyntax>`:
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terminated by an ``.end_amdhsa_kernel`` directive. terminated by an ``.end_amdhsa_kernel`` directive.
.. table:: AMDHSA Kernel Assembler Directives .. table:: AMDHSA Kernel Assembler Directives
:name: amdhsa-kernel-directives-table :name: amdhsa-kernel-directives-table
======================================================== =================== ============ =================== ======================================================== =================== ============ ===================
Directive Default Supported On Description Directive Default Supported On Description
======================================================== =================== ============ =================== ======================================================== =================== ============ ===================
``.amdhsa_group_segment_fixed_size`` 0 GFX6-GFX10 Controls GROUP_SEGMENT_FIXED_SIZE in ``.amdhsa_group_segment_fixed_size`` 0 GFX6+ Controls GROUP_SEGMENT_FIXED_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_private_segment_fixed_size`` 0 GFX6-GFX10 Controls PRIVATE_SEGMENT_FIXED_SIZE in ``.amdhsa_private_segment_fixed_size`` 0 GFX6+ Controls PRIVATE_SEGMENT_FIXED_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_kernarg_size`` 0 GFX6-GFX10 Controls KERNARG_SIZE in ``.amdhsa_kernarg_size`` 0 GFX6+ Controls KERNARG_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in ``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6+ Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_PTR in ``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6+ Controls ENABLE_SGPR_DISPATCH_PTR in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_QUEUE_PTR in ``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6+ Controls ENABLE_SGPR_QUEUE_PTR in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in ``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6+ Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_ID in ``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6+ Controls ENABLE_SGPR_DISPATCH_ID in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6-GFX10 Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in ``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6+ Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in ``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6+ Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
``.amdhsa_wavefront_size32`` Target GFX10 Controls ENABLE_WAVEFRONT_SIZE32 in ``.amdhsa_wavefront_size32`` Target GFX10 Controls ENABLE_WAVEFRONT_SIZE32 in
Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
Specific Specific
(wavefrontsize64) (wavefrontsize64)
``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6-GFX10 Controls ENABLE_PRIVATE_SEGMENT in ``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6+ Controls ENABLE_PRIVATE_SEGMENT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_X in ``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6+ Controls ENABLE_SGPR_WORKGROUP_ID_X in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_Y in ``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6+ Controls ENABLE_SGPR_WORKGROUP_ID_Y in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_system_sgpr_workgroup_id_z`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_Z in ``.amdhsa_system_sgpr_workgroup_id_z`` 0 GFX6+ Controls ENABLE_SGPR_WORKGROUP_ID_Z in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_system_sgpr_workgroup_info`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_INFO in ``.amdhsa_system_sgpr_workgroup_info`` 0 GFX6+ Controls ENABLE_SGPR_WORKGROUP_INFO in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_system_vgpr_workitem_id`` 0 GFX6-GFX10 Controls ENABLE_VGPR_WORKITEM_ID in ``.amdhsa_system_vgpr_workitem_id`` 0 GFX6+ Controls ENABLE_VGPR_WORKITEM_ID in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
Possible values are defined in Possible values are defined in
:ref:`amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table`. :ref:`amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table`.
``.amdhsa_next_free_vgpr`` Required GFX6-GFX10 Maximum VGPR number explicitly referenced, plus one. ``.amdhsa_next_free_vgpr`` Required GFX6+ Maximum VGPR number explicitly referenced, plus one.
Used to calculate GRANULATED_WORKITEM_VGPR_COUNT in Used to calculate GRANULATED_WORKITEM_VGPR_COUNT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
``.amdhsa_next_free_sgpr`` Required GFX6-GFX10 Maximum SGPR number explicitly referenced, plus one. ``.amdhsa_next_free_sgpr`` Required GFX6+ Maximum SGPR number explicitly referenced, plus one.
Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
``.amdhsa_reserve_vcc`` 1 GFX6-GFX10 Whether the kernel may use the special VCC SGPR. ``.amdhsa_reserve_vcc`` 1 GFX6+ Whether the kernel may use the special VCC SGPR.
Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
``.amdhsa_reserve_flat_scratch`` 1 GFX7-GFX10 Whether the kernel may use flat instructions to access ``.amdhsa_reserve_flat_scratch`` 1 GFX7+ Whether the kernel may use flat instructions to access
scratch memory. Used to calculate scratch memory. Used to calculate
GRANULATED_WAVEFRONT_SGPR_COUNT in GRANULATED_WAVEFRONT_SGPR_COUNT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
``.amdhsa_reserve_xnack_mask`` Target GFX8-GFX10 Whether the kernel may trigger XNACK replay. ``.amdhsa_reserve_xnack_mask`` Target GFX8+ Whether the kernel may trigger XNACK replay.
Feature Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in Feature Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
Specific :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. Specific :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
(xnack) (xnack)
``.amdhsa_float_round_mode_32`` 0 GFX6-GFX10 Controls FLOAT_ROUND_MODE_32 in ``.amdhsa_float_round_mode_32`` 0 GFX6+ Controls FLOAT_ROUND_MODE_32 in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
Possible values are defined in Possible values are defined in
:ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`. :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
``.amdhsa_float_round_mode_16_64`` 0 GFX6-GFX10 Controls FLOAT_ROUND_MODE_16_64 in ``.amdhsa_float_round_mode_16_64`` 0 GFX6+ Controls FLOAT_ROUND_MODE_16_64 in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
Possible values are defined in Possible values are defined in
:ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`. :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`.
``.amdhsa_float_denorm_mode_32`` 0 GFX6-GFX10 Controls FLOAT_DENORM_MODE_32 in ``.amdhsa_float_denorm_mode_32`` 0 GFX6+ Controls FLOAT_DENORM_MODE_32 in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
Possible values are defined in Possible values are defined in
:ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`. :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
``.amdhsa_float_denorm_mode_16_64`` 3 GFX6-GFX10 Controls FLOAT_DENORM_MODE_16_64 in ``.amdhsa_float_denorm_mode_16_64`` 3 GFX6+ Controls FLOAT_DENORM_MODE_16_64 in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
Possible values are defined in Possible values are defined in
:ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`. :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
``.amdhsa_dx10_clamp`` 1 GFX6-GFX10 Controls ENABLE_DX10_CLAMP in ``.amdhsa_dx10_clamp`` 1 GFX6+ Controls ENABLE_DX10_CLAMP in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
``.amdhsa_ieee_mode`` 1 GFX6-GFX10 Controls ENABLE_IEEE_MODE in ``.amdhsa_ieee_mode`` 1 GFX6+ Controls ENABLE_IEEE_MODE in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
``.amdhsa_fp16_overflow`` 0 GFX9-GFX10 Controls FP16_OVFL in ``.amdhsa_fp16_overflow`` 0 GFX9+ Controls FP16_OVFL in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
``.amdhsa_workgroup_processor_mode`` Target GFX10 Controls ENABLE_WGP_MODE in ``.amdhsa_workgroup_processor_mode`` Target GFX10 Controls ENABLE_WGP_MODE in
Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`.
Specific Specific
(cumode) (cumode)
``.amdhsa_memory_ordered`` 1 GFX10 Controls MEM_ORDERED in ``.amdhsa_memory_ordered`` 1 GFX10 Controls MEM_ORDERED in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
``.amdhsa_forward_progress`` 0 GFX10 Controls FWD_PROGRESS in ``.amdhsa_forward_progress`` 0 GFX10 Controls FWD_PROGRESS in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-table`.
``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in ``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6+ Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_exception_fp_denorm_src`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in ``.amdhsa_exception_fp_denorm_src`` 0 GFX6+ Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_exception_fp_ieee_div_zero`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in ``.amdhsa_exception_fp_ieee_div_zero`` 0 GFX6+ Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_exception_fp_ieee_overflow`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in ``.amdhsa_exception_fp_ieee_overflow`` 0 GFX6+ Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_exception_fp_ieee_underflow`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in ``.amdhsa_exception_fp_ieee_underflow`` 0 GFX6+ Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_exception_fp_ieee_inexact`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in ``.amdhsa_exception_fp_ieee_inexact`` 0 GFX6+ Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
``.amdhsa_exception_int_div_zero`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in ``.amdhsa_exception_int_div_zero`` 0 GFX6+ Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-table`.
======================================================== =================== ============ =================== ======================================================== =================== ============ ===================
.amdgpu_metadata .amdgpu_metadata
++++++++++++++++ ++++++++++++++++
Optional directive which declares the contents of the ``NT_AMDGPU_METADATA`` Optional directive which declares the contents of the ``NT_AMDGPU_METADATA``
note record (see :ref:`amdgpu-elf-note-records-table-v3-v4`). note record (see :ref:`amdgpu-elf-note-records-table-v3-v4`).
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