[PowerPC] Add missing negate for VPERMXOR on little endian subtargets

[nemanjai]

Summary

This intrinsic is supposed to have the permute control vector complemented on little endian systems (as the ABI specifies and GCC implements). With the current code gen, the result vector is byte-reversed.

[nemanjai]

Fixed the inadvertently reversed operands in the instruction definition.

[saghir]

LGTM.

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2442

s/system/subtargets

[NeHuang]

LGTM

[NeHuang]

llvm/test/CodeGen/PowerPC/crypto_bifs.ll

2

nit: Is it necessary to add "--check-prefix=CHECK" in line 2 and line 6?

[amyk]

Also LGTM.

llvm/lib/Target/PowerPC/PPCInstrVSX.td

2443

nit: Maybe add the new predicates in the Predicate combinations available comment? :)

llvm/lib/Target/PowerPC/PPCInstrAltivec.td

 def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",
                          int_ppc_altivec_crypto_vpmsumb, v16i8>;
 def VPMSUMH : VX1_Int_Ty<1096, "vpmsumh",
                          int_ppc_altivec_crypto_vpmsumh, v8i16>;
 def VPMSUMW : VX1_Int_Ty<1160, "vpmsumw",
                          int_ppc_altivec_crypto_vpmsumw, v4i32>;
 def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd",
                          int_ppc_altivec_crypto_vpmsumd, v2i64>;
-def VPERMXOR : VA1a_Int_Ty<45, "vpermxor",
-                         int_ppc_altivec_crypto_vpermxor, v16i8>;
+def VPERMXOR : VAForm_1<45, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VC),
+                        "vpermxor $VD, $VA, $VB, $VC", IIC_VecFP, []>;
 
 // Vector doubleword integer pack and unpack.
 let hasSideEffects = 1 in {
   def VPKSDSS : VX1_Int_Ty2<1486, "vpksdss", int_ppc_altivec_vpksdss,
                             v4i32, v2i64>;
   def VPKSDUS : VX1_Int_Ty2<1358, "vpksdus", int_ppc_altivec_vpksdus,
                             v4i32, v2i64>;
   def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus,

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 // ISA 3.0 (Power9). However, the granularity of features on later subtargets
 // is finer for various reasons. For example, we have Power8Vector,
 // Power8Altivec, DirectMove that all came in with ISA 2.07. The situation is
 // similar with ISA 3.0 with Power9Vector, Power9Altivec, IsISA3_0. Then there
 // are orthogonal predicates such as endianness for which the order was
 // arbitrarily chosen to be Big, Little.
 //
 // Predicate combinations available:
+// [HasVSX, IsLittleEndian, HasP8Altivec] Altivec patterns using VSX instr.
+// [HasVSX, IsBigEndian, HasP8Altivec] Altivec patterns using VSX instr.
 // [HasVSX]
 // [HasVSX, IsBigEndian]
 // [HasVSX, IsLittleEndian]
 // [HasVSX, NoP9Vector]
 // [HasVSX, NoP9Vector, IsLittleEndian]
 // [HasVSX, HasOnlySwappingMemOps]
 // [HasVSX, HasOnlySwappingMemOps, IsBigEndian]
 // [HasVSX, HasP8Vector]

 // [HasVSX, HasP9Vector, IsBigEndian, IsPPC64]
 // [HasVSX, HasP9Vector, IsLittleEndian]
 // [HasVSX, HasP9Altivec]
 // [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64]
 // [HasVSX, HasP9Altivec, IsLittleEndian]
 // [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64]
 // [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian]
 
+// These Altivec patterns are here because we need a VSX instruction to match
+// the intrinsic (but only for little endian system).
+let Predicates = [HasVSX, IsLittleEndian, HasP8Altivec] in
+  def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,
+                                                    v16i8:$b, v16i8:$c)),
+            (v16i8 (VPERMXOR $a, $b, (XXLNOR (COPY_TO_REGCLASS $c, VSRC),
+                                             (COPY_TO_REGCLASS $c, VSRC))))>;
+let Predicates = [HasVSX, IsBigEndian, HasP8Altivec] in
+  def : Pat<(v16i8 (int_ppc_altivec_crypto_vpermxor v16i8:$a,
+                                                    v16i8:$b, v16i8:$c)),
+            (v16i8 (VPERMXOR $a, $b, $c))>;
+
 let AddedComplexity = 400 in {
 // Valid for any VSX subtarget, regardless of endianness.
 let Predicates = [HasVSX] in {
 def : Pat<(v4i32 (vnot_ppc v4i32:$A)),
           (v4i32 (XXLNOR $A, $A))>;
 def : Pat<(v4i32 (or (and (vnot_ppc v4i32:$C), v4i32:$A),
                      (and v4i32:$B, v4i32:$C))),
           (v4i32 (XXSEL $A, $B, $C))>;

llvm/test/CodeGen/PowerPC/crypto_bifs.ll

-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+crypto < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 -mattr=+crypto < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-LE
 ; FIXME: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
 ; FIXME: The original intent was to add a check-next for the blr after every check.
 ; However, this currently fails since we don't eliminate stores of the unused
 ; locals. These stores are sometimes scheduled after the crypto instruction
 
 ; Function Attrs: nounwind
 define <16 x i8> @test_vpmsumb() #0 {
 entry:
entry:
   store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %a, align 16
   store <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8>* %b, align 16
   store <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8>* %c, align 16
   %0 = load <16 x i8>,  <16 x i8>* %a, align 16
   %1 = load <16 x i8>,  <16 x i8>* %b, align 16
   %2 = load <16 x i8>,  <16 x i8>* %c, align 16
   %3 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
   ret <16 x i8> %3
+; CHECK-LE: xxlnor
 ; CHECK: vpermxor 2,
 }
 
 ; Function Attrs: nounwind readnone
 declare <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8>, <16 x i8>, <16 x i8>) #1
 
 ; Function Attrs: nounwind
 define <8 x i16> @test_vpermxorh() #0 {
 entry:
   %a = alloca <8 x i16>, align 16
   %b = alloca <8 x i16>, align 16
   %c = alloca <8 x i16>, align 16
   store <8 x i16> <i16 258, i16 772, i16 1286, i16 1800, i16 2314, i16 2828, i16 3342, i16 3856>, <8 x i16>* %a, align 16
   store <8 x i16> <i16 29042, i16 29556, i16 30070, i16 30584, i16 31098, i16 31612, i16 32126, i16 32624>, <8 x i16>* %b, align 16
   store <8 x i16> <i16 29042, i16 29556, i16 30070, i16 30584, i16 31098, i16 31612, i16 32126, i16 32624>, <8 x i16>* %c, align 16
   %0 = load <8 x i16>,  <8 x i16>* %a, align 16
   %1 = bitcast <8 x i16> %0 to <16 x i8>
   %2 = load <8 x i16>,  <8 x i16>* %b, align 16
   %3 = bitcast <8 x i16> %2 to <16 x i8>
   %4 = load <8 x i16>,  <8 x i16>* %c, align 16
   %5 = bitcast <8 x i16> %4 to <16 x i8>
   %6 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %1, <16 x i8> %3, <16 x i8> %5)
   %7 = bitcast <16 x i8> %6 to <8 x i16>
   ret <8 x i16> %7
+; CHECK-LE: xxlnor
 ; CHECK: vpermxor 2,
 }
 
 ; Function Attrs: nounwind
 define <4 x i32> @test_vpermxorw() #0 {
 entry:
   %a = alloca <4 x i32>, align 16
   %b = alloca <4 x i32>, align 16
   %c = alloca <4 x i32>, align 16
   store <4 x i32> <i32 16909060, i32 84281096, i32 151653132, i32 219025168>, <4 x i32>* %a, align 16
   store <4 x i32> <i32 1903326068, i32 1970698104, i32 2038070140, i32 2105442160>, <4 x i32>* %b, align 16
   store <4 x i32> <i32 1903326068, i32 1970698104, i32 2038070140, i32 2105442160>, <4 x i32>* %c, align 16
   %0 = load <4 x i32>,  <4 x i32>* %a, align 16
   %1 = bitcast <4 x i32> %0 to <16 x i8>
   %2 = load <4 x i32>,  <4 x i32>* %b, align 16
   %3 = bitcast <4 x i32> %2 to <16 x i8>
   %4 = load <4 x i32>,  <4 x i32>* %c, align 16
   %5 = bitcast <4 x i32> %4 to <16 x i8>
   %6 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %1, <16 x i8> %3, <16 x i8> %5)
   %7 = bitcast <16 x i8> %6 to <4 x i32>
   ret <4 x i32> %7
+; CHECK-LE: xxlnor
 ; CHECK: vpermxor 2,
 }
 
 ; Function Attrs: nounwind
 define <2 x i64> @test_vpermxord() #0 {
 entry:
   %a = alloca <2 x i64>, align 16
   %b = alloca <2 x i64>, align 16
   %c = alloca <2 x i64>, align 16
   store <2 x i64> <i64 72623859790382856, i64 651345242494996240>, <2 x i64>* %a, align 16
   store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %b, align 16
   store <2 x i64> <i64 8174723217654970232, i64 8753444600359583600>, <2 x i64>* %c, align 16
   %0 = load <2 x i64>,  <2 x i64>* %a, align 16
   %1 = bitcast <2 x i64> %0 to <16 x i8>
   %2 = load <2 x i64>,  <2 x i64>* %b, align 16
   %3 = bitcast <2 x i64> %2 to <16 x i8>
   %4 = load <2 x i64>,  <2 x i64>* %c, align 16
   %5 = bitcast <2 x i64> %4 to <16 x i8>
   %6 = call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor(<16 x i8> %1, <16 x i8> %3, <16 x i8> %5)
   %7 = bitcast <16 x i8> %6 to <2 x i64>
   ret <2 x i64> %7
+; CHECK-LE: xxlnor
 ; CHECK: vpermxor 2,
 }
 
 ; Function Attrs: nounwind
 define <2 x i64> @test_vcipher() #0 {
 entry:
   %a = alloca <2 x i64>, align 16
   %b = alloca <2 x i64>, align 16