Previously uniqueCallSite could have race conditions between different
threads. Now it is accessed with an atomic RMW and will be unique
between different threads.
Details
Details
Diff Detail
Diff Detail
- Repository
- rG LLVM Github Monorepo
Paths
| Differential D94784
[llvm][nvptx] add atomicity to counter in ISelLowering ClosedPublic Authored by tpopp on Jan 15 2021, 8:13 AM.
Details Summary Previously uniqueCallSite could have race conditions between different
Diff Detail
Event Timelinebkramer added inline comments. This revision is now accepted and ready to land.Jan 18 2021, 9:43 AM This revision was landed with ongoing or failed builds.Jan 19 2021, 1:20 AM Closed by commit rG170199f56262: [llvm][nvptx] add atomicity to counter in ISelLowering (authored by Tres Popp <tpopp@google.com>). · Explain Why This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 317056 llvm/lib/Target/NVPTX/NVPTXISelLowering.h
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
|
clang-tidy: warning: invalid case style for parameter 'retAlignment' [readability-identifier-naming]
not useful