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[llvm][nvptx] add atomicity to counter in ISelLowering
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Authored by tpopp on Jan 15 2021, 8:13 AM.

Details

Summary

Previously uniqueCallSite could have race conditions between different
threads. Now it is accessed with an atomic RMW and will be unique
between different threads.

Diff Detail

Event Timeline

tpopp created this revision.Jan 15 2021, 8:13 AM
tpopp requested review of this revision.Jan 15 2021, 8:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 15 2021, 8:13 AM
tpopp updated this revision to Diff 316976.Jan 15 2021, 9:00 AM

Match LLVM naming convention.

tpopp updated this revision to Diff 317056.Jan 15 2021, 1:09 PM

Another naming convention correction.

bkramer accepted this revision.Jan 18 2021, 9:43 AM
bkramer added inline comments.
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
68

Unnecessary, globals are always initialized to 0.

1246

Just pass unsigned by value

This revision is now accepted and ready to land.Jan 18 2021, 9:43 AM
This revision was landed with ongoing or failed builds.Jan 19 2021, 1:20 AM
This revision was automatically updated to reflect the committed changes.
tpopp marked 2 inline comments as done.Jan 19 2021, 1:20 AM