[AArch64][GlobalISel] Assign FPR banks to loads which are used by integer->float conversions.

[aemerson]

Summary

G_[US]ITOFP users of loads on AArch64 can operate on both gpr and fpr banks for scalars. Because of this, if their source is a load, then that load can be assigned to an fpr bank and therefore avoid having to do a cross bank copy via a gpr->fpr conversion.

[paquette]

LGTM

llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir

384

Doesn't look like the G_FCONSTANTs are used here, or in the other test?

[aemerson]

llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir

384

Yep, will remove.

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   }
   case TargetOpcode::G_TRUNC: {
     LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
     if (!SrcTy.isVector() && SrcTy.getSizeInBits() == 128)
       OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
     break;
   }
   case TargetOpcode::G_SITOFP:
-  case TargetOpcode::G_UITOFP:
+  case TargetOpcode::G_UITOFP: {
     if (MRI.getType(MI.getOperand(0).getReg()).isVector())
       break;
+    // Integer to FP conversions don't necessarily happen between GPR -> FPR
+    // regbanks. They can also be done within an FPR register.
+    Register SrcReg = MI.getOperand(1).getReg();
+    if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank)
+      OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
+    else
       OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
     break;
+  }
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI:
     if (MRI.getType(MI.getOperand(0).getReg()).isVector())
       break;
     OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
     break;
   case TargetOpcode::G_FCMP:
     OpRegBankIdx = {PMI_FirstGPR,
else
       // In that case, we want the default mapping to be on FPR
       // instead of blind map every scalar to GPR.
       for (const MachineInstr &UseMI :
            MRI.use_nodbg_instructions(MI.getOperand(0).getReg())) {
         // If we have at least one direct use in a FP instruction,
         // assume this was a floating point load in the IR.
         // If it was not, we would have had a bitcast before
         // reaching that instruction.
-        if (onlyUsesFP(UseMI, MRI, TRI)) {
+        // Int->FP conversion operations are also captured in onlyDefinesFP().
+        if (onlyUsesFP(UseMI, MRI, TRI) || onlyDefinesFP(UseMI, MRI, TRI)) {
           OpRegBankIdx[0] = PMI_FirstFPR;
           break;
         }
       }
     break;
   case TargetOpcode::G_STORE:
     // Check if that store is fed by fp instructions.
     if (OpRegBankIdx[0] == PMI_FirstGPR) {

llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect %s -o - | FileCheck %s
 
 # Check that we correctly assign register banks based off of instructions which
 # only use or only define FPRs.
 #
-# For example, G_SITOFP takes in a GPR, but only ever produces values on FPRs.
+# For example, G_SITOFP may take in a GPR, but only ever produces values on FPRs.
 # Some instructions can have inputs/outputs on either FPRs or GPRs. If one of
 # those instructions takes in the result of a G_SITOFP as a source, we should
 # put that source on a FPR.
 #
 # Similarly, G_FPTOSI can only take in a value on a FPR. So, if the result of
 # an instruction is consumed by a G_FPTOSI, we should put the instruction on
 # FPRs.
 
body:             |
   bb.1:
     successors: %bb.2
     %unmerge_1:_(s32), %unmerge_2:_(s32) = G_UNMERGE_VALUES %unmerge_src(s64)
     G_BR %bb.2
   bb.2:
     %phi:_(s32) = G_PHI %gpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
     $s0 = COPY %phi(s32)
     RET_ReallyLR implicit $s0
+
+...
+---
+name:            load_used_by_sitofp
+legalized:       true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0
+    ; The load should be assigned an fpr bank because it's used by the sitofp.
+    ; The sitofp should assign both src and dest to FPR, resulting in no copies.
+    ; CHECK-LABEL: name: load_used_by_sitofp
+    ; CHECK: liveins: $x0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
+    ; CHECK: [[LOAD:%[0-9]+]]:fpr(s32) = G_LOAD [[COPY]](p0) :: (load 4)
+    ; CHECK: [[SITOFP:%[0-9]+]]:fpr(s32) = G_SITOFP [[LOAD]](s32)
+    ; CHECK: $s0 = COPY [[SITOFP]](s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %0:_(p0) = COPY $x0
+    %1:_(s32) = G_LOAD %0 :: (load 4)
+    %2:_(s32) = G_SITOFP %1:_(s32)
+    $s0 = COPY %2(s32)
+    RET_ReallyLR implicit $s0
+...
+---
+name:            load_used_by_uitofp
+legalized:       true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: load_used_by_uitofp
+    ; CHECK: liveins: $x0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
+    ; CHECK: [[LOAD:%[0-9]+]]:fpr(s32) = G_LOAD [[COPY]](p0) :: (load 4)
+    ; CHECK: [[UITOFP:%[0-9]+]]:fpr(s32) = G_UITOFP [[LOAD]](s32)
+    ; CHECK: $s0 = COPY [[UITOFP]](s32)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %0:_(p0) = COPY $x0
+    %1:_(s32) = G_LOAD %0 :: (load 4)
+    %2:_(s32) = G_UITOFP %1:_(s32)
+    $s0 = COPY %2(s32)
+    RET_ReallyLR implicit $s0
+...