TargetParser prototype - NFC (ARM only)

[rengolin]

Summary

This new class in a global context contain arch-specific knowledge in order
to provide LLVM libraries, tools and projects with the ability to understand
the architectures. For now, only FPU, ARCH and ARCH extensions on ARM are
supported.

Current behaviour it to parse from free-text to enum values and back, so that
all users can share the same parser and codes. This simplifies a lot both the
ASM/Obj streamers in the back-end (where this came from), and the front-end
parsers for command line arguments (where this is going to be used next).

The previous implementation, using .def/.h includes is deprecated due to its
inflexibility to be built without the backend support and for being too
cumbersome. As more architectures join this scheme, and as more features of
such architectures are added (such as hardware features, type sizes, etc) into
a full blown TargetDescription class, having a set of classes is the most
sane implementation.

The ultimate goal of this refactor both LLVM's and Clang's target description
classes into one unique interface, so that we can de-duplicate and standardise
the descriptions, as well as make it available for other front-ends, tools,
etc.

The FPU parsing for command line options in Clang has been converted to use
this new library and a number of aliases were added for compatibility:

• A bogus neon-vfpv3 alias (neon defaults to vfp3)
• armv5/v6
• {fp4/fp5}-{sp/dp}-d16

Next steps:

• Port Clang's FPU/ARCH/EXT parsing to use this library.
• Create a TableGen back-end to generate this information.
• Run this TableGen process regardless of which back-ends are built.
• Expose more information and rename it to TargetDescription.
• Re-factor Clang to use as much of it as possible.

Notes:

• The patter is the same as ARMBuildAttrs, but uses a class instead of global functions. This is due to the fact that we may want later to extend the description abilities and remove the "ARM" from the TargetParser, making it a polymorphic class. For now, we only have target parser usage in target specific area, so it should work ok.
• It's in Support because we don't want to tie to any specific back-end, but the arch-specific knowledge should later be generated by a TableGen back-end on a generic context, so some .td files will be exposed for the architectures supported even if we're not building those back-ends. This is to be done well later.
• The IDs are in the exact same order as before, and the parsing is pretty much in the same way (StringSwitch vs. iteration), so no functional or performance changes should happen.
• Clang's patch is in D9549.

[rengolin]

Cleaning some left-over comments.

[rengolin]

New line at end of file warning.

[john.brawn]

A general question: how far are you planning to go with this, in particular are you going to sort out cpu <-> arch mapping (which is duplicated in several places)?

I ask because I'm currently thinking about adjusting the ARM -mcpu and -march handling in clang to be more like AArch64, in particular making -march=garbage not mean -mcpu=arm7tdmi (and instead give an error), and it's be nice to not collide with what you're doing.

include/llvm/Support/ARMTargetParser.h

91–92

Synonym.

lib/Support/ARMTargetParser.cpp

158–159

The -sp-d16 FP variants aren't synonyms for the -d16 variants. This preserves the current behaviour, where clang -S -mfpu=fpv5-sp-d16 gets you .fpu fpv5-d16 (which doesn't seem right to me), but it could at least do with a comment.

[rengolin]

include/llvm/Support/ARMTargetParser.h

91–92

Oops. :)

lib/Support/ARMTargetParser.cpp

158–159

Yes, I'm trying to keep 100% compatibility, so that this doesn't break anything obscure and I have to revert the refactoring. Once the mechanism is in place, it'll be *a lot* easier to make it right in a single place.

I'll add a comment.

[rengolin]

typo + fixme

[rengolin]

A few new alias found while supporting Clang's FPU parser.

[rengolin]

Adding more FIXMEs. I'll be doing them as soon as this patch is in.

[rnk]

I guess Support is an OK place to park this particular pile of strings, enums, and tables. The target feature CPU and feature parsing is very similar in nature to triple parsing.

If this reaches the logical conclusion, we'll have a file per in-tree LLVM backend, or 13 files. At that point, we might wish to make a new library.

include/llvm/Support/ARMTargetParser.h

24

Actually, I'd much rather use .def files if possible. TableGen slows down builds and is hard to understand. Sure, pre-processor macros are hard to reason about, but they're *still* easier to understand than tablegen.

Also, so long as this library is in Support, and I think it will be here for a while, this FIXME is unactionable because Support cannot depend on TableGen.

I think we can solve any inflexibility of .def files with a separate plain C++ source synonym table, like you currently have.

lib/Support/ARMTargetParser.cpp

105–106

This style of separating the class name and the method name appears in LLVM, but it's really uncommon and I don't want to encourage it. Do you mind not using it?

[rengolin]

In D9435#168002, @rnk wrote:

I guess Support is an OK place to park this particular pile of strings, enums, and tables. The target feature CPU and feature parsing is very similar in nature to triple parsing.

Yes. The idea is to have triple parsing joined with this library, and possible ARM attributes, too, into one big TargetDescription library, which will probably reside in TargetDescription.h/cpp files.

If this reaches the logical conclusion, we'll have a file per in-tree LLVM backend, or 13 files. At that point, we might wish to make a new library.

I think I should rename it now to TargetParser, so that it's clear that this is not just ARM. Or I could call it TargetDescription.cpp/h and leave just the parser for now, then refactor it later.

cheers,
--renato

include/llvm/Support/ARMTargetParser.h

24

The reason for using TableGen is that this information is already there. We just need to extract it with a new back-end to just output a small number of tables, instead of duplicating it here and getting it out of sync, again.

We discussed this earlier, and the consensus was that having a common TableGen run for the basic target information independent of which back-ends are compiled. Again, because that information is *already* there, and new hardware information is added in TableGen files, so these tables will be updated automatically.

With .def files, we'd probably have to populate them via TableGen to get up-to-date information anyway. Doesn't make much difference. I personally would rather have a larger header than multiple .def files.

lib/Support/ARMTargetParser.cpp

105–106

sure! That was a side effect of refactoring. I also dislike it. :)

[rengolin]

Changes due to comments:

• Re-write method names in a single line
• Rename ARMTargetParser.h/cpp to TargetParser.h/cpp
• Added a few comments about TableGen

[rnk]

lgtm

include/llvm/Support/TargetParser.h

22 ↗

(On Diff #25304)

"generated"

[rengolin]

Thanks! r236900 with the typo fixed.

include/llvm/Support/ARMTargetParser.h

+//===-- ARMTargetParser - Parser for target features ------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a target parser to recognise hardware features such as
+// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_ARMTARGETPARSER_H
+#define LLVM_SUPPORT_ARMTARGETPARSER_H
+
+// SubtargetFeatureKV
+//#define GET_SUBTARGETINFO_MC_DESC
+//#include "ARMGenSubtargetInfo.inc"
+
+//namespace {
+//  class StringRef;
+//}
+
+namespace llvm {
+  class StringRef;
+
+namespace ARM {
+  // FPU names.
+  // FIXME: TableGen this.
+  enum FPUKind {
+    INVALID_FPU = 0,
+    VFP,
+    VFPV2,
+    VFPV3,
+    VFPV3_D16,
+    VFPV4,
+    VFPV4_D16,
+    FPV5_D16,
+    FP_ARMV8,
+    NEON,
+    NEON_VFPV4,
+    NEON_FP_ARMV8,
+    CRYPTO_NEON_FP_ARMV8,
+    SOFTVFP,
+    LAST_FPU
+  };
+
+  // Arch names.
+  // FIXME: TableGen this.
+  enum ArchKind {
+    INVALID_ARCH = 0,
+    ARMV2,
+    ARMV2A,
+    ARMV3,
+    ARMV3M,
+    ARMV4,
+    ARMV4T,
+    ARMV5,
+    ARMV5T,
+    ARMV5TE,
+    ARMV6,
+    ARMV6J,
+    ARMV6K,
+    ARMV6T2,
+    ARMV6Z,
+    ARMV6ZK,
+    ARMV6M,
+    ARMV7,
+    ARMV7A,
+    ARMV7R,
+    ARMV7M,
+    ARMV8A,
+    ARMV8_1A,
+    IWMMXT,
+    IWMMXT2,
+    LAST_ARCH
+  };
+
+  // Arch extension modifiers for CPUs.
+  // FIXME: TableGen this.
+  enum ArchExtKind {
+    INVALID_ARCHEXT = 0,
+    CRC,
+    CRYPTO,
+    FP,
+    HWDIV,
+    MP,
+    SEC,
+    VIRT,
+    LAST_ARCHEXT
+  };
+
+} // namespace ARM
+
+class ARMTargetParser {
+  static StringRef getFPUSynonim(StringRef FPU);
+  static StringRef getArchSynonim(StringRef Arch);
+
+public:
+  // Information by ID
+  static const char * getFPUName(unsigned ID);
+  static const char * getArchName(unsigned ID);
+  static unsigned getArchDefaultCPUArch(unsigned ID);
+  static const char * getArchDefaultCPUName(unsigned ID);
+  static const char * getArchExtName(unsigned ID);
+
+  // Parser
+  static unsigned parseFPU(StringRef FPU);
+  static unsigned parseArch(StringRef Arch);
+  static unsigned parseArchExt(StringRef ArchExt);
+};
+
+} // namespace llvm
+
+#endif
 No newline at end of file

lib/Support/ARMTargetParser.cpp

+//===-- ARMTargetParser - Parser for target features ------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a target parser to recognise hardware features such as
+// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/ARMBuildAttributes.h"
+#include "llvm/Support/ARMTargetParser.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+
+using namespace llvm;
+
+namespace {
+
+// List of canonical FPU names (use getFPUSynonym)
+// FIXME: TableGen this.
+struct {
+  const char * Name;
+  ARM::FPUKind ID;
+} FPUNames[] = {
+  { "invalid",              ARM::INVALID_FPU },
+  { "vfp",                  ARM::VFP },
+  { "vfpv2",                ARM::VFPV2 },
+  { "vfpv3",                ARM::VFPV3 },
+  { "vfpv3-d16",            ARM::VFPV3_D16 },
+  { "vfpv4",                ARM::VFPV4 },
+  { "vfpv4-d16",            ARM::VFPV4_D16 },
+  { "fpv5-d16",             ARM::FPV5_D16 },
+  { "fp-armv8",             ARM::FP_ARMV8 },
+  { "neon",                 ARM::NEON },
+  { "neon-vfpv4",           ARM::NEON_VFPV4 },
+  { "neon-fp-armv8",        ARM::NEON_FP_ARMV8 },
+  { "crypto-neon-fp-armv8", ARM::CRYPTO_NEON_FP_ARMV8 },
+  { "softvfp",              ARM::SOFTVFP }
+};
+// List of canonical arch names (use getArchSynonym)
+// FIXME: TableGen this.
+struct {
+  const char *Name;
+  ARM::ArchKind ID;
+  const char *DefaultCPU;
+  ARMBuildAttrs::CPUArch DefaultArch;
+} ARCHNames[] = {
+  { "invalid",   ARM::INVALID_ARCH, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
+  { "armv2",     ARM::ARMV2,    "2",       ARMBuildAttrs::CPUArch::v4 },
+  { "armv2a",    ARM::ARMV2A,   "2A",      ARMBuildAttrs::CPUArch::v4 },
+  { "armv3",     ARM::ARMV3,    "3",       ARMBuildAttrs::CPUArch::v4 },
+  { "armv3m",    ARM::ARMV3M,   "3M",      ARMBuildAttrs::CPUArch::v4 },
+  { "armv4",     ARM::ARMV4,    "4",       ARMBuildAttrs::CPUArch::v4 },
+  { "armv4t",    ARM::ARMV4T,   "4T",      ARMBuildAttrs::CPUArch::v4T },
+  { "armv5",     ARM::ARMV5,    "5",       ARMBuildAttrs::CPUArch::v5T },
+  { "armv5t",    ARM::ARMV5T,   "5T",      ARMBuildAttrs::CPUArch::v5T },
+  { "armv5te",   ARM::ARMV5TE,  "5TE",     ARMBuildAttrs::CPUArch::v5TE },
+  { "armv6",     ARM::ARMV6,    "6",       ARMBuildAttrs::CPUArch::v6 },
+  { "armv6j",    ARM::ARMV6J,   "6J",      ARMBuildAttrs::CPUArch::v6 },
+  { "armv6k",    ARM::ARMV6K,   "6K",      ARMBuildAttrs::CPUArch::v6K },
+  { "armv6t2",   ARM::ARMV6T2,  "6T2",     ARMBuildAttrs::CPUArch::v6T2 },
+  { "armv6z",    ARM::ARMV6Z,   "6Z",      ARMBuildAttrs::CPUArch::v6KZ },
+  { "armv6zk",   ARM::ARMV6ZK,  "6ZK",     ARMBuildAttrs::CPUArch::v6KZ },
+  { "armv6-m",   ARM::ARMV6M,   "6-M",     ARMBuildAttrs::CPUArch::v6_M },
+  { "armv7",     ARM::ARMV7,    "7",       ARMBuildAttrs::CPUArch::v7 },
+  { "armv7-a",   ARM::ARMV7A,   "7-A",     ARMBuildAttrs::CPUArch::v7 },
+  { "armv7-r",   ARM::ARMV7R,   "7-R",     ARMBuildAttrs::CPUArch::v7 },
+  { "armv7-m",   ARM::ARMV7M,   "7-M",     ARMBuildAttrs::CPUArch::v7 },
+  { "armv8-a",   ARM::ARMV8A,   "8-A",     ARMBuildAttrs::CPUArch::v8 },
+  { "armv8.1-a", ARM::ARMV8_1A, "8.1-A",   ARMBuildAttrs::CPUArch::v8 },
+  { "iwmmxt",    ARM::IWMMXT,   "iwmmxt",  ARMBuildAttrs::CPUArch::v5TE },
+  { "iwmmxt2",   ARM::IWMMXT2,  "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }
+};
+// List of canonical ARCH names (use getARCHSynonym)
+// FIXME: TableGen this.
+struct {
+  const char *Name;
+  ARM::ArchExtKind ID;
+} ARCHExtNames[] = {
+  { "invalid",  ARM::INVALID_ARCHEXT },
+  { "crc",      ARM::CRC },
+  { "crypto",   ARM::CRYPTO },
+  { "fp",       ARM::FP },
+  { "idiv",     ARM::HWDIV },
+  { "mp",       ARM::MP },
+  { "sec",      ARM::SEC },
+  { "virt",     ARM::VIRT }
+};
+
+} // namespace
+
+namespace llvm {
+
+// ======================================================= //
+// Information by ID
+// ======================================================= //
+
+const char *
+ARMTargetParser::
+getFPUName(unsigned ID) {
+  if (ID >= ARM::LAST_FPU)
+    return nullptr;
+  return FPUNames[ID].Name;
+}
+
+const char *
+ARMTargetParser::
+getArchName(unsigned ID) {
+  if (ID >= ARM::LAST_ARCH)
+    return nullptr;
+  return ARCHNames[ID].Name;
+}
+
+const char *
+ARMTargetParser::
+getArchDefaultCPUName(unsigned ID) {
+  if (ID >= ARM::LAST_ARCH)
+    return nullptr;
+  return ARCHNames[ID].DefaultCPU;
+}
+
+unsigned
+ARMTargetParser::
+getArchDefaultCPUArch(unsigned ID) {
+  if (ID >= ARM::LAST_ARCH)
+    return 0;
+  return ARCHNames[ID].DefaultArch;
+}
+
+const char *
+ARMTargetParser::
+getArchExtName(unsigned ID) {
+  if (ID >= ARM::LAST_ARCHEXT)
+    return nullptr;
+  return ARCHExtNames[ID].Name;
+}
+
+// ======================================================= //
+// Parsers
+// ======================================================= //
+
+StringRef
+ARMTargetParser::
+getFPUSynonim(StringRef FPU) {
+  return StringSwitch<StringRef>(FPU)
+    .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
+    .Case("vfp2", "vfpv2")
+    .Case("vfp3", "vfpv3")
+    .Case("vfp4", "vfpv4")
+    .Case("vfp3-d16", "vfpv3-d16")
+    .Case("vfp4-d16", "vfpv4-d16")
+    .Cases("fp4-sp-d16", "fpv4-sp-d16", "vfpv4-d16")
+    .Cases("fp5-sp-d16", "fpv5-sp-d16", "fpv5-d16")
+    .Case("fp5-dp-d16", "fpv5-d16")
+    .Default(FPU);
+}
+
+StringRef
+ARMTargetParser::
+getArchSynonim(StringRef Arch) {
+  return StringSwitch<StringRef>(Arch)
+    .Case("armv7a", "armv7-a")
+    .Case("armv7r", "armv7-r")
+    .Case("armv7m", "armv7-m")
+    .Case("armv8a", "armv8-a")
+    .Case("armv8.1a", "armv8.1-a")
+    .Default(Arch);
+}
+
+unsigned
+ARMTargetParser::
+parseFPU(StringRef FPU) {
+  StringRef Syn = getFPUSynonim(FPU);
+  for (const auto F : FPUNames) {
+    if (Syn == F.Name)
+      return F.ID;
+  }
+  return ARM::INVALID_FPU;
+}
+
+unsigned
+ARMTargetParser::
+parseArch(StringRef Arch) {
+  StringRef Syn = getArchSynonim(Arch);
+  for (const auto A : ARCHNames) {
+    if (Syn == A.Name)
+      return A.ID;
+  }
+  return ARM::INVALID_ARCH;
+}
+
+unsigned
+ARMTargetParser::
+parseArchExt(StringRef ArchExt) {
+  for (const auto A : ARCHExtNames) {
+    if (ArchExt == A.Name)
+      return A.ID;
+  }
+  return ARM::INVALID_ARCHEXT;
+}
+
+} // namespace llvm
 No newline at end of file

lib/Support/CMakeLists.txt

if( NOT MSVC )
   endif( MINGW )
 endif( NOT MSVC )
 
 add_llvm_library(LLVMSupport
   APFloat.cpp
   APInt.cpp
   APSInt.cpp
   ARMBuildAttrs.cpp
+  ARMTargetParser.cpp
   ARMWinEH.cpp
   Allocator.cpp
   BlockFrequency.cpp
   BranchProbability.cpp
   circular_raw_ostream.cpp
   COM.cpp
   CommandLine.cpp
   Compression.cpp

lib/Target/ARM/ARMArchExtName.h

-//===-- ARMArchExtName.h - List of the ARM Extension names ------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_ARM_ARMARCHEXTNAME_H
-#define LLVM_LIB_TARGET_ARM_ARMARCHEXTNAME_H
-
-namespace llvm {
-namespace ARM {
-
-enum ArchExtKind {
-  INVALID_ARCHEXT = 0
-
-#define ARM_ARCHEXT_NAME(NAME, ID) , ID
-#include "ARMArchExtName.def"
-};
-
-} // namespace ARM
-} // namespace llvm
-
-#endif

lib/Target/ARM/ARMArchExtName.def

-//===-- ARMArchExtName.def - List of the ARM Extension names ----*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the list of the supported ARM Architecture Extension
-// names. These can be used to enable the extension through .arch_extension
-// attribute
-//
-//===----------------------------------------------------------------------===//
-
-// NOTE: NO INCLUDE GUARD DESIRED!
-
-#ifndef ARM_ARCHEXT_NAME
-#error "You must define ARM_ARCHEXT_NAME(NAME, ID) before including ARMArchExtName.h"
-#endif
-
-ARM_ARCHEXT_NAME("crc", CRC)
-ARM_ARCHEXT_NAME("crypto", CRYPTO)
-ARM_ARCHEXT_NAME("fp", FP)
-ARM_ARCHEXT_NAME("idiv", HWDIV)
-ARM_ARCHEXT_NAME("mp", MP)
-ARM_ARCHEXT_NAME("sec", SEC)
-ARM_ARCHEXT_NAME("virt", VIRT)
-
-#undef ARM_ARCHEXT_NAME

lib/Target/ARM/ARMAsmPrinter.cpp

 // This file contains a printer that converts from our internal representation
 // of machine-dependent LLVM code to GAS-format ARM assembly language.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMAsmPrinter.h"
 #include "ARM.h"
 #include "ARMConstantPoolValue.h"
-#include "ARMFPUName.h"
-#include "ARMArchExtName.h"
 #include "ARMMachineFunctionInfo.h"
 #include "ARMTargetMachine.h"
 #include "ARMTargetObjectFile.h"
 #include "InstPrinter/ARMInstPrinter.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
 #include "MCTargetDesc/ARMMCExpr.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallString.h"

 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCObjectStreamer.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/ARMBuildAttributes.h"
+#include "llvm/Support/ARMTargetParser.h"
 #include "llvm/Support/COFF.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"

lib/Target/ARM/ARMFPUName.h

-//===-- ARMFPUName.h - List of the ARM FPU names ----------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_ARM_ARMFPUNAME_H
-#define LLVM_LIB_TARGET_ARM_ARMFPUNAME_H
-
-namespace llvm {
-namespace ARM {
-
-enum FPUKind {
-  INVALID_FPU = 0
-
-#define ARM_FPU_NAME(NAME, ID) , ID
-#include "ARMFPUName.def"
-};
-
-} // namespace ARM
-} // namespace llvm
-
-#endif

lib/Target/ARM/ARMFPUName.def

-//===-- ARMFPUName.def - List of the ARM FPU names --------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the list of the supported ARM FPU names.
-//
-//===----------------------------------------------------------------------===//
-
-// NOTE: NO INCLUDE GUARD DESIRED!
-
-#ifndef ARM_FPU_NAME
-#error "You must define ARM_FPU_NAME(NAME, ID) before including ARMFPUName.h"
-#endif
-
-ARM_FPU_NAME("vfp", VFP)
-ARM_FPU_NAME("vfpv2", VFPV2)
-ARM_FPU_NAME("vfpv3", VFPV3)
-ARM_FPU_NAME("vfpv3-d16", VFPV3_D16)
-ARM_FPU_NAME("vfpv4", VFPV4)
-ARM_FPU_NAME("vfpv4-d16", VFPV4_D16)
-ARM_FPU_NAME("fpv5-d16", FPV5_D16)
-ARM_FPU_NAME("fp-armv8", FP_ARMV8)
-ARM_FPU_NAME("neon", NEON)
-ARM_FPU_NAME("neon-vfpv4", NEON_VFPV4)
-ARM_FPU_NAME("neon-fp-armv8", NEON_FP_ARMV8)
-ARM_FPU_NAME("crypto-neon-fp-armv8", CRYPTO_NEON_FP_ARMV8)
-ARM_FPU_NAME("softvfp", SOFTVFP)
-
-#undef ARM_FPU_NAME

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
-#include "ARMFPUName.h"
 #include "ARMFeatures.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
-#include "MCTargetDesc/ARMArchName.h"
 #include "MCTargetDesc/ARMBaseInfo.h"
 #include "MCTargetDesc/ARMMCExpr.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAsmInfo.h"

 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSection.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MCTargetAsmParser.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/ARMEHABI.h"
+#include "llvm/Support/ARMTargetParser.h"
 #include "llvm/Support/COFF.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 

   return false;
 }
 
 /// parseDirectiveArch
 ///  ::= .arch token
 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
 
-  unsigned ID = StringSwitch<unsigned>(Arch)
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
-    .Case(NAME, ARM::ID)
-#define ARM_ARCH_ALIAS(NAME, ID) \
-    .Case(NAME, ARM::ID)
-#include "MCTargetDesc/ARMArchName.def"
-    .Default(ARM::INVALID_ARCH);
+  unsigned ID = ARMTargetParser::parseArch(Arch);
 
   if (ID == ARM::INVALID_ARCH) {
     Error(L, "Unknown arch name");
     return false;
   }
 
   getTargetStreamer().emitArch(ID);
   return false;

 };
 
 /// parseDirectiveFPU
 ///  ::= .fpu str
 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
   SMLoc FPUNameLoc = getTok().getLoc();
   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
 
-  unsigned ID = StringSwitch<unsigned>(FPU)
-#define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
-#include "ARMFPUName.def"
-    .Default(ARM::INVALID_FPU);
+  unsigned ID = ARMTargetParser::parseFPU(FPU);
 
   if (ID == ARM::INVALID_FPU) {
     Error(FPUNameLoc, "Unknown FPU name");
     return false;
   }
 
   for (const auto &Entry : FPUs) {
     if (Entry.ID != ID)

     Parser.eatToEndOfStatement();
     return false;
   }
 
   StringRef Arch = Parser.getTok().getString();
   SMLoc ArchLoc = Parser.getTok().getLoc();
   getLexer().Lex();
 
-  unsigned ID = StringSwitch<unsigned>(Arch)
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
-    .Case(NAME, ARM::ID)
-#define ARM_ARCH_ALIAS(NAME, ID) \
-    .Case(NAME, ARM::ID)
-#include "MCTargetDesc/ARMArchName.def"
-#undef ARM_ARCH_NAME
-#undef ARM_ARCH_ALIAS
-    .Default(ARM::INVALID_ARCH);
+  unsigned ID = ARMTargetParser::parseArch(Arch);
 
   if (ID == ARM::INVALID_ARCH) {
     Error(ArchLoc, "unknown architecture '" + Arch + "'");
     Parser.eatToEndOfStatement();
     return false;
   }
 
   getTargetStreamer().emitObjectArch(ID);

lib/Target/ARM/MCTargetDesc/ARMArchName.h

-//===-- ARMArchName.h - List of the ARM arch names --------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMARCHNAME_H
-#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMARCHNAME_H
-
-namespace llvm {
-namespace ARM {
-
-enum ArchKind {
-  INVALID_ARCH = 0
-
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) , ID
-#define ARM_ARCH_ALIAS(NAME, ID) /* empty */
-#include "ARMArchName.def"
-};
-
-} // namespace ARM
-} // namespace llvm
-
-#endif

lib/Target/ARM/MCTargetDesc/ARMArchName.def

-//===-- ARMArchName.def - List of the ARM arch names ------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the list of the supported ARM architecture names,
-// i.e. the supported value for -march= option.
-//
-//===----------------------------------------------------------------------===//
-
-// NOTE: NO INCLUDE GUARD DESIRED!
-
-#ifndef ARM_ARCH_NAME
-#error "You must define ARM_ARCH_NAME before including ARMArchName.def"
-#endif
-
-// ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH)
-ARM_ARCH_NAME("armv2",   ARMV2,   "2",       v4)
-ARM_ARCH_NAME("armv2a",  ARMV2A,  "2A",      v4)
-ARM_ARCH_NAME("armv3",   ARMV3,   "3",       v4)
-ARM_ARCH_NAME("armv3m",  ARMV3M,  "3M",      v4)
-ARM_ARCH_NAME("armv4",   ARMV4,   "4",       v4)
-ARM_ARCH_NAME("armv4t",  ARMV4T,  "4T",      v4T)
-ARM_ARCH_NAME("armv5",   ARMV5,   "5",       v5T)
-ARM_ARCH_NAME("armv5t",  ARMV5T,  "5T",      v5T)
-ARM_ARCH_NAME("armv5te", ARMV5TE, "5TE",     v5TE)
-ARM_ARCH_NAME("armv6",   ARMV6,   "6",       v6)
-ARM_ARCH_NAME("armv6j",  ARMV6J,  "6J",      v6)
-ARM_ARCH_NAME("armv6k",  ARMV6K,  "6K",      v6K)
-ARM_ARCH_NAME("armv6t2", ARMV6T2, "6T2",     v6T2)
-ARM_ARCH_NAME("armv6z",  ARMV6Z,  "6Z",      v6KZ)
-ARM_ARCH_NAME("armv6zk", ARMV6ZK, "6ZK",     v6KZ)
-ARM_ARCH_NAME("armv6-m", ARMV6M,  "6-M",     v6_M)
-ARM_ARCH_NAME("armv7",   ARMV7,   "7",       v7)
-ARM_ARCH_NAME("armv7-a", ARMV7A,  "7-A",     v7)
-ARM_ARCH_ALIAS("armv7a", ARMV7A)
-ARM_ARCH_NAME("armv7-r", ARMV7R,  "7-R",     v7)
-ARM_ARCH_ALIAS("armv7r", ARMV7R)
-ARM_ARCH_NAME("armv7-m", ARMV7M,  "7-M",     v7)
-ARM_ARCH_ALIAS("armv7m", ARMV7M)
-ARM_ARCH_NAME("armv8-a", ARMV8A,  "8-A",     v8)
-ARM_ARCH_ALIAS("armv8a", ARMV8A)
-ARM_ARCH_NAME("armv8.1-a", ARMV8_1A, "8.1-A", v8)
-ARM_ARCH_ALIAS("armv8.1a", ARMV8_1A)
-ARM_ARCH_NAME("iwmmxt",  IWMMXT,  "iwmmxt",  v5TE)
-ARM_ARCH_NAME("iwmmxt2", IWMMXT2, "iwmmxt2", v5TE)
-
-#undef ARM_ARCH_NAME
-#undef ARM_ARCH_ALIAS

lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp

 //===- lib/MC/ARMELFStreamer.cpp - ELF Object Output for ARM --------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file assembles .s files and emits ARM ELF .o object files. Different
 // from generic ELF streamer in emitting mapping symbols ($a, $t and $d) to
 // delimit regions of data and code.
 //
 //===----------------------------------------------------------------------===//
 
-#include "ARMArchName.h"
-#include "ARMFPUName.h"
-#include "ARMArchExtName.h"
 #include "ARMRegisterInfo.h"
 #include "ARMUnwindOpAsm.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCAssembler.h"
 #include "llvm/MC/MCCodeEmitter.h"

 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSection.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MCValue.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/ARMEHABI.h"
+#include "llvm/Support/ARMTargetParser.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ELF.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/LEB128.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 
 using namespace llvm;
 
 static std::string GetAEABIUnwindPersonalityName(unsigned Index) {
   assert(Index < ARM::EHABI::NUM_PERSONALITY_INDEX &&
          "Invalid personality index");
   return (Twine("__aeabi_unwind_cpp_pr") + Twine(Index)).str();
 }
 
-static const char *GetFPUName(unsigned ID) {
-  switch (ID) {
-  default:
-    llvm_unreachable("Unknown FPU kind");
-    break;
-#define ARM_FPU_NAME(NAME, ID) case ARM::ID: return NAME;
-#include "ARMFPUName.def"
-  }
-  return nullptr;
-}
-
-static const char *GetArchName(unsigned ID) {
-  switch (ID) {
-  default:
-    llvm_unreachable("Unknown ARCH kind");
-    break;
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
-  case ARM::ID: return NAME;
-#define ARM_ARCH_ALIAS(NAME, ID) /* empty */
-#include "ARMArchName.def"
-  }
-  return nullptr;
-}
-
-static const char *GetArchDefaultCPUName(unsigned ID) {
-  switch (ID) {
-  default:
-    llvm_unreachable("Unknown ARCH kind");
-    break;
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
-  case ARM::ID: return DEFAULT_CPU_NAME;
-#define ARM_ARCH_ALIAS(NAME, ID) /* empty */
-#include "ARMArchName.def"
-  }
-  return nullptr;
-}
-
-static unsigned GetArchDefaultCPUArch(unsigned ID) {
-  switch (ID) {
-  default:
-    llvm_unreachable("Unknown ARCH kind");
-    break;
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
-  case ARM::ID: return ARMBuildAttrs::DEFAULT_CPU_ARCH;
-#define ARM_ARCH_ALIAS(NAME, ID) /* empty */
-#include "ARMArchName.def"
-  }
-  return 0;
-}
-
-static const char *GetArchExtName(unsigned ID) {
-  switch (ID) {
-  default:
-    llvm_unreachable("Unknown ARCH Extension kind");
-    break;
-#define ARM_ARCHEXT_NAME(NAME, ID)                                             \
-  case ARM::ID:                                                                \
-    return NAME;
-#include "ARMArchExtName.def"
-  }
-  return nullptr;
-}
-
 namespace {
 
 class ARMELFStreamer;
 
 class ARMTargetAsmStreamer : public ARMTargetStreamer {
   formatted_raw_ostream &OS;
   MCInstPrinter &InstPrinter;
   bool IsVerboseAsm;
if (!StringValue.empty())
       OS << ", \"" << StringValue << "\"";
     if (IsVerboseAsm)
       OS << "\t@ " << ARMBuildAttrs::AttrTypeAsString(Attribute);
     break;
   }
   OS << "\n";
 }
 void ARMTargetAsmStreamer::emitArch(unsigned Arch) {
-  OS << "\t.arch\t" << GetArchName(Arch) << "\n";
+  OS << "\t.arch\t" << ARMTargetParser::getArchName(Arch) << "\n";
 }
 void ARMTargetAsmStreamer::emitArchExtension(unsigned ArchExt) {
-  OS << "\t.arch_extension\t" << GetArchExtName(ArchExt) << "\n";
+  OS << "\t.arch_extension\t" << ARMTargetParser::getArchExtName(ArchExt) << "\n";
 }
 void ARMTargetAsmStreamer::emitObjectArch(unsigned Arch) {
-  OS << "\t.object_arch\t" << GetArchName(Arch) << '\n';
+  OS << "\t.object_arch\t" << ARMTargetParser::getArchName(Arch) << '\n';
 }
 void ARMTargetAsmStreamer::emitFPU(unsigned FPU) {
-  OS << "\t.fpu\t" << GetFPUName(FPU) << "\n";
+  OS << "\t.fpu\t" << ARMTargetParser::getFPUName(FPU) << "\n";
 }
 void ARMTargetAsmStreamer::finishAttributeSection() {
 }
 void
 ARMTargetAsmStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *S) {
   OS << "\t.tlsdescseq\t" << S->getSymbol().getName();
 }
 
void ARMTargetELFStreamer::emitArch(unsigned Value) {
   Arch = Value;
 }
 void ARMTargetELFStreamer::emitObjectArch(unsigned Value) {
   EmittedArch = Value;
 }
 void ARMTargetELFStreamer::emitArchDefaultAttributes() {
   using namespace ARMBuildAttrs;
 
-  setAttributeItem(CPU_name, GetArchDefaultCPUName(Arch), false);
+  setAttributeItem(CPU_name,
+                   ARMTargetParser::getArchDefaultCPUName(Arch),
+                   false);
+
   if (EmittedArch == ARM::INVALID_ARCH)
-    setAttributeItem(CPU_arch, GetArchDefaultCPUArch(Arch), false);
+    setAttributeItem(CPU_arch,
+                     ARMTargetParser::getArchDefaultCPUArch(Arch),
+                     false);
   else
-    setAttributeItem(CPU_arch, GetArchDefaultCPUArch(EmittedArch), false);
+    setAttributeItem(CPU_arch,
+                     ARMTargetParser::getArchDefaultCPUArch(EmittedArch),
+                     false);
 
   switch (Arch) {
   case ARM::ARMV2:
   case ARM::ARMV2A:
   case ARM::ARMV3:
   case ARM::ARMV3M:
   case ARM::ARMV4:
   case ARM::ARMV5: