[SelectionDAGBuilder] Update signature of `getRegsAndSizes()`.

[joechrisellis]

Summary

The mapping between registers and relative size has been updated to
use TypeSize to account for the size of scalable EVTs.

The patch is a NFCI, if not for the fact that with this change the
function getUnderlyingArgRegs does not raise a warning for implicit
conversion of TypeSize to unsigned when generating machine code
from the test added to the patch.

[fpetrogalli]

Fix formatting in test. NFC

[arsenm]

Test name should be more descriptive

llvm/test/CodeGen/AArch64/reproducer.ll

23

Is all the debug info really necessary?

[fpetrogalli]

Rename test file. NFC.

[fpetrogalli]

llvm/test/CodeGen/AArch64/reproducer.ll

23

I removed as much as I could, anything less than this seems to make llc unhappy.

[fpetrogalli]

NFC: fix code formatting.

[fpetrogalli]

NFC. Rename declare in test.

[arsenm]

llvm/test/CodeGen/AArch64/sdag-no-typesize-warnings-regandsizes.ll

24 ↗

(On Diff #308066)

This is removable

33 ↗

(On Diff #308066)

It is possible to hack on the fields here but it's a pain

[joechrisellis]

Eliminate superfluous debug info from test.

[joechrisellis]

Hi @arsenm, I am finishing up this patch. 😄

I've reduced the debug info where possible. Will assume that you're happy with this small change and will push tomorrow, probably. Let me know otherwise!

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

void AddInlineAsmOperands(unsigned Code, bool HasMatching,
                             SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
 
   /// Check if the total RegCount is greater than one.
   bool occupiesMultipleRegs() const {
     return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1;
   }
 
   /// Return a list of registers and their sizes.
-  SmallVector<std::pair<unsigned, unsigned>, 4> getRegsAndSizes() const;
+  SmallVector<std::pair<unsigned, TypeSize>, 4> getRegsAndSizes() const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
     for (unsigned i = 0; i != NumRegs; ++i) {
       assert(Reg < Regs.size() && "Mismatch in # registers expected");
       unsigned TheReg = Regs[Reg++];
       Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
     }
   }
 }
 
-SmallVector<std::pair<unsigned, unsigned>, 4>
+SmallVector<std::pair<unsigned, TypeSize>, 4>
 RegsForValue::getRegsAndSizes() const {
-  SmallVector<std::pair<unsigned, unsigned>, 4> OutVec;
+  SmallVector<std::pair<unsigned, TypeSize>, 4> OutVec;
   unsigned I = 0;
   for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
     unsigned RegCount = std::get<0>(CountAndVT);
     MVT RegisterVT = std::get<1>(CountAndVT);
-    unsigned RegisterSize = RegisterVT.getSizeInBits();
+    TypeSize RegisterSize = RegisterVT.getSizeInBits();
     for (unsigned E = I + RegCount; I != E; ++I)
       OutVec.push_back(std::make_pair(Regs[I], RegisterSize));
   }
   return OutVec;
 }
 
 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa,
                                const TargetLibraryInfo *li) {
static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL,
   }
 
   return DAG.getNode(Opcode, DL, VT, LHS, RHS, Scale);
 }
 
 // getUnderlyingArgRegs - Find underlying registers used for a truncated,
 // bitcasted, or split argument. Returns a list of <Register, size in bits>
 static void
-getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
+getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, TypeSize>> &Regs,
                      const SDValue &N) {
   switch (N.getOpcode()) {
   case ISD::CopyFromReg: {
     SDValue Op = N.getOperand(1);
     Regs.emplace_back(cast<RegisterSDNode>(Op)->getReg(),
                       Op.getValueType().getSizeInBits());
     return;
   }
bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
 
   bool IsIndirect = false;
   Optional<MachineOperand> Op;
   // Some arguments' frame index is recorded during argument lowering.
   int FI = FuncInfo.getArgumentFrameIndex(Arg);
   if (FI != std::numeric_limits<int>::max())
     Op = MachineOperand::CreateFI(FI);
 
-  SmallVector<std::pair<unsigned, unsigned>, 8> ArgRegsAndSizes;
+  SmallVector<std::pair<unsigned, TypeSize>, 8> ArgRegsAndSizes;
   if (!Op && N.getNode()) {
     getUnderlyingArgRegs(ArgRegsAndSizes, N);
     Register Reg;
     if (ArgRegsAndSizes.size() == 1)
       Reg = ArgRegsAndSizes.front().first;
 
     if (Reg && Reg.isVirtual()) {
       MachineRegisterInfo &RegInfo = MF.getRegInfo();
if (!Op && N.getNode()) {
     if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(LCandidate.getNode()))
       if (FrameIndexSDNode *FINode =
           dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
         Op = MachineOperand::CreateFI(FINode->getIndex());
   }
 
   if (!Op) {
     // Create a DBG_VALUE for each decomposed value in ArgRegs to cover Reg
-    auto splitMultiRegDbgValue
-      = [&](ArrayRef<std::pair<unsigned, unsigned>> SplitRegs) {
+    auto splitMultiRegDbgValue = [&](
+        ArrayRef<std::pair<unsigned, TypeSize>> SplitRegs) {
       unsigned Offset = 0;
       for (auto RegAndSize : SplitRegs) {
         // If the expression is already a fragment, the current register
         // offset+size might extend beyond the fragment. In this case, only
         // the register bits that are inside the fragment are relevant.
         int RegFragmentSizeInBits = RegAndSize.second;
         if (auto ExprFragmentInfo = Expr->getFragmentInfo()) {
           uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits;

llvm/test/CodeGen/AArch64/reproducer.ll

+; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; If this check fails please read
+; clang/test/CodeGen/aarch64-sve-intrinsics/README for instructions on
+; how to resolve it.
+
+; WARN-NOT: warning
+
+; CHECK-LABEL: do_something:
+define <vscale x 2 x double> @do_something(<vscale x 2 x double> %vx) {
+entry:
+  call void @llvm.dbg.value(metadata <vscale x 2 x double> %vx, metadata !6, metadata !DIExpression()), !dbg !19
+    %0 = tail call <vscale x 2 x double> @xxx(<vscale x 2 x double> %vx)
+      ret <vscale x 2 x double> %0
+      }
+
+declare <vscale x 2 x double> @xxx(<vscale x 2 x double>)
+
+; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4}
+!llvm.ident = !{!5}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "file.c", directory: "/")
+!2 = !{}
+!3 = !{i32 7, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{!"clang version 12.0.0"}
+!6 = !DILocalVariable(name: "vx", arg: 1, scope: !7, file: !1, line: 3, type: !10)
+!7 = distinct !DISubprogram(name: "do_something", scope: !1, file: !1, line: 3, type: !8, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !17)
+!8 = !DISubroutineType(types: !9)
+!9 = !{!10}
+!10 = !DIDerivedType(tag: DW_TAG_typedef, name: "svfloat64_t", file: !11, line: 56, baseType: !12)
+!11 = !DIFile(filename: "arm_sve.h", directory: "/")
+!12 = !DIDerivedType(tag: DW_TAG_typedef, name: "__SVFloat64_t", file: !1, baseType: !13)
+!13 = !DICompositeType(tag: DW_TAG_array_type, baseType: !14, flags: DIFlagVector, elements: !15)
+!14 = !DIBasicType(name: "double", size: 64, encoding: DW_ATE_float)
+!15 = !{!16}
+!16 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus))
+!17 = !{!6, !18}
+!18 = !DILocalVariable(name: "vout", scope: !7, file: !1, line: 4, type: !10)
+!19 = !DILocation(line: 0, scope: !7)