[MC][ARM] Fix number of operands of tMOVSr

[dmgreen]

Thanks for splitting this out. LGTM

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

case ARM::t2MOVr:
     // request the 32-bit variant, transform it here.
     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
         isARMLowRegister(Inst.getOperand(1).getReg()) &&
         Inst.getOperand(2).getImm() == ARMCC::AL &&
         Inst.getOperand(4).getReg() == ARM::CPSR &&
         !HasWideQualifier) {
       // The operands aren't the same for tMOV[S]r... (no cc_out)
       MCInst TmpInst;
-      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
+      unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr;
+      TmpInst.setOpcode(Op);
       TmpInst.addOperand(Inst.getOperand(0));
       TmpInst.addOperand(Inst.getOperand(1));
+      if (Op == ARM::tMOVr) {
         TmpInst.addOperand(Inst.getOperand(2));
         TmpInst.addOperand(Inst.getOperand(3));
+      }
       Inst = TmpInst;
       return true;
     }
     break;
 
   case ARM::t2SXTH:
   case ARM::t2SXTB:
   case ARM::t2UXTH:

llvm/test/MC/ARM/tMOVSr.s

+@ REQUIRES: asserts
+@ RUN: llvm-mc --triple=thumbv8 --debug %s 2>&1 | FileCheck %s --match-full-lines
+
+@ CHECK: Changed to: <MCInst #{{[0-9]+}} tMOVSr <MCOperand Reg:{{[0-9]+}}> <MCOperand Reg:{{[0-9]+}}>>
+.text
+  movs r2, r3