[lldb] [debugserver] Add stN aliases for stmmN for compatibility

[mgorny]

Summary

Add stN aliases for the FPU (stmmN) registers on MacOSX. This should
improve compatibility between MacOSX and other platforms, and fix
x86*-fp-write tests without having to duplicate them.

[labath]

Thanks for doing this. The changes look pretty straight-forward.

The main thing I think is missing here is the shelltest equivalent of @skipIfOutOfTreeDebugserver -- most people build/test lldb with the system debug server (because, reasons...) and so the test will still fail in those configurations...

[mgorny]

Added aliases to all regsets, not just the first ones. Updated test status.

amd64 tests still fail due to missing fip/fdp. I wonder how hard would it be to port it to Darwin.

[labath]

Still looks good to me. :) Jason, do you have any concerns?

Unfortunately, we still need a @skipIfOutOfTreeDebugserver equivalent....

[mgorny]

Rebase and fix TestRegisters.

[mgorny]

In D91847#2410564, @labath wrote:

Still looks good to me. :) Jason, do you have any concerns?

Unfortunately, we still need a @skipIfOutOfTreeDebugserver equivalent....

Long term, probably yes. Short term, the tests are broken again because of ftag changes, so I think we can get away without it.

That said, I need to test this more. I'll also try running tests with out-of-tree debugserver to see if anything else fails.

[krytarowski]

I would mark stmmX as an alias to stX and keep stX as the default for all platforms. stmmX could be an alias for everybody for legacy reasons.

[mgorny]

Added system-debugserver feature to skip tests.

[labath]

I think this is fine -- sorry this dropped off my radar.

@jasonmolenda, do you have any thoughts about this?

[labath]

In D91847#2410723, @krytarowski wrote:

I would mark stmmX as an alias to stX and keep stX as the default for all platforms. stmmX could be an alias for everybody for legacy reasons.

Possibly. Though we could also do that later, as the next step towards total deprecation...

[mgorny]

I suppose this has waited long enough to deserve another test run.

lldb/test/API/commands/register/register/register_command/TestRegisters.py

def fp_register_write(self):
                 ("ftw", "0x0000ff0e", False),
                 ("ip", "0x0000ff0e", False),
                 ("dp", "0x0000ff0e", False),
                 ("mxcsr", "0x0000ff0e", False),
                 ("mxcsrmask", "0x0000ff0e", False),
             ]
 
             st0regname = None
-            if currentFrame.FindRegister("st0").IsValid():
-                st0regname = "st0"
-            elif currentFrame.FindRegister("stmm0").IsValid():
+            # Darwin is using stmmN by default but support stN as an alias.
+            # Therefore, we need to check for stmmN first.
+            if currentFrame.FindRegister("stmm0").IsValid():
                 st0regname = "stmm0"
+            elif currentFrame.FindRegister("st0").IsValid():
+                st0regname = "st0"
             if st0regname is not None:
                 # reg          value
                 # must-have
                 reg_list.append(
                     (st0regname, "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00}", True))
                 reg_list.append(
                     ("xmm0",
                      "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}",

lldb/test/CMakeLists.txt

 # These values are not canonicalized within LLVM.
 llvm_canonicalize_cmake_booleans(
   LLDB_BUILD_INTEL_PT
   LLDB_ENABLE_PYTHON
   LLDB_ENABLE_LUA
   LLDB_ENABLE_LZMA
   LLVM_ENABLE_ZLIB
   LLVM_ENABLE_SHARED_LIBS
+  LLDB_USE_SYSTEM_DEBUGSERVER
   LLDB_IS_64_BITS)
 
 # Configure the individual test suites.
 add_subdirectory(API)
 add_subdirectory(Shell)
 add_subdirectory(Unit)
 
 # Configure the top level test suite.

lldb/test/Shell/Register/x86-multithread-write.test

 # XFAIL: system-windows
-# XFAIL: system-darwin
 # REQUIRES: native && (target-x86 || target-x86_64)
+# UNSUPPORTED: system-debugserver
 # RUN: %clangxx_host %p/Inputs/x86-multithread-write.cpp -o %t -pthread
 # RUN: %lldb -b -s %s %t | FileCheck %s
 
 process launch
 # CHECK: Process {{[0-9]+}} stopped
 
 register write eax 0x05060708
 register write ebx 0x15161718

lldb/test/Shell/lit.cfg.py

if config.lldb_enable_lua:
     config.available_features.add('lua')
 
 if config.lldb_enable_lzma:
     config.available_features.add('lzma')
 
 if find_executable('xz') != None:
     config.available_features.add('xz')
 
+if config.lldb_system_debugserver:
+    config.available_features.add('system-debugserver')
+
 # NetBSD permits setting dbregs either if one is root
 # or if user_set_dbregs is enabled
 can_set_dbregs = True
 if platform.system() == 'NetBSD' and os.geteuid() != 0:
     try:
         output = subprocess.check_output(["/sbin/sysctl", "-n",
           "security.models.extensions.user_set_dbregs"]).decode().strip()
         if output != "1":
             can_set_dbregs = False
     except subprocess.CalledProcessError:
         can_set_dbregs = False
 if can_set_dbregs:
     config.available_features.add('dbregs-set')
 
 # pass control variable through
 llvm_config.with_system_environment('FREEBSD_LEGACY_PLUGIN')

lldb/test/Shell/lit.site.cfg.py.in

 config.python_executable = "@Python3_EXECUTABLE@"
 config.have_zlib = @LLVM_ENABLE_ZLIB@
 config.lldb_enable_lzma = @LLDB_ENABLE_LZMA@
 config.host_triple = "@LLVM_HOST_TRIPLE@"
 config.lldb_bitness = 64 if @LLDB_IS_64_BITS@ else 32
 config.lldb_enable_python = @LLDB_ENABLE_PYTHON@
 config.lldb_enable_lua = @LLDB_ENABLE_LUA@
 config.lldb_build_directory = "@LLDB_TEST_BUILD_DIRECTORY@"
+config.lldb_system_debugserver = @LLDB_USE_SYSTEM_DEBUGSERVER@
 # The shell tests use their own module caches.
 config.lldb_module_cache = os.path.join("@LLDB_TEST_MODULE_CACHE_LLDB@", "lldb-shell")
 config.clang_module_cache = os.path.join("@LLDB_TEST_MODULE_CACHE_CLANG@", "lldb-shell")
 
 # Support substitution of the tools and libs dirs with user parameters. This is
 # used when we can't determine the tool dir at configuration time.
 try:
     config.llvm_tools_dir = config.llvm_tools_dir % lit_config.params

lldb/tools/debugserver/source/MacOSX/i386/DNBArchImplI386.cpp

const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_no_avx[] = {
      INVALID_NUB_REGNUM, NULL, NULL},
     {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
      FPU_OFFSET(mxcsr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
     {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
      FPU_SIZE_UINT(mxcsrmask), FPU_OFFSET(mxcsrmask), INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
 
-    {e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0,
      INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
-    {e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1,
      INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
-    {e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2,
      INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
-    {e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3,
      INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
-    {e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4,
      INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
-    {e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5,
      INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
-    {e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6,
      INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
-    {e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7,
      INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
 
     {e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8,
      FPU_SIZE_XMM(xmm0), FPU_OFFSET(xmm0), INVALID_NUB_REGNUM, dwarf_xmm0,
      INVALID_NUB_REGNUM, debugserver_xmm0, NULL, NULL},
     {e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8,
      FPU_SIZE_XMM(xmm1), FPU_OFFSET(xmm1), INVALID_NUB_REGNUM, dwarf_xmm1,
const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_avx[] = {
      INVALID_NUB_REGNUM, NULL, NULL},
     {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
      AVX_OFFSET(mxcsr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
     {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
      FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
 
-    {e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0,
      INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
-    {e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1,
      INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
-    {e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2,
      INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
-    {e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3,
      INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
-    {e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4,
      INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
-    {e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5,
      INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
-    {e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6,
      INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
-    {e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7,
      INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
 
     {e_regSetFPU, fpu_ymm0, "ymm0", NULL, Vector, VectorOfUInt8,
      FPU_SIZE_YMM(ymm0), AVX_OFFSET_YMM(0), INVALID_NUB_REGNUM, dwarf_ymm0,
      INVALID_NUB_REGNUM, debugserver_ymm0, NULL, NULL},
     {e_regSetFPU, fpu_ymm1, "ymm1", NULL, Vector, VectorOfUInt8,
      FPU_SIZE_YMM(ymm1), AVX_OFFSET_YMM(1), INVALID_NUB_REGNUM, dwarf_ymm1,
const DNBRegisterInfo DNBArchImplI386::g_fpu_registers_avx512f[] = {
      INVALID_NUB_REGNUM, NULL, NULL},
     {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
      AVX_OFFSET(mxcsr), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
     {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
      FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), INVALID_NUB_REGNUM,
      INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, NULL, NULL},
 
-    {e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), INVALID_NUB_REGNUM, dwarf_stmm0,
      INVALID_NUB_REGNUM, debugserver_stmm0, NULL, NULL},
-    {e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), INVALID_NUB_REGNUM, dwarf_stmm1,
      INVALID_NUB_REGNUM, debugserver_stmm1, NULL, NULL},
-    {e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), INVALID_NUB_REGNUM, dwarf_stmm2,
      INVALID_NUB_REGNUM, debugserver_stmm2, NULL, NULL},
-    {e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), INVALID_NUB_REGNUM, dwarf_stmm3,
      INVALID_NUB_REGNUM, debugserver_stmm3, NULL, NULL},
-    {e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), INVALID_NUB_REGNUM, dwarf_stmm4,
      INVALID_NUB_REGNUM, debugserver_stmm4, NULL, NULL},
-    {e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), INVALID_NUB_REGNUM, dwarf_stmm5,
      INVALID_NUB_REGNUM, debugserver_stmm5, NULL, NULL},
-    {e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), INVALID_NUB_REGNUM, dwarf_stmm6,
      INVALID_NUB_REGNUM, debugserver_stmm6, NULL, NULL},
-    {e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), INVALID_NUB_REGNUM, dwarf_stmm7,
      INVALID_NUB_REGNUM, debugserver_stmm7, NULL, NULL},
 
     AVX512_K_REG_DEF(0),
     AVX512_K_REG_DEF(1),
     AVX512_K_REG_DEF(2),
     AVX512_K_REG_DEF(3),
     AVX512_K_REG_DEF(4),

lldb/tools/debugserver/source/MacOSX/x86_64/DNBArchImplX86_64.cpp

const DNBRegisterInfo DNBArchImplX86_64::g_fpu_registers_no_avx[] = {
     {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
      FPU_OFFSET(ds), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
      FPU_OFFSET(mxcsr), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
      FPU_SIZE_UINT(mxcsrmask), FPU_OFFSET(mxcsrmask), -1U, -1U, -1U, -1U, NULL,
      NULL},
 
-    {e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), ehframe_dwarf_stmm0,
      ehframe_dwarf_stmm0, -1U, debugserver_stmm0, NULL, NULL},
-    {e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), ehframe_dwarf_stmm1,
      ehframe_dwarf_stmm1, -1U, debugserver_stmm1, NULL, NULL},
-    {e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), ehframe_dwarf_stmm2,
      ehframe_dwarf_stmm2, -1U, debugserver_stmm2, NULL, NULL},
-    {e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), ehframe_dwarf_stmm3,
      ehframe_dwarf_stmm3, -1U, debugserver_stmm3, NULL, NULL},
-    {e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), ehframe_dwarf_stmm4,
      ehframe_dwarf_stmm4, -1U, debugserver_stmm4, NULL, NULL},
-    {e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), ehframe_dwarf_stmm5,
      ehframe_dwarf_stmm5, -1U, debugserver_stmm5, NULL, NULL},
-    {e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), ehframe_dwarf_stmm6,
      ehframe_dwarf_stmm6, -1U, debugserver_stmm6, NULL, NULL},
-    {e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), ehframe_dwarf_stmm7,
      ehframe_dwarf_stmm7, -1U, debugserver_stmm7, NULL, NULL},
 
     {e_regSetFPU, fpu_xmm0, "xmm0", NULL, Vector, VectorOfUInt8,
      FPU_SIZE_XMM(xmm0), FPU_OFFSET(xmm0), ehframe_dwarf_xmm0,
      ehframe_dwarf_xmm0, -1U, debugserver_xmm0, NULL, NULL},
     {e_regSetFPU, fpu_xmm1, "xmm1", NULL, Vector, VectorOfUInt8,
      FPU_SIZE_XMM(xmm1), FPU_OFFSET(xmm1), ehframe_dwarf_xmm1,
const DNBRegisterInfo DNBArchImplX86_64::g_fpu_registers_avx[] = {
     {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
      AVX_OFFSET(ds), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
      AVX_OFFSET(mxcsr), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
      FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), -1U, -1U, -1U, -1U, NULL,
      NULL},
 
-    {e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), ehframe_dwarf_stmm0,
      ehframe_dwarf_stmm0, -1U, debugserver_stmm0, NULL, NULL},
-    {e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), ehframe_dwarf_stmm1,
      ehframe_dwarf_stmm1, -1U, debugserver_stmm1, NULL, NULL},
-    {e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), ehframe_dwarf_stmm2,
      ehframe_dwarf_stmm2, -1U, debugserver_stmm2, NULL, NULL},
-    {e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), ehframe_dwarf_stmm3,
      ehframe_dwarf_stmm3, -1U, debugserver_stmm3, NULL, NULL},
-    {e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), ehframe_dwarf_stmm4,
      ehframe_dwarf_stmm4, -1U, debugserver_stmm4, NULL, NULL},
-    {e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), ehframe_dwarf_stmm5,
      ehframe_dwarf_stmm5, -1U, debugserver_stmm5, NULL, NULL},
-    {e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), ehframe_dwarf_stmm6,
      ehframe_dwarf_stmm6, -1U, debugserver_stmm6, NULL, NULL},
-    {e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), ehframe_dwarf_stmm7,
      ehframe_dwarf_stmm7, -1U, debugserver_stmm7, NULL, NULL},
 
     {e_regSetFPU, fpu_ymm0, "ymm0", NULL, Vector, VectorOfUInt8,
      FPU_SIZE_YMM(ymm0), AVX_OFFSET_YMM(0), ehframe_dwarf_ymm0,
      ehframe_dwarf_ymm0, -1U, debugserver_ymm0, NULL, NULL},
     {e_regSetFPU, fpu_ymm1, "ymm1", NULL, Vector, VectorOfUInt8,
      FPU_SIZE_YMM(ymm1), AVX_OFFSET_YMM(1), ehframe_dwarf_ymm1,
const DNBRegisterInfo DNBArchImplX86_64::g_fpu_registers_avx512f[] = {
     {e_regSetFPU, fpu_ds, "foseg", NULL, Uint, Hex, FPU_SIZE_UINT(ds),
      AVX_OFFSET(ds), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_mxcsr, "mxcsr", NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr),
      AVX_OFFSET(mxcsr), -1U, -1U, -1U, -1U, NULL, NULL},
     {e_regSetFPU, fpu_mxcsrmask, "mxcsrmask", NULL, Uint, Hex,
      FPU_SIZE_UINT(mxcsrmask), AVX_OFFSET(mxcsrmask), -1U, -1U, -1U, -1U, NULL,
      NULL},
 
-    {e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm0, "stmm0", "st0", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), ehframe_dwarf_stmm0,
      ehframe_dwarf_stmm0, -1U, debugserver_stmm0, NULL, NULL},
-    {e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm1, "stmm1", "st1", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), ehframe_dwarf_stmm1,
      ehframe_dwarf_stmm1, -1U, debugserver_stmm1, NULL, NULL},
-    {e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm2, "stmm2", "st2", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), ehframe_dwarf_stmm2,
      ehframe_dwarf_stmm2, -1U, debugserver_stmm2, NULL, NULL},
-    {e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm3, "stmm3", "st3", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), ehframe_dwarf_stmm3,
      ehframe_dwarf_stmm3, -1U, debugserver_stmm3, NULL, NULL},
-    {e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm4, "stmm4", "st4", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), ehframe_dwarf_stmm4,
      ehframe_dwarf_stmm4, -1U, debugserver_stmm4, NULL, NULL},
-    {e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm5, "stmm5", "st5", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), ehframe_dwarf_stmm5,
      ehframe_dwarf_stmm5, -1U, debugserver_stmm5, NULL, NULL},
-    {e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm6, "stmm6", "st6", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), ehframe_dwarf_stmm6,
      ehframe_dwarf_stmm6, -1U, debugserver_stmm6, NULL, NULL},
-    {e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8,
+    {e_regSetFPU, fpu_stmm7, "stmm7", "st7", Vector, VectorOfUInt8,
      FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), ehframe_dwarf_stmm7,
      ehframe_dwarf_stmm7, -1U, debugserver_stmm7, NULL, NULL},
 
      AVX512_K_REG_DEF(0),
      AVX512_K_REG_DEF(1),
      AVX512_K_REG_DEF(2),
      AVX512_K_REG_DEF(3),
      AVX512_K_REG_DEF(4),