[PowerPC] Fix FLT_ROUNDS_ on little endian

[qiucf]

Summary

Opcode FLT_ROUNDS_ is lowered as:

1. Move FPSCR content to an FP register
2. Move lower 32 bits into a GPR
3. Adjust its value, and return

For subtargets without direct move support, it will store and then load. The load address needs adjustment (+4) only on big-endian targets. This patch fixes it on little-endian and will try direct move instruction first.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8899

Can we use some generic node to express this semantic ? So that , we will handle it automatically. i.e.
x = MFFS
y = bitcast f64 to i64
z = trunc y to i32

[qiucf]

Use bitcast-truncate

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8899

Yes. But the original code needs to be kept for ppc32 (i64 is illegal on that so crash will happen for the bitcast).

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

8942

Is it better to check the type legal for i64 ? We cannot do this for PPC32 is because that, the i64 is not legal and we are not allowed to produce the illegal type during legalizeOp.

8946

Add an assertion here:
assert(hasBigEndianPartOrdering(...))

[qiucf]

Address comments

[steven.zhang]

LGTM now. Thank you for doing this.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (!(ReusingLoad = canReuseLoadAddress(Src, MVT::i32, RLI, DAG))) {
 
       RLI.Ptr = FIdx;
       RLI.Chain = Chain;
       RLI.MPI =
           MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
       RLI.Alignment = Align(4);
     }
 
     MachineMemOperand *MMO =
       MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
                               RLI.Alignment, RLI.AAInfo, RLI.Ranges);
     SDValue Ops[] = { RLI.Chain, RLI.Ptr };
     Ld = DAG.getMemIntrinsicNode(IsSigned ? PPCISD::LFIWAX : PPCISD::LFIWZX, dl,
                                  DAG.getVTList(MVT::f64, MVT::Other), Ops,
                                  MVT::i32, MMO);
     Chain = Ld.getValue(1);
     if (ReusingLoad)
if (IsStrict)
     Chain = FP.getValue(1);
   if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
     if (IsStrict)
       FP = DAG.getNode(ISD::STRICT_FP_ROUND, dl,
                        DAG.getVTList(MVT::f32, MVT::Other),
                        {Chain, FP, DAG.getIntPtrConstant(0, dl)}, Flags);
     else
       FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
                        DAG.getIntPtrConstant(0, dl));
   }
   return FP;
 }
 
 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
                                             SelectionDAG &DAG) const {
   SDLoc dl(Op);
   /*
    The rounding mode is in bits 30:31 of FPSR, and has the following
    settings:
      00 Round to nearest
      01 Round to 0
SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
   EVT VT = Op.getValueType();
   EVT PtrVT = getPointerTy(MF.getDataLayout());
 
   // Save FP Control Word to register
   SDValue Chain = Op.getOperand(0);
   SDValue MFFS = DAG.getNode(PPCISD::MFFS, dl, {MVT::f64, MVT::Other}, Chain);
   Chain = MFFS.getValue(1);
 
+  SDValue CWD;
+  if (isTypeLegal(MVT::i64)) {
+    CWD = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
+                      DAG.getNode(ISD::BITCAST, dl, MVT::i64, MFFS));
+  } else {
     // Save FP register to stack slot
     int SSFI = MF.getFrameInfo().CreateStackObject(8, Align(8), false);
     SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
     Chain = DAG.getStore(Chain, dl, MFFS, StackSlot, MachinePointerInfo());
 
     // Load FP Control Word from low 32 bits of stack slot.
+    assert(hasBigEndianPartOrdering(MVT::i64, MF.getDataLayout()) &&
+           "Stack slot adjustment is valid only on big endian subtargets!");
     SDValue Four = DAG.getConstant(4, dl, PtrVT);
     SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
-  SDValue CWD = DAG.getLoad(MVT::i32, dl, Chain, Addr, MachinePointerInfo());
+    CWD = DAG.getLoad(MVT::i32, dl, Chain, Addr, MachinePointerInfo());
     Chain = CWD.getValue(1);
+  }
 
   // Transform as necessary
   SDValue CWD1 =
     DAG.getNode(ISD::AND, dl, MVT::i32,
                 CWD, DAG.getConstant(3, dl, MVT::i32));
   SDValue CWD2 =
     DAG.getNode(ISD::SRL, dl, MVT::i32,
                 DAG.getNode(ISD::AND, dl, MVT::i32,

llvm/test/CodeGen/PowerPC/frounds.ll

 ; PPC64-NEXT:    stw 3, -8(1)
 ; PPC64-NEXT:    stw 3, -4(1)
 ; PPC64-NEXT:    blr
 ;
 ; PPC64LE-LABEL: foo:
 ; PPC64LE:       # %bb.0: # %entry
 ; PPC64LE-NEXT:    mffs 0
 ; PPC64LE-NEXT:    stfd 0, -16(1)
-; PPC64LE-NEXT:    lwz 3, -12(1)
+; PPC64LE-NEXT:    lwz 3, -16(1)
 ; PPC64LE-NEXT:    not 4, 3
 ; PPC64LE-NEXT:    clrlwi 3, 3, 30
 ; PPC64LE-NEXT:    rlwinm 4, 4, 31, 31, 31
 ; PPC64LE-NEXT:    xor 3, 3, 4
 ; PPC64LE-NEXT:    stw 3, -8(1)
 ; PPC64LE-NEXT:    stw 3, -4(1)
 ; PPC64LE-NEXT:    blr
 ;
 ; DM-LABEL: foo:
 ; DM:       # %bb.0: # %entry
 ; DM-NEXT:    mffs 0
-; DM-NEXT:    stfd 0, -16(1)
-; DM-NEXT:    lwz 3, -12(1)
+; DM-NEXT:    mffprd 3, 0
 ; DM-NEXT:    not 4, 3
 ; DM-NEXT:    clrlwi 3, 3, 30
 ; DM-NEXT:    rlwinm 4, 4, 31, 31, 31
 ; DM-NEXT:    xor 3, 3, 4
 ; DM-NEXT:    stw 3, -8(1)
 ; DM-NEXT:    stw 3, -4(1)
 ; DM-NEXT:    blr
 entry: