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Differential D91458

[NFC][AMDGPU] Document kernel descriptor
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Authored by t-tye on Nov 13 2020, 1:13 PM.

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kzhuravl
scott.linder
b-sumner
rampitec
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rG8605d3134c97: [NFC][AMDGPU] Document kernel descriptor
Summary
  • Document that the kernel descriptor defined is for code object V3. Document that it also applies to earlier code object formats for CP.
  • Document the deprecated bits in kernel descriptor.

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t-tye created this revision.Nov 13 2020, 1:13 PM
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Closed by commit rG8605d3134c97: [NFC][AMDGPU] Document kernel descriptor (authored by t-tye). · Explain Why
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llvm/docs/AMDGPUUsage.rst

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Kernel Descriptor Kernel Descriptor
~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~
A kernel descriptor consists of the information needed by CP to initiate the A kernel descriptor consists of the information needed by CP to initiate the
execution of a kernel, including the entry point address of the machine code execution of a kernel, including the entry point address of the machine code
that implements the kernel. that implements the kernel.
Kernel Descriptor for GFX6-GFX10 Code Object V3 Kernel Descriptor for GFX6-GFX10 (--amdhsa-code-object-version=3)
++++++++++++++++++++++++++++++++ ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=+++++++++
CP microcode requires the Kernel descriptor to be allocated on 64-byte CP microcode requires the Kernel descriptor to be allocated on 64-byte
alignment. alignment.
.. table:: Kernel Descriptor for GFX6-GFX10 The fields used by CP for code objects before V3 also match those specified in
:name: amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
.. table:: Code Object V3 Kernel Descriptor for GFX6-GFX10
:name: amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3
======= ======= =============================== ============================ ======= ======= =============================== ============================
Bits Size Field Name Description Bits Size Field Name Description
======= ======= =============================== ============================ ======= ======= =============================== ============================
31:0 4 bytes GROUP_SEGMENT_FIXED_SIZE The amount of fixed local 31:0 4 bytes GROUP_SEGMENT_FIXED_SIZE The amount of fixed local
address space memory address space memory
required for a work-group required for a work-group
in bytes. This does not in bytes. This does not
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines .. table:: Code Object V3 Kernel Descriptor for GFX6-GFX10
458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-9 458 1 bit ENABLE_WAVEFRONT_SIZE32 GFX6-9
Reserved, must be 0. Reserved, must be 0.
GFX10 GFX10
- If 0 execute in - If 0 execute in
wavefront size 64 mode. wavefront size 64 mode.
- If 1 execute in - If 1 execute in
native wavefront size native wavefront size
32 mode. 32 mode.
463:459 5 bits Reserved, must be 0. 463:459 1 bit Reserved, must be 0.
511:464 6 bytes Reserved, must be 0. 464 1 bit RESERVED_464 Deprecated, must be 0.
467:465 3 bits Reserved, must be 0.
468 1 bit RESERVED_468 Deprecated, must be 0.
469:471 3 bits Reserved, must be 0.
511:472 5 bytes Reserved, must be 0.
512 **Total size 64 bytes.** 512 **Total size 64 bytes.**
======= ==================================================================== ======= ====================================================================
.. ..
.. table:: compute_pgm_rsrc1 for GFX6-GFX10 .. table:: compute_pgm_rsrc1 for GFX6-GFX10
:name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table :name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table
▲ Show 20 Lines • Show All 5,493 Lines • ▼ Show 20 Linesterminated by an ``.end_amdhsa_kernel`` directive.
.. table:: AMDHSA Kernel Assembler Directives .. table:: AMDHSA Kernel Assembler Directives
:name: amdhsa-kernel-directives-table :name: amdhsa-kernel-directives-table
======================================================== =================== ============ =================== ======================================================== =================== ============ ===================
Directive Default Supported On Description Directive Default Supported On Description
======================================================== =================== ============ =================== ======================================================== =================== ============ ===================
``.amdhsa_group_segment_fixed_size`` 0 GFX6-GFX10 Controls GROUP_SEGMENT_FIXED_SIZE in ``.amdhsa_group_segment_fixed_size`` 0 GFX6-GFX10 Controls GROUP_SEGMENT_FIXED_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
``.amdhsa_private_segment_fixed_size`` 0 GFX6-GFX10 Controls PRIVATE_SEGMENT_FIXED_SIZE in ``.amdhsa_private_segment_fixed_size`` 0 GFX6-GFX10 Controls PRIVATE_SEGMENT_FIXED_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in ``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in
:ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_PTR in ``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_PTR in
:ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_QUEUE_PTR in ``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_QUEUE_PTR in
:ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in ``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6-GFX10 Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in
:ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_ID in ``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6-GFX10 Controls ENABLE_SGPR_DISPATCH_ID in
:ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6-GFX10 Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in ``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6-GFX10 Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in
:ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in ``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in
:ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
``.amdhsa_wavefront_size32`` Target GFX10 Controls ENABLE_WAVEFRONT_SIZE32 in ``.amdhsa_wavefront_size32`` Target GFX10 Controls ENABLE_WAVEFRONT_SIZE32 in
Feature :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. Feature :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
Specific Specific
(-wavefrontsize64) (-wavefrontsize64)
``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET in ``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_X in ``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_X in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_Y in ``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6-GFX10 Controls ENABLE_SGPR_WORKGROUP_ID_Y in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
Show All 40 Lines ``.amdhsa_float_denorm_mode_16_64`` 3 GFX6-GFX10 Controls FLOAT_DENORM_MODE_16_64 in
:ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`. :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`.
``.amdhsa_dx10_clamp`` 1 GFX6-GFX10 Controls ENABLE_DX10_CLAMP in ``.amdhsa_dx10_clamp`` 1 GFX6-GFX10 Controls ENABLE_DX10_CLAMP in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
``.amdhsa_ieee_mode`` 1 GFX6-GFX10 Controls ENABLE_IEEE_MODE in ``.amdhsa_ieee_mode`` 1 GFX6-GFX10 Controls ENABLE_IEEE_MODE in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
``.amdhsa_fp16_overflow`` 0 GFX9-GFX10 Controls FP16_OVFL in ``.amdhsa_fp16_overflow`` 0 GFX9-GFX10 Controls FP16_OVFL in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
``.amdhsa_workgroup_processor_mode`` Target GFX10 Controls ENABLE_WGP_MODE in ``.amdhsa_workgroup_processor_mode`` Target GFX10 Controls ENABLE_WGP_MODE in
Feature :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table`. Feature :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table-v3`.
Specific Specific
(-cumode) (-cumode)
``.amdhsa_memory_ordered`` 1 GFX10 Controls MEM_ORDERED in ``.amdhsa_memory_ordered`` 1 GFX10 Controls MEM_ORDERED in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
``.amdhsa_forward_progress`` 0 GFX10 Controls FWD_PROGRESS in ``.amdhsa_forward_progress`` 0 GFX10 Controls FWD_PROGRESS in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx10-table`.
``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in ``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6-GFX10 Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in
:ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`. :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx10-table`.
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