[AMDGPU] Define and use names for export targets. NFC.

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPU.h

284 ↗

(On Diff #304606)

It is better to live in the SIDefines.h. That encoding fields all live there.

[foad]

Move to SIDefines.h.

[foad]

One more use of the new names.

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/AMDGPUExportClustering.cpp

 
 static bool isExport(const SUnit &SU) {
   return SIInstrInfo::isEXP(*SU.getInstr());
 }
 
 static bool isPositionExport(const SIInstrInfo *TII, SUnit *SU) {
   const MachineInstr *MI = SU->getInstr();
   int Imm = TII->getNamedOperand(*MI, AMDGPU::OpName::tgt)->getImm();
-  return Imm >= 12 && Imm <= 15;
+  return Imm >= AMDGPU::Exp::ET_POS0 && Imm <= AMDGPU::Exp::ET_POS3;
 }
 
 static void sortChain(const SIInstrInfo *TII, SmallVector<SUnit *, 8> &Chain,
                       unsigned PosCount) {
   if (!PosCount || PosCount == Chain.size())
     return;
 
   // Position exports should occur as soon as possible in the shader

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 
 //===----------------------------------------------------------------------===//
 // exp
 //===----------------------------------------------------------------------===//
 
 OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str,
                                                       uint8_t &Val) {
   if (Str == "null") {
-    Val = 9;
+    Val = Exp::ET_NULL;
     return MatchOperand_Success;
   }
 
   if (Str.startswith("mrt")) {
     Str = Str.drop_front(3);
     if (Str == "z") { // == mrtz
-      Val = 8;
+      Val = Exp::ET_MRTZ;
       return MatchOperand_Success;
     }
 
     if (Str.getAsInteger(10, Val))
       return MatchOperand_ParseFail;
 
-    if (Val > 7)
+    if (Val > Exp::ET_MRT7)
       return MatchOperand_ParseFail;
 
     return MatchOperand_Success;
   }
 
   if (Str.startswith("pos")) {
     Str = Str.drop_front(3);
     if (Str.getAsInteger(10, Val))
       return MatchOperand_ParseFail;
 
-    if (Val > 4 || (Val == 4 && !isGFX10()))
+    if (Val > (isGFX10() ? 4 : 3))
       return MatchOperand_ParseFail;
 
-    Val += 12;
+    Val += Exp::ET_POS0;
     return MatchOperand_Success;
   }
 
   if (isGFX10() && Str == "prim") {
-    Val = 20;
+    Val = Exp::ET_PRIM;
     return MatchOperand_Success;
   }
 
   if (Str.startswith("param")) {
     Str = Str.drop_front(5);
     if (Str.getAsInteger(10, Val))
       return MatchOperand_ParseFail;
 
     if (Val >= 32)
       return MatchOperand_ParseFail;
 
-    Val += 32;
+    Val += Exp::ET_PARAM0;
     return MatchOperand_Success;
   }
 
   return MatchOperand_ParseFail;
 }
 
 OperandMatchResultTy AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {
   if (!isToken(AsmToken::Identifier))

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

 }
 
 void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
                                     const MCSubtargetInfo &STI,
                                     raw_ostream &O) {
   // This is really a 6 bit field.
   uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
 
-  if (Tgt <= 7)
-    O << " mrt" << Tgt;
-  else if (Tgt == 8)
+  if (Tgt <= Exp::ET_MRT7)
+    O << " mrt" << Tgt - Exp::ET_MRT0;
+  else if (Tgt == Exp::ET_MRTZ)
     O << " mrtz";
-  else if (Tgt == 9)
+  else if (Tgt == Exp::ET_NULL)
     O << " null";
-  else if ((Tgt >= 12 && Tgt <= 15) || (Tgt == 16 && AMDGPU::isGFX10(STI)))
-    O << " pos" << Tgt - 12;
-  else if (AMDGPU::isGFX10(STI) && Tgt == 20)
+  else if (Tgt >= Exp::ET_POS0 &&
+           Tgt <= (isGFX10(STI) ? Exp::ET_POS4 : Exp::ET_POS3))
+    O << " pos" << Tgt - Exp::ET_POS0;
+  else if (isGFX10(STI) && Tgt == Exp::ET_PRIM)
     O << " prim";
-  else if (Tgt >= 32 && Tgt <= 63)
-    O << " param" << Tgt - 32;
+  else if (Tgt >= Exp::ET_PARAM0 && Tgt <= Exp::ET_PARAM31)
+    O << " param" << Tgt - Exp::ET_PARAM0;
   else {
     // Reserved values 10, 11
     O << " invalid_target_" << Tgt;
   }
 }
 
 static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
                                bool IsPacked, bool HasDstSel) {

llvm/lib/Target/AMDGPU/SIDefines.h

 enum DppFiMode {
   DPP_FI_0  = 0,
   DPP_FI_1  = 1,
   DPP8_FI_0 = 0xE9,
   DPP8_FI_1 = 0xEA,
 };
 
 } // namespace DPP
+
+namespace Exp {
+
+enum Target {
+  ET_MRT0 = 0,
+  ET_MRT7 = 7,
+  ET_MRTZ = 8,
+  ET_NULL = 9,
+  ET_POS0 = 12,
+  ET_POS3 = 15,
+  ET_POS4 = 16, // GFX10+
+  ET_PRIM = 20, // GFX10+
+  ET_PARAM0 = 32,
+  ET_PARAM31 = 63,
+};
+
+} // namespace Exp
 } // namespace AMDGPU
 
 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS                                0x00B028
 #define   S_00B028_VGPRS(x)                                           (((x) & 0x3F) << 0)
 #define   S_00B028_SGPRS(x)                                           (((x) & 0x0F) << 6)
 #define   S_00B028_MEM_ORDERED(x)                                     (((x) & 0x1) << 25)
 #define   G_00B028_MEM_ORDERED(x)                                     (((x) >> 25) & 0x1)
 #define   C_00B028_MEM_ORDERED                                        0xFDFFFFFF

llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

if (callWaitsOnFunctionReturn(Inst)) {
       // Act as a wait on everything
       ScoreBrackets->applyWaitcnt(AMDGPU::Waitcnt::allZero(ST->hasVscnt()));
     } else {
       // May need to way wait for anything.
       ScoreBrackets->applyWaitcnt(AMDGPU::Waitcnt());
     }
   } else if (SIInstrInfo::isEXP(Inst)) {
     int Imm = TII->getNamedOperand(Inst, AMDGPU::OpName::tgt)->getImm();
-    if (Imm >= 32 && Imm <= 63)
+    if (Imm >= AMDGPU::Exp::ET_PARAM0 && Imm <= AMDGPU::Exp::ET_PARAM31)
       ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_PARAM_ACCESS, Inst);
-    else if (Imm >= 12 && Imm <= 15)
+    else if (Imm >= AMDGPU::Exp::ET_POS0 && Imm <= AMDGPU::Exp::ET_POS3)
       ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_POS_ACCESS, Inst);
     else
       ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_GPR_LOCK, Inst);
   } else {
     switch (Inst.getOpcode()) {
     case AMDGPU::S_SENDMSG:
     case AMDGPU::S_SENDMSGHALT:
       ScoreBrackets->updateByEvent(TII, TRI, MRI, SQ_MESSAGE, Inst);