[AArch64] Add check for widening instruction for SVE.

[CarolineConcatto]

Summary

This patch fixes the function isWideningInstruction for scalable vectors.
Now the cost model can check the widening pattern for SVE.

[CarolineConcatto]

• add a warning check in the llvm test

[sdesmalen]

Looks good to me! Cheers @CarolineConcatto

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

 }
 
 bool AArch64TTIImpl::isWideningInstruction(Type *DstTy, unsigned Opcode,
                                            ArrayRef<const Value *> Args) {
 
   // A helper that returns a vector type from the given type. The number of
   // elements in type Ty determine the vector width.
   auto toVectorTy = [&](Type *ArgTy) {
-    return FixedVectorType::get(ArgTy->getScalarType(),
-                                cast<FixedVectorType>(DstTy)->getNumElements());
+    return VectorType::get(ArgTy->getScalarType(),
+                           cast<VectorType>(DstTy)->getElementCount());
   };
 
   // Exit early if DstTy is not a vector type whose elements are at least
   // 16-bits wide.
   if (!DstTy->isVectorTy() || DstTy->getScalarSizeInBits() < 16)
     return false;
 
   // Determine if the operation has a widening variant. We consider both the
bool AArch64TTIImpl::isWideningInstruction(Type *DstTy, unsigned Opcode,
   // operation.
   auto *SrcTy = toVectorTy(Extend->getSrcTy());
   auto SrcTyL = TLI->getTypeLegalizationCost(DL, SrcTy);
   unsigned SrcElTySize = SrcTyL.second.getScalarSizeInBits();
   if (!SrcTyL.second.isVector() || SrcElTySize != SrcTy->getScalarSizeInBits())
     return false;
 
   // Get the total number of vector elements in the legalized types.
-  unsigned NumDstEls = DstTyL.first * DstTyL.second.getVectorNumElements();
-  unsigned NumSrcEls = SrcTyL.first * SrcTyL.second.getVectorNumElements();
+  unsigned NumDstEls = DstTyL.first * DstTyL.second.getVectorMinNumElements();
+  unsigned NumSrcEls = SrcTyL.first * SrcTyL.second.getVectorMinNumElements();
 
   // Return true if the legalized types have the same number of vector elements
   // and the destination element type size is twice that of the source type.
   return NumDstEls == NumSrcEls && 2 * SrcElTySize == DstElTySize;
 }
 
 int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
                                      TTI::CastContextHint CCH,

llvm/test/Analysis/CostModel/AArch64/sve-widening-instruction.ll

+; Checks if widening instructions works for SVE
+
+; RUN: opt  -cost-model -analyze -mtriple=aarch64--linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
+
+define <vscale x 4 x i32> @widening(<vscale x 16 x i8> %in, <vscale x 4 x i16> %in2) {
+
+; CHECK-LABEL: 'widening':
+; CHECK: Cost Model: Found an estimated cost of {{[0-9]+}} for instruction:   %in.bc = bitcast <vscale x 16 x i8> %in to <vscale x 4 x i32>
+; CHECK-NEXT: Cost Model: Found an estimated cost of {{[0-9]+}} for instruction:   %in2.ext = zext <vscale x 4 x i16> %in2 to <vscale x 4 x i32>
+; CHECK-NEXT: Cost Model: Found an estimated cost of {{[0-9]+}} for instruction:   %in.add = add <vscale x 4 x i32> %in.bc, %in2.ext
+; CHECK-NEXT: Cost Model: Found an estimated cost of {{[0-9]+}} for instruction:   ret <vscale x 4 x i32> %in.add
+
+  %in.bc = bitcast <vscale x 16 x i8> %in to <vscale x 4 x i32>
+  %in2.ext = zext <vscale x 4 x i16> %in2 to <vscale x 4 x i32>
+  %in.add = add <vscale x 4 x i32> %in.bc, %in2.ext
+  ret <vscale x 4 x i32> %in.add
+}