[PowerPC] Add the hw sqrt test for vector type v4f32/v2f64

[steven.zhang]

Summary

PowerPC ISA support the input test for vector type v4f32 and v2f64. Replace the software compare with hw test will improve the perf.

[shchenz]

LGTM

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget) {
   int RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
   if (VT.getScalarType() == MVT::f64)
     RefinementSteps++;
   return RefinementSteps;
 }
 
 SDValue PPCTargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG,
                                             const DenormalMode &Mode) const {
-  // TODO - add support for v2f64/v4f32
+  // We only have VSX Vector Test for software Square Root.
   EVT VT = Op.getValueType();
-  if (VT != MVT::f64)
+  if (VT != MVT::f64 &&
+      ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX()))
     return SDValue();
 
   SDLoc DL(Op);
   // The output register of FTSQRT is CR field.
   SDValue FTSQRT = DAG.getNode(PPCISD::FTSQRT, DL, MVT::i32, Op);
   // ftsqrt BF,FRB
   // Let e_b be the unbiased exponent of the double-precision
   // floating-point operand in register FRB.
SDValue PPCTargetLowering::getSqrtInputTest(SDValue Op, SelectionDAG &DAG,
   return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i1,
                                     FTSQRT, SRIdxVal),
                  0);
 }
 
 SDValue
 PPCTargetLowering::getSqrtResultForDenormInput(SDValue Op,
                                                SelectionDAG &DAG) const {
-  // TODO - add support for v2f64/v4f32
+  // We only have VSX Vector Square Root.
   EVT VT = Op.getValueType();
-  if (VT != MVT::f64)
+  if (VT != MVT::f64 &&
+      ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX()))
     return TargetLowering::getSqrtResultForDenormInput(Op, DAG);
 
   return DAG.getNode(PPCISD::FSQRT, SDLoc(Op), VT, Op);
 }
 
 SDValue PPCTargetLowering::getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
                                            int Enabled, int &RefinementSteps,
                                            bool &UseOneConstNR,

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def XVTDIVDP : XX3Form_1<60, 125,
                          (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
                          "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
   def XVTDIVSP : XX3Form_1<60, 93,
                          (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
                          "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>;
 
   def XVTSQRTDP : XX2Form_1<60, 234,
                           (outs crrc:$crD), (ins vsrc:$XB),
-                          "xvtsqrtdp $crD, $XB", IIC_FPCompare, []>;
+                          "xvtsqrtdp $crD, $XB", IIC_FPCompare,
+                          [(set i32:$crD, (PPCftsqrt v2f64:$XB))]>;
   def XVTSQRTSP : XX2Form_1<60, 170,
                           (outs crrc:$crD), (ins vsrc:$XB),
-                          "xvtsqrtsp $crD, $XB", IIC_FPCompare, []>;
+                          "xvtsqrtsp $crD, $XB", IIC_FPCompare,
+                          [(set i32:$crD, (PPCftsqrt v4f32:$XB))]>;
   }
 
   def XVDIVDP : XX3Form<60, 120,
                         (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                         "xvdivdp $XT, $XA, $XB", IIC_FPDivD,
                         [(set v2f64:$XT, (any_fdiv v2f64:$XA, v2f64:$XB))]>;
   def XVDIVSP : XX3Form<60, 88,
                         (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),

 def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C),
           (XVNMSUBASP $C, $A, $B)>;
 def : Pat<(fneg (PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C)),
           (XVMSUBASP $C, $A, $B)>;
 def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, (fneg v4f32:$C)),
           (XVNMADDASP $C, $A, $B)>;
 
 def : Pat<(PPCfsqrt f64:$frA), (XSSQRTDP $frA)>;
+def : Pat<(PPCfsqrt v2f64:$frA), (XVSQRTDP $frA)>;
+def : Pat<(PPCfsqrt v4f32:$frA), (XVSQRTSP $frA)>;
 
 def : Pat<(v2f64 (bitconvert v4f32:$A)),
           (COPY_TO_REGCLASS $A, VSRC)>;
 def : Pat<(v2f64 (bitconvert v4i32:$A)),
           (COPY_TO_REGCLASS $A, VSRC)>;
 def : Pat<(v2f64 (bitconvert v8i16:$A)),
           (COPY_TO_REGCLASS $A, VSRC)>;
 def : Pat<(v2f64 (bitconvert v16i8:$A)),

llvm/test/CodeGen/PowerPC/recipest.ll

 ; CHECK-P7-NEXT:    vxor 0, 0, 0
 ; CHECK-P7-NEXT:    vmaddfp 3, 5, 4, 3
 ; CHECK-P7-NEXT:    vcmpeqfp 2, 2, 0
 ; CHECK-P7-NEXT:    vsel 2, 3, 0, 2
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo3_fmf:
 ; CHECK-P8:       # %bb.0:
+; CHECK-P8-NEXT:    xvtsqrtsp 0, 34
+; CHECK-P8-NEXT:    bc 12, 2, .LBB24_2
+; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xvrsqrtesp 0, 34
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI24_0@toc@ha
 ; CHECK-P8-NEXT:    addis 4, 2, .LCPI24_1@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI24_0@toc@l
-; CHECK-P8-NEXT:    lvx 3, 0, 3
-; CHECK-P8-NEXT:    addi 3, 4, .LCPI24_1@toc@l
-; CHECK-P8-NEXT:    lvx 4, 0, 3
 ; CHECK-P8-NEXT:    xvmulsp 1, 34, 0
-; CHECK-P8-NEXT:    xvmaddasp 35, 1, 0
-; CHECK-P8-NEXT:    xvmulsp 0, 1, 36
-; CHECK-P8-NEXT:    xxlxor 1, 1, 1
-; CHECK-P8-NEXT:    xvcmpeqsp 2, 34, 1
-; CHECK-P8-NEXT:    xvmulsp 0, 0, 35
-; CHECK-P8-NEXT:    xxsel 34, 0, 1, 2
+; CHECK-P8-NEXT:    lvx 2, 0, 3
+; CHECK-P8-NEXT:    addi 3, 4, .LCPI24_1@toc@l
+; CHECK-P8-NEXT:    lvx 3, 0, 3
+; CHECK-P8-NEXT:    xvmaddasp 34, 1, 0
+; CHECK-P8-NEXT:    xvmulsp 0, 1, 35
+; CHECK-P8-NEXT:    xvmulsp 34, 0, 34
+; CHECK-P8-NEXT:    blr
+; CHECK-P8-NEXT:  .LBB24_2:
+; CHECK-P8-NEXT:    xvsqrtsp 34, 34
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo3_fmf:
 ; CHECK-P9:       # %bb.0:
+; CHECK-P9-NEXT:    xvtsqrtsp 0, 34
+; CHECK-P9-NEXT:    bc 12, 2, .LBB24_2
+; CHECK-P9-NEXT:  # %bb.1:
 ; CHECK-P9-NEXT:    xvrsqrtesp 0, 34
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI24_0@toc@ha
 ; CHECK-P9-NEXT:    addi 3, 3, .LCPI24_0@toc@l
 ; CHECK-P9-NEXT:    lxvx 2, 0, 3
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI24_1@toc@ha
 ; CHECK-P9-NEXT:    addi 3, 3, .LCPI24_1@toc@l
 ; CHECK-P9-NEXT:    xvmulsp 1, 34, 0
 ; CHECK-P9-NEXT:    xvmaddasp 2, 1, 0
 ; CHECK-P9-NEXT:    lxvx 0, 0, 3
 ; CHECK-P9-NEXT:    xvmulsp 0, 1, 0
-; CHECK-P9-NEXT:    xxlxor 1, 1, 1
-; CHECK-P9-NEXT:    xvmulsp 0, 0, 2
-; CHECK-P9-NEXT:    xvcmpeqsp 2, 34, 1
-; CHECK-P9-NEXT:    xxsel 34, 0, 1, 2
+; CHECK-P9-NEXT:    xvmulsp 34, 0, 2
+; CHECK-P9-NEXT:    blr
+; CHECK-P9-NEXT:  .LBB24_2:
+; CHECK-P9-NEXT:    xvsqrtsp 34, 34
 ; CHECK-P9-NEXT:    blr
   %r = call reassoc ninf afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %r
 }
 
 define <4 x float> @hoo3_safe(<4 x float> %a) nounwind {
 ; CHECK-P7-LABEL: hoo3_safe:
 ; CHECK-P7:       # %bb.0:

 ; CHECK-P7-NEXT:    fmul 2, 2, 4
 ; CHECK-P7-NEXT:    fmadd 3, 2, 4, 3
 ; CHECK-P7-NEXT:    fmul 0, 2, 0
 ; CHECK-P7-NEXT:    fmul 2, 0, 3
 ; CHECK-P7-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: hoo4_fmf:
 ; CHECK-P8:       # %bb.0:
+; CHECK-P8-NEXT:    xvtsqrtdp 0, 34
+; CHECK-P8-NEXT:    bc 12, 2, .LBB26_2
+; CHECK-P8-NEXT:  # %bb.1:
 ; CHECK-P8-NEXT:    xvrsqrtedp 0, 34
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI26_0@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI26_0@toc@l
 ; CHECK-P8-NEXT:    lxvd2x 1, 0, 3
 ; CHECK-P8-NEXT:    addis 3, 2, .LCPI26_1@toc@ha
 ; CHECK-P8-NEXT:    addi 3, 3, .LCPI26_1@toc@l
 ; CHECK-P8-NEXT:    lxvd2x 3, 0, 3
 ; CHECK-P8-NEXT:    xxswapd 1, 1
 ; CHECK-P8-NEXT:    xvmuldp 2, 34, 0
 ; CHECK-P8-NEXT:    xxswapd 3, 3
 ; CHECK-P8-NEXT:    xxlor 4, 1, 1
 ; CHECK-P8-NEXT:    xvmaddadp 4, 2, 0
 ; CHECK-P8-NEXT:    xvmuldp 0, 0, 3
 ; CHECK-P8-NEXT:    xvmuldp 0, 0, 4
 ; CHECK-P8-NEXT:    xvmuldp 2, 34, 0
 ; CHECK-P8-NEXT:    xvmaddadp 1, 2, 0
 ; CHECK-P8-NEXT:    xvmuldp 0, 2, 3
-; CHECK-P8-NEXT:    xxlxor 2, 2, 2
-; CHECK-P8-NEXT:    xvcmpeqdp 34, 34, 2
-; CHECK-P8-NEXT:    xvmuldp 0, 0, 1
-; CHECK-P8-NEXT:    xxsel 34, 0, 2, 34
+; CHECK-P8-NEXT:    xvmuldp 34, 0, 1
+; CHECK-P8-NEXT:    blr
+; CHECK-P8-NEXT:  .LBB26_2:
+; CHECK-P8-NEXT:    xvsqrtdp 34, 34
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo4_fmf:
 ; CHECK-P9:       # %bb.0:
+; CHECK-P9-NEXT:    xvtsqrtdp 0, 34
+; CHECK-P9-NEXT:    bc 12, 2, .LBB26_2
+; CHECK-P9-NEXT:  # %bb.1:
 ; CHECK-P9-NEXT:    xvrsqrtedp 0, 34
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI26_0@toc@ha
 ; CHECK-P9-NEXT:    addi 3, 3, .LCPI26_0@toc@l
 ; CHECK-P9-NEXT:    lxvx 2, 0, 3
 ; CHECK-P9-NEXT:    addis 3, 2, .LCPI26_1@toc@ha
 ; CHECK-P9-NEXT:    addi 3, 3, .LCPI26_1@toc@l
 ; CHECK-P9-NEXT:    xvmuldp 1, 34, 0
 ; CHECK-P9-NEXT:    xxlor 3, 2, 2
 ; CHECK-P9-NEXT:    xvmaddadp 3, 1, 0
 ; CHECK-P9-NEXT:    lxvx 1, 0, 3
 ; CHECK-P9-NEXT:    xvmuldp 0, 0, 1
 ; CHECK-P9-NEXT:    xvmuldp 0, 0, 3
 ; CHECK-P9-NEXT:    xvmuldp 3, 34, 0
 ; CHECK-P9-NEXT:    xvmaddadp 2, 3, 0
 ; CHECK-P9-NEXT:    xvmuldp 0, 3, 1
-; CHECK-P9-NEXT:    xxlxor 1, 1, 1
-; CHECK-P9-NEXT:    xvcmpeqdp 34, 34, 1
-; CHECK-P9-NEXT:    xvmuldp 0, 0, 2
-; CHECK-P9-NEXT:    xxsel 34, 0, 1, 34
+; CHECK-P9-NEXT:    xvmuldp 34, 0, 2
+; CHECK-P9-NEXT:    blr
+; CHECK-P9-NEXT:  .LBB26_2:
+; CHECK-P9-NEXT:    xvsqrtdp 34, 34
 ; CHECK-P9-NEXT:    blr
   %r = call reassoc ninf afn <2 x double> @llvm.sqrt.v2f64(<2 x double> %a)
   ret <2 x double> %r
 }
 
 define <2 x double> @hoo4_safe(<2 x double> %a) #1 {
 ; CHECK-P7-LABEL: hoo4_safe:
 ; CHECK-P7:       # %bb.0: